tree 01e7b3ee30568491cc461c1c36ac6adef591388a
parent e36bd9c6c99f47902d6fd6804730aa587ae275a0
author Ulf Hansson <ulf.hansson@linaro.org> 1378281675 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1379617944 +0100

ARM: 7833/1: mmc: mmci: Adapt to register write restrictions

After a write to the MMCICLOCK register data cannot be written to this
register for three feedback clock cycles. Writes to the MMCIPOWER
register must be separated by three MCLK cycles. Previously no issues
has been observered, but using higher ARM clock frequencies on STE-
platforms has triggered this problem.

The MMCICLOCK register is written to in .set_ios and for some data
transmissions for SDIO. We do not need a delay at the data transmission
path, because sending and receiving data will require more than three
clock cycles. Then we use a simple logic to only delay in .set_ios and
thus we don't affect throughput performance.

Signed-off-by: Johan Rudholm <jrudholm@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Rickard Andersson <rickard.andersson@stericsson.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>