ARM: S5P64X0: Change to using s3c_gpio_cfgall_range()
Change the code setting a range of GPIO pins' configuration and
pull state to use the recently introduced s3c_gpio_cfgall_range().
Mop up a few missed s3c_gpio_cfgpin_range() changes.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index be64fee..e78ee18 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -44,16 +44,10 @@
switch (pdev->id) {
case 0:
base = S5P6440_GPC(0);
- s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
break;
case 1:
base = S5P6440_GPC(4);
- s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
break;
default:
@@ -61,7 +55,8 @@
return -EINVAL;
}
- s3c_gpio_cfgpin_range(base, 3, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgall_range(base, 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
@@ -73,16 +68,10 @@
switch (pdev->id) {
case 0:
base = S5P6450_GPC(0);
- s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
break;
case 1:
base = S5P6450_GPC(4);
- s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
break;
default:
@@ -90,7 +79,8 @@
return -EINVAL;
}
- s3c_gpio_cfgpin_range(base, 3, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgall_range(base, 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}