| commit | fa0406a8d8c3a4a302085ccd031d999161405f70 | [log] [tgz] |
|---|---|---|
| author | Paul Walmsley <paul@pwsan.com> | Tue May 12 17:27:09 2009 -0600 |
| committer | paul <paul@twilight.(none)> | Tue May 12 17:27:09 2009 -0600 |
| tree | bc37051ba47599b871a0f438070821f8c4bbf0ea | |
| parent | d75d9e73cd59127a4d926a2bf5e9cdcc90f033d6 [diff] |
OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh mode. This prevents the SDRC from attempting to power off the SDRAM, which can cause the system to hang. Signed-off-by: Paul Walmsley <paul@pwsan.com>