| commit | fa4d0ca104bfdcda7b7e2bac855b358f302fd310 | [log] [tgz] |
|---|---|---|
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | Wed Mar 23 17:38:26 2016 +0100 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Fri Apr 22 00:29:23 2016 +0200 |
| tree | 14c68c6b45413a4281a7d53af3b84564400a4bf1 | |
| parent | 7f2ea3847d47d49929d41573a3b26c80ddebbef5 [diff] |
clk: sunxi: Add PLL3 clock The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>