tree b917d0fc5d38dc845c197e46fb9ff6c60d66fb0f
parent ae74ac0828868af3295395be7bc892e0d0aba376
parent 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4
author Stephen Boyd <sboyd@codeaurora.org> 1509486741 -0700
committer Stephen Boyd <sboyd@codeaurora.org> 1509486741 -0700
mergetag object 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4
 type commit
 tag sunxi-clk-for-4.15
 tagger Maxime Ripard <maxime.ripard@free-electrons.com> 1508485125 +0200
 
 Allwinner clock changes for 4.15
 
 The most notable changes are:
   - Addition of sigma/delta modulation for the audio PLLs on the newer SoCs
   - A83t Display clocks supports
 
 There's also a bunch of minor fixes that didn't have any impact on current
 features provided by the kernel.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJZ6ahsAAoJEBx+YmzsjxAgtvAQALfAX8+9HfJ7dk84s2qhLoZ6
 LsTujOAzUSWgOFDRhHK5vkqzq4GMqL+Tum57g7Sa7iStkYjSjtqDoMG3ajvehm1L
 rGqilZFMLSiOGiV2sQXmA8EANVjqNH6jeOc6Szwo7e0tqw5FC27TjN3jNHAAmd0z
 B9dmKQSaquMfHa+ldtOSmUjitY1uwq4dKdxuZrCxBVcgjJEwYuXOVCCioUN+d+/j
 ZRkcsoROW48FqVcsu9wONGYJxgKMVfkOR6P4QuTOfrw5Flvj5DZPYKMk0c2hYcEh
 FfSFJU7kq43dEIzD2sS4o17RTtoJQz8pO7qQ6TwL23sgtZuxvUKofhnSFbe7OV3P
 nqqiaDXEayjxNYD+aN4hpKBdK6rml9bhO8d1Y4d3dgFTdP3jhbsbO3CQebbzTKTs
 /KLyYKG3G7r3BrvY7XfrSRT1q68mp9O8GFxUMXCGwcESiqyBFLoDX32+25fZumtg
 2wADvSyTBHViJDsgHaJFuzG0rOKQLxVW2VUce3RFlFZAUCxZ9ZMrSj8ANhGfCqJ9
 RH9dpTVPVw1fPl1Lpx9ZLz9sE5Y+rQXn18etyV04rTuW9nlAQqua5wLicGEAz3Dq
 bln44RgngxpQk/0/O77Q6U+7F9gUdowwri+1m2m0s73xNjAUAE42SuCnuFZz7P3L
 4i58+Nv/CU9H98ew4TRR
 =4mo5
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock driver updates from Maxime Ripard:

  - Addition of sigma/delta modulation for the audio PLLs on the newer SoCs
  - A83t Display clocks supports
  - minor fixes that didn't have any impact on current features

* tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun4i: Export video PLLs
  clk: sunxi-ng: Add A83T display clocks
  clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun4i: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: nm: Add support for sigma-delta modulation
  clk: sunxi-ng: Add sigma-delta modulation support
  clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock
  clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider
  clk: sunxi-ng: a83t: Fix invalid csi-mclk mux offset
  clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision
  clk: sunxi-ng: sun6i: Export video PLLs
  clk: sunxi-ng: Implement reset control status readback
  clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.c
  clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
  clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs