Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright 2008 (c) Intel Corporation |
| 4 | * Jesse Barnes <jbarnes@virtuousgeek.org> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
| 28 | #include "drm.h" |
| 29 | #include "i915_drm.h" |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 30 | #include "intel_drv.h" |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 31 | |
| 32 | static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) |
| 33 | { |
| 34 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 35 | u32 dpll_reg; |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 37 | if (HAS_PCH_SPLIT(dev)) |
| 38 | dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B; |
| 39 | else |
| 40 | dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 41 | |
| 42 | return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | static void i915_save_palette(struct drm_device *dev, enum pipe pipe) |
| 46 | { |
| 47 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 48 | unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 49 | u32 *array; |
| 50 | int i; |
| 51 | |
| 52 | if (!i915_pipe_enabled(dev, pipe)) |
| 53 | return; |
| 54 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 55 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 56 | reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 57 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 58 | if (pipe == PIPE_A) |
| 59 | array = dev_priv->save_palette_a; |
| 60 | else |
| 61 | array = dev_priv->save_palette_b; |
| 62 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame^] | 63 | for (i = 0; i < 256; i++) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 64 | array[i] = I915_READ(reg + (i << 2)); |
| 65 | } |
| 66 | |
| 67 | static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) |
| 68 | { |
| 69 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 70 | unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 71 | u32 *array; |
| 72 | int i; |
| 73 | |
| 74 | if (!i915_pipe_enabled(dev, pipe)) |
| 75 | return; |
| 76 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 77 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 78 | reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 79 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 80 | if (pipe == PIPE_A) |
| 81 | array = dev_priv->save_palette_a; |
| 82 | else |
| 83 | array = dev_priv->save_palette_b; |
| 84 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame^] | 85 | for (i = 0; i < 256; i++) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 86 | I915_WRITE(reg + (i << 2), array[i]); |
| 87 | } |
| 88 | |
| 89 | static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) |
| 90 | { |
| 91 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 92 | |
| 93 | I915_WRITE8(index_port, reg); |
| 94 | return I915_READ8(data_port); |
| 95 | } |
| 96 | |
| 97 | static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) |
| 98 | { |
| 99 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 100 | |
| 101 | I915_READ8(st01); |
| 102 | I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); |
| 103 | return I915_READ8(VGA_AR_DATA_READ); |
| 104 | } |
| 105 | |
| 106 | static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) |
| 107 | { |
| 108 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 109 | |
| 110 | I915_READ8(st01); |
| 111 | I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); |
| 112 | I915_WRITE8(VGA_AR_DATA_WRITE, val); |
| 113 | } |
| 114 | |
| 115 | static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) |
| 116 | { |
| 117 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 118 | |
| 119 | I915_WRITE8(index_port, reg); |
| 120 | I915_WRITE8(data_port, val); |
| 121 | } |
| 122 | |
| 123 | static void i915_save_vga(struct drm_device *dev) |
| 124 | { |
| 125 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 126 | int i; |
| 127 | u16 cr_index, cr_data, st01; |
| 128 | |
| 129 | /* VGA color palette registers */ |
| 130 | dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 131 | |
| 132 | /* MSR bits */ |
| 133 | dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); |
| 134 | if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { |
| 135 | cr_index = VGA_CR_INDEX_CGA; |
| 136 | cr_data = VGA_CR_DATA_CGA; |
| 137 | st01 = VGA_ST01_CGA; |
| 138 | } else { |
| 139 | cr_index = VGA_CR_INDEX_MDA; |
| 140 | cr_data = VGA_CR_DATA_MDA; |
| 141 | st01 = VGA_ST01_MDA; |
| 142 | } |
| 143 | |
| 144 | /* CRT controller regs */ |
| 145 | i915_write_indexed(dev, cr_index, cr_data, 0x11, |
| 146 | i915_read_indexed(dev, cr_index, cr_data, 0x11) & |
| 147 | (~0x80)); |
| 148 | for (i = 0; i <= 0x24; i++) |
| 149 | dev_priv->saveCR[i] = |
| 150 | i915_read_indexed(dev, cr_index, cr_data, i); |
| 151 | /* Make sure we don't turn off CR group 0 writes */ |
| 152 | dev_priv->saveCR[0x11] &= ~0x80; |
| 153 | |
| 154 | /* Attribute controller registers */ |
| 155 | I915_READ8(st01); |
| 156 | dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); |
| 157 | for (i = 0; i <= 0x14; i++) |
| 158 | dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); |
| 159 | I915_READ8(st01); |
| 160 | I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); |
| 161 | I915_READ8(st01); |
| 162 | |
| 163 | /* Graphics controller registers */ |
| 164 | for (i = 0; i < 9; i++) |
| 165 | dev_priv->saveGR[i] = |
| 166 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); |
| 167 | |
| 168 | dev_priv->saveGR[0x10] = |
| 169 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); |
| 170 | dev_priv->saveGR[0x11] = |
| 171 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); |
| 172 | dev_priv->saveGR[0x18] = |
| 173 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); |
| 174 | |
| 175 | /* Sequencer registers */ |
| 176 | for (i = 0; i < 8; i++) |
| 177 | dev_priv->saveSR[i] = |
| 178 | i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); |
| 179 | } |
| 180 | |
| 181 | static void i915_restore_vga(struct drm_device *dev) |
| 182 | { |
| 183 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 184 | int i; |
| 185 | u16 cr_index, cr_data, st01; |
| 186 | |
| 187 | /* MSR bits */ |
| 188 | I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); |
| 189 | if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { |
| 190 | cr_index = VGA_CR_INDEX_CGA; |
| 191 | cr_data = VGA_CR_DATA_CGA; |
| 192 | st01 = VGA_ST01_CGA; |
| 193 | } else { |
| 194 | cr_index = VGA_CR_INDEX_MDA; |
| 195 | cr_data = VGA_CR_DATA_MDA; |
| 196 | st01 = VGA_ST01_MDA; |
| 197 | } |
| 198 | |
| 199 | /* Sequencer registers, don't write SR07 */ |
| 200 | for (i = 0; i < 7; i++) |
| 201 | i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, |
| 202 | dev_priv->saveSR[i]); |
| 203 | |
| 204 | /* CRT controller regs */ |
| 205 | /* Enable CR group 0 writes */ |
| 206 | i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); |
| 207 | for (i = 0; i <= 0x24; i++) |
| 208 | i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); |
| 209 | |
| 210 | /* Graphics controller regs */ |
| 211 | for (i = 0; i < 9; i++) |
| 212 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, |
| 213 | dev_priv->saveGR[i]); |
| 214 | |
| 215 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, |
| 216 | dev_priv->saveGR[0x10]); |
| 217 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, |
| 218 | dev_priv->saveGR[0x11]); |
| 219 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, |
| 220 | dev_priv->saveGR[0x18]); |
| 221 | |
| 222 | /* Attribute controller registers */ |
| 223 | I915_READ8(st01); /* switch back to index mode */ |
| 224 | for (i = 0; i <= 0x14; i++) |
| 225 | i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); |
| 226 | I915_READ8(st01); /* switch back to index mode */ |
| 227 | I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); |
| 228 | I915_READ8(st01); |
| 229 | |
| 230 | /* VGA color palette registers */ |
| 231 | I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 232 | } |
| 233 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 234 | static void i915_save_modeset_reg(struct drm_device *dev) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 235 | { |
| 236 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 237 | int i; |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 238 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 239 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 240 | return; |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 241 | |
Chris Wilson | f3c91c1 | 2010-11-21 09:56:00 +0000 | [diff] [blame] | 242 | /* Cursor state */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 243 | dev_priv->saveCURACNTR = I915_READ(_CURACNTR); |
| 244 | dev_priv->saveCURAPOS = I915_READ(_CURAPOS); |
| 245 | dev_priv->saveCURABASE = I915_READ(_CURABASE); |
| 246 | dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR); |
| 247 | dev_priv->saveCURBPOS = I915_READ(_CURBPOS); |
| 248 | dev_priv->saveCURBBASE = I915_READ(_CURBBASE); |
Chris Wilson | f3c91c1 | 2010-11-21 09:56:00 +0000 | [diff] [blame] | 249 | if (IS_GEN2(dev)) |
| 250 | dev_priv->saveCURSIZE = I915_READ(CURSIZE); |
| 251 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 252 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 253 | dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); |
| 254 | dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); |
| 255 | } |
| 256 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 257 | /* Pipe & plane A info */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 258 | dev_priv->savePIPEACONF = I915_READ(_PIPEACONF); |
| 259 | dev_priv->savePIPEASRC = I915_READ(_PIPEASRC); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 260 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 261 | dev_priv->saveFPA0 = I915_READ(_PCH_FPA0); |
| 262 | dev_priv->saveFPA1 = I915_READ(_PCH_FPA1); |
| 263 | dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 264 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 265 | dev_priv->saveFPA0 = I915_READ(_FPA0); |
| 266 | dev_priv->saveFPA1 = I915_READ(_FPA1); |
| 267 | dev_priv->saveDPLL_A = I915_READ(_DPLL_A); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 268 | } |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 269 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 270 | dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD); |
| 271 | dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A); |
| 272 | dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A); |
| 273 | dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A); |
| 274 | dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A); |
| 275 | dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A); |
| 276 | dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 277 | if (!HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 278 | dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 279 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 280 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 281 | dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1); |
| 282 | dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1); |
| 283 | dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1); |
| 284 | dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1); |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 285 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 286 | dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL); |
| 287 | dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 288 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 289 | dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1); |
| 290 | dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ); |
| 291 | dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 292 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 293 | dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF); |
| 294 | dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A); |
| 295 | dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A); |
| 296 | dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A); |
| 297 | dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A); |
| 298 | dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A); |
| 299 | dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 300 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 301 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 302 | dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR); |
| 303 | dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE); |
| 304 | dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE); |
| 305 | dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS); |
| 306 | dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 307 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 308 | dev_priv->saveDSPASURF = I915_READ(_DSPASURF); |
| 309 | dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 310 | } |
| 311 | i915_save_palette(dev, PIPE_A); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 312 | dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 313 | |
| 314 | /* Pipe & plane B info */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 315 | dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF); |
| 316 | dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 317 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 318 | dev_priv->saveFPB0 = I915_READ(_PCH_FPB0); |
| 319 | dev_priv->saveFPB1 = I915_READ(_PCH_FPB1); |
| 320 | dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 321 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 322 | dev_priv->saveFPB0 = I915_READ(_FPB0); |
| 323 | dev_priv->saveFPB1 = I915_READ(_FPB1); |
| 324 | dev_priv->saveDPLL_B = I915_READ(_DPLL_B); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 325 | } |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 326 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 327 | dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD); |
| 328 | dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B); |
| 329 | dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B); |
| 330 | dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B); |
| 331 | dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B); |
| 332 | dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B); |
| 333 | dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 334 | if (!HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 335 | dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 336 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 337 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 338 | dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1); |
| 339 | dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1); |
| 340 | dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1); |
| 341 | dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1); |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 342 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 343 | dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL); |
| 344 | dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 345 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 346 | dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1); |
| 347 | dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ); |
| 348 | dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 349 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 350 | dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF); |
| 351 | dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B); |
| 352 | dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B); |
| 353 | dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B); |
| 354 | dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B); |
| 355 | dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B); |
| 356 | dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 357 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 358 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 359 | dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR); |
| 360 | dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE); |
| 361 | dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE); |
| 362 | dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS); |
| 363 | dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 364 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 365 | dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF); |
| 366 | dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 367 | } |
| 368 | i915_save_palette(dev, PIPE_B); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 369 | dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 370 | |
| 371 | /* Fences */ |
| 372 | switch (INTEL_INFO(dev)->gen) { |
| 373 | case 6: |
| 374 | for (i = 0; i < 16; i++) |
| 375 | dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); |
| 376 | break; |
| 377 | case 5: |
| 378 | case 4: |
| 379 | for (i = 0; i < 16; i++) |
| 380 | dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); |
| 381 | break; |
| 382 | case 3: |
| 383 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 384 | for (i = 0; i < 8; i++) |
| 385 | dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); |
| 386 | case 2: |
| 387 | for (i = 0; i < 8; i++) |
| 388 | dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); |
| 389 | break; |
| 390 | } |
| 391 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 392 | return; |
| 393 | } |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 394 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 395 | static void i915_restore_modeset_reg(struct drm_device *dev) |
| 396 | { |
| 397 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 398 | int dpll_a_reg, fpa0_reg, fpa1_reg; |
| 399 | int dpll_b_reg, fpb0_reg, fpb1_reg; |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 400 | int i; |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 401 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 402 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 403 | return; |
| 404 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 405 | /* Fences */ |
| 406 | switch (INTEL_INFO(dev)->gen) { |
| 407 | case 6: |
| 408 | for (i = 0; i < 16; i++) |
| 409 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]); |
| 410 | break; |
| 411 | case 5: |
| 412 | case 4: |
| 413 | for (i = 0; i < 16; i++) |
| 414 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]); |
| 415 | break; |
| 416 | case 3: |
| 417 | case 2: |
| 418 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 419 | for (i = 0; i < 8; i++) |
| 420 | I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); |
| 421 | for (i = 0; i < 8; i++) |
| 422 | I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); |
| 423 | break; |
| 424 | } |
| 425 | |
| 426 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 427 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 428 | dpll_a_reg = _PCH_DPLL_A; |
| 429 | dpll_b_reg = _PCH_DPLL_B; |
| 430 | fpa0_reg = _PCH_FPA0; |
| 431 | fpb0_reg = _PCH_FPB0; |
| 432 | fpa1_reg = _PCH_FPA1; |
| 433 | fpb1_reg = _PCH_FPB1; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 434 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 435 | dpll_a_reg = _DPLL_A; |
| 436 | dpll_b_reg = _DPLL_B; |
| 437 | fpa0_reg = _FPA0; |
| 438 | fpb0_reg = _FPB0; |
| 439 | fpa1_reg = _FPA1; |
| 440 | fpb1_reg = _FPB1; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 441 | } |
| 442 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 443 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 444 | I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); |
| 445 | I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); |
| 446 | } |
| 447 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 448 | /* Pipe & plane A info */ |
| 449 | /* Prime the clock */ |
| 450 | if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 451 | I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 452 | ~DPLL_VCO_ENABLE); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 453 | POSTING_READ(dpll_a_reg); |
| 454 | udelay(150); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 455 | } |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 456 | I915_WRITE(fpa0_reg, dev_priv->saveFPA0); |
| 457 | I915_WRITE(fpa1_reg, dev_priv->saveFPA1); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 458 | /* Actually enable it */ |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 459 | I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 460 | POSTING_READ(dpll_a_reg); |
| 461 | udelay(150); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 462 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 463 | I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD); |
| 464 | POSTING_READ(_DPLL_A_MD); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 465 | } |
| 466 | udelay(150); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 467 | |
| 468 | /* Restore mode */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 469 | I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A); |
| 470 | I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A); |
| 471 | I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A); |
| 472 | I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A); |
| 473 | I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A); |
| 474 | I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 475 | if (!HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 476 | I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 477 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 478 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 479 | I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); |
| 480 | I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); |
| 481 | I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); |
| 482 | I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1); |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 483 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 484 | I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); |
| 485 | I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 486 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 487 | I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1); |
| 488 | I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); |
| 489 | I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 490 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 491 | I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF); |
| 492 | I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); |
| 493 | I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); |
| 494 | I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); |
| 495 | I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); |
| 496 | I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); |
| 497 | I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 498 | } |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 499 | |
| 500 | /* Restore plane info */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 501 | I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE); |
| 502 | I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS); |
| 503 | I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC); |
| 504 | I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR); |
| 505 | I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 506 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 507 | I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF); |
| 508 | I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 509 | } |
| 510 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 511 | I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 512 | |
| 513 | i915_restore_palette(dev, PIPE_A); |
| 514 | /* Enable the plane */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 515 | I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR); |
| 516 | I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR)); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 517 | |
| 518 | /* Pipe & plane B info */ |
| 519 | if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 520 | I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 521 | ~DPLL_VCO_ENABLE); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 522 | POSTING_READ(dpll_b_reg); |
| 523 | udelay(150); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 524 | } |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 525 | I915_WRITE(fpb0_reg, dev_priv->saveFPB0); |
| 526 | I915_WRITE(fpb1_reg, dev_priv->saveFPB1); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 527 | /* Actually enable it */ |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 528 | I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 529 | POSTING_READ(dpll_b_reg); |
| 530 | udelay(150); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 531 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 532 | I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD); |
| 533 | POSTING_READ(_DPLL_B_MD); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 534 | } |
| 535 | udelay(150); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 536 | |
| 537 | /* Restore mode */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 538 | I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B); |
| 539 | I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B); |
| 540 | I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B); |
| 541 | I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B); |
| 542 | I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B); |
| 543 | I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 544 | if (!HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 545 | I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 546 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 547 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 548 | I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); |
| 549 | I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); |
| 550 | I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); |
| 551 | I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1); |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 552 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 553 | I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); |
| 554 | I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 555 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 556 | I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1); |
| 557 | I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); |
| 558 | I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 559 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 560 | I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF); |
| 561 | I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); |
| 562 | I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); |
| 563 | I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); |
| 564 | I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); |
| 565 | I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); |
| 566 | I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 567 | } |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 568 | |
| 569 | /* Restore plane info */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 570 | I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE); |
| 571 | I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS); |
| 572 | I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC); |
| 573 | I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR); |
| 574 | I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 575 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 576 | I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF); |
| 577 | I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 578 | } |
| 579 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 580 | I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 581 | |
| 582 | i915_restore_palette(dev, PIPE_B); |
| 583 | /* Enable the plane */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 584 | I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR); |
| 585 | I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR)); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 586 | |
Chris Wilson | f3c91c1 | 2010-11-21 09:56:00 +0000 | [diff] [blame] | 587 | /* Cursor state */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 588 | I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS); |
| 589 | I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR); |
| 590 | I915_WRITE(_CURABASE, dev_priv->saveCURABASE); |
| 591 | I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS); |
| 592 | I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR); |
| 593 | I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE); |
Chris Wilson | f3c91c1 | 2010-11-21 09:56:00 +0000 | [diff] [blame] | 594 | if (IS_GEN2(dev)) |
| 595 | I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); |
| 596 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 597 | return; |
| 598 | } |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 599 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 600 | static void i915_save_display(struct drm_device *dev) |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 601 | { |
| 602 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 603 | |
| 604 | /* Display arbitration control */ |
| 605 | dev_priv->saveDSPARB = I915_READ(DSPARB); |
| 606 | |
| 607 | /* This is only meaningful in non-KMS mode */ |
| 608 | /* Don't save them in KMS mode */ |
| 609 | i915_save_modeset_reg(dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 610 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 611 | /* CRT state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 612 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 613 | dev_priv->saveADPA = I915_READ(PCH_ADPA); |
| 614 | } else { |
| 615 | dev_priv->saveADPA = I915_READ(ADPA); |
| 616 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 617 | |
| 618 | /* LVDS state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 619 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 620 | dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); |
| 621 | dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); |
| 622 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); |
| 623 | dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); |
| 624 | dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); |
| 625 | dev_priv->saveLVDS = I915_READ(PCH_LVDS); |
| 626 | } else { |
| 627 | dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); |
| 628 | dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); |
| 629 | dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); |
| 630 | dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 631 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 632 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); |
| 633 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
| 634 | dev_priv->saveLVDS = I915_READ(LVDS); |
| 635 | } |
| 636 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 637 | if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 638 | dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 639 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 640 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 641 | dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); |
| 642 | dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); |
| 643 | dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); |
| 644 | } else { |
| 645 | dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); |
| 646 | dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); |
| 647 | dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); |
| 648 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 649 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 650 | /* Display Port state */ |
| 651 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
| 652 | dev_priv->saveDP_B = I915_READ(DP_B); |
| 653 | dev_priv->saveDP_C = I915_READ(DP_C); |
| 654 | dev_priv->saveDP_D = I915_READ(DP_D); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 655 | dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M); |
| 656 | dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M); |
| 657 | dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N); |
| 658 | dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N); |
| 659 | dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M); |
| 660 | dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M); |
| 661 | dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N); |
| 662 | dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 663 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 664 | /* FIXME: save TV & SDVO state */ |
| 665 | |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 666 | /* Only save FBC state on the platform that supports FBC */ |
| 667 | if (I915_HAS_FBC(dev)) { |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 668 | if (HAS_PCH_SPLIT(dev)) { |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 669 | dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); |
| 670 | } else if (IS_GM45(dev)) { |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 671 | dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); |
| 672 | } else { |
| 673 | dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); |
| 674 | dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); |
| 675 | dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); |
| 676 | dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); |
| 677 | } |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 678 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 679 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 680 | /* VGA state */ |
| 681 | dev_priv->saveVGA0 = I915_READ(VGA0); |
| 682 | dev_priv->saveVGA1 = I915_READ(VGA1); |
| 683 | dev_priv->saveVGA_PD = I915_READ(VGA_PD); |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 684 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 685 | dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); |
| 686 | else |
| 687 | dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 688 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 689 | i915_save_vga(dev); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 690 | } |
| 691 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 692 | static void i915_restore_display(struct drm_device *dev) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 693 | { |
| 694 | struct drm_i915_private *dev_priv = dev->dev_private; |
Peng Li | 461cba2 | 2008-11-18 12:39:02 +0800 | [diff] [blame] | 695 | |
Keith Packard | 881ee98 | 2008-11-02 23:08:44 -0800 | [diff] [blame] | 696 | /* Display arbitration */ |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 697 | I915_WRITE(DSPARB, dev_priv->saveDSPARB); |
| 698 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 699 | /* Display port ratios (must be done before clock is set) */ |
| 700 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 701 | I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M); |
| 702 | I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M); |
| 703 | I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N); |
| 704 | I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N); |
| 705 | I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M); |
| 706 | I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M); |
| 707 | I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N); |
| 708 | I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 709 | } |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 710 | |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 711 | /* This is only meaningful in non-KMS mode */ |
| 712 | /* Don't restore them in KMS mode */ |
| 713 | i915_restore_modeset_reg(dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 714 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 715 | /* CRT state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 716 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 717 | I915_WRITE(PCH_ADPA, dev_priv->saveADPA); |
| 718 | else |
| 719 | I915_WRITE(ADPA, dev_priv->saveADPA); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 720 | |
| 721 | /* LVDS state */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 722 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 723 | I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 724 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 725 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 726 | I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); |
| 727 | } else if (IS_MOBILE(dev) && !IS_I830(dev)) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 728 | I915_WRITE(LVDS, dev_priv->saveLVDS); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 729 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 730 | if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 731 | I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); |
| 732 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 733 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 734 | I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); |
| 735 | I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); |
| 736 | I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); |
| 737 | I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2); |
| 738 | I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); |
| 739 | I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); |
| 740 | I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); |
| 741 | I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 742 | I915_WRITE(RSTDBYCTL, |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 743 | dev_priv->saveMCHBAR_RENDER_STANDBY); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 744 | } else { |
| 745 | I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); |
| 746 | I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); |
| 747 | I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL); |
| 748 | I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); |
| 749 | I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); |
| 750 | I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); |
| 751 | I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); |
| 752 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 753 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 754 | /* Display Port state */ |
| 755 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
| 756 | I915_WRITE(DP_B, dev_priv->saveDP_B); |
| 757 | I915_WRITE(DP_C, dev_priv->saveDP_C); |
| 758 | I915_WRITE(DP_D, dev_priv->saveDP_D); |
| 759 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 760 | /* FIXME: restore TV & SDVO state */ |
| 761 | |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 762 | /* only restore FBC info on the platform that supports FBC*/ |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 763 | intel_disable_fbc(dev); |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 764 | if (I915_HAS_FBC(dev)) { |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 765 | if (HAS_PCH_SPLIT(dev)) { |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 766 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); |
| 767 | } else if (IS_GM45(dev)) { |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 768 | I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); |
| 769 | } else { |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 770 | I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); |
| 771 | I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); |
| 772 | I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); |
| 773 | I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); |
| 774 | } |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 775 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 776 | /* VGA state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 777 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 778 | I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); |
| 779 | else |
| 780 | I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); |
Ben Widawsky | 483f179 | 2011-06-22 09:55:01 -0700 | [diff] [blame] | 781 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 782 | I915_WRITE(VGA0, dev_priv->saveVGA0); |
| 783 | I915_WRITE(VGA1, dev_priv->saveVGA1); |
| 784 | I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); |
Chris Wilson | 72bcb26 | 2010-08-14 14:41:22 +0100 | [diff] [blame] | 785 | POSTING_READ(VGA_PD); |
| 786 | udelay(150); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 787 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 788 | i915_restore_vga(dev); |
| 789 | } |
| 790 | |
| 791 | int i915_save_state(struct drm_device *dev) |
| 792 | { |
| 793 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 794 | int i; |
| 795 | |
| 796 | pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); |
| 797 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 798 | mutex_lock(&dev->struct_mutex); |
| 799 | |
Chris Wilson | 968b503 | 2011-03-23 18:16:55 +0000 | [diff] [blame] | 800 | /* Hardware status page */ |
| 801 | dev_priv->saveHWS = I915_READ(HWS_PGA); |
| 802 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 803 | i915_save_display(dev); |
| 804 | |
| 805 | /* Interrupt state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 806 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 807 | dev_priv->saveDEIER = I915_READ(DEIER); |
| 808 | dev_priv->saveDEIMR = I915_READ(DEIMR); |
| 809 | dev_priv->saveGTIER = I915_READ(GTIER); |
| 810 | dev_priv->saveGTIMR = I915_READ(GTIMR); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 811 | dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR); |
| 812 | dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 813 | dev_priv->saveMCHBAR_RENDER_STANDBY = |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 814 | I915_READ(RSTDBYCTL); |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 815 | dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 816 | } else { |
| 817 | dev_priv->saveIER = I915_READ(IER); |
| 818 | dev_priv->saveIMR = I915_READ(IMR); |
| 819 | } |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 820 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 821 | if (IS_IRONLAKE_M(dev)) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 822 | ironlake_disable_drps(dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 823 | if (IS_GEN6(dev)) |
| 824 | gen6_disable_rps(dev); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 825 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 826 | /* Cache mode state */ |
| 827 | dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); |
| 828 | |
| 829 | /* Memory Arbitration state */ |
| 830 | dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); |
| 831 | |
| 832 | /* Scratch space */ |
| 833 | for (i = 0; i < 16; i++) { |
| 834 | dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); |
| 835 | dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); |
| 836 | } |
| 837 | for (i = 0; i < 3; i++) |
| 838 | dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); |
| 839 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 840 | mutex_unlock(&dev->struct_mutex); |
| 841 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | int i915_restore_state(struct drm_device *dev) |
| 846 | { |
| 847 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 848 | int i; |
| 849 | |
| 850 | pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); |
| 851 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 852 | mutex_lock(&dev->struct_mutex); |
| 853 | |
Chris Wilson | 968b503 | 2011-03-23 18:16:55 +0000 | [diff] [blame] | 854 | /* Hardware status page */ |
| 855 | I915_WRITE(HWS_PGA, dev_priv->saveHWS); |
| 856 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 857 | i915_restore_display(dev); |
| 858 | |
| 859 | /* Interrupt state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 860 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 861 | I915_WRITE(DEIER, dev_priv->saveDEIER); |
| 862 | I915_WRITE(DEIMR, dev_priv->saveDEIMR); |
| 863 | I915_WRITE(GTIER, dev_priv->saveGTIER); |
| 864 | I915_WRITE(GTIMR, dev_priv->saveGTIMR); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 865 | I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); |
| 866 | I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 867 | I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 868 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 869 | I915_WRITE(IER, dev_priv->saveIER); |
| 870 | I915_WRITE(IMR, dev_priv->saveIMR); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 871 | } |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 872 | mutex_unlock(&dev->struct_mutex); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 873 | |
Keith Packard | 92b79f4 | 2011-08-12 17:07:18 -0700 | [diff] [blame] | 874 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 875 | intel_init_clock_gating(dev); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 876 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 877 | if (IS_IRONLAKE_M(dev)) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 878 | ironlake_enable_drps(dev); |
Kyle McMartin | 48fcfc8 | 2010-11-03 16:27:57 -0400 | [diff] [blame] | 879 | intel_init_emon(dev); |
| 880 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 881 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 882 | if (IS_GEN6(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 883 | gen6_enable_rps(dev_priv); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 884 | gen6_update_ring_freq(dev_priv); |
| 885 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 886 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 887 | mutex_lock(&dev->struct_mutex); |
| 888 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 889 | /* Cache mode state */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame^] | 890 | I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 891 | |
| 892 | /* Memory arbitration state */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame^] | 893 | I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 894 | |
| 895 | for (i = 0; i < 16; i++) { |
| 896 | I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); |
Roel Kluin | 819e006 | 2009-07-26 00:50:38 +0200 | [diff] [blame] | 897 | I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 898 | } |
| 899 | for (i = 0; i < 3; i++) |
| 900 | I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); |
| 901 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 902 | mutex_unlock(&dev->struct_mutex); |
| 903 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 904 | intel_i2c_reset(dev); |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 905 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 906 | return 0; |
| 907 | } |