Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Definitions for the new Marvell Yukon 2 driver. |
| 3 | */ |
| 4 | #ifndef _SKY2_H |
| 5 | #define _SKY2_H |
| 6 | |
| 7 | /* PCI config registers */ |
Stephen Hemminger | 977bdf0 | 2006-02-22 11:44:58 -0800 | [diff] [blame] | 8 | enum { |
| 9 | PCI_DEV_REG1 = 0x40, |
| 10 | PCI_DEV_REG2 = 0x44, |
| 11 | PCI_DEV_STATUS = 0x7c, |
| 12 | PCI_DEV_REG3 = 0x80, |
| 13 | PCI_DEV_REG4 = 0x84, |
| 14 | PCI_DEV_REG5 = 0x88, |
| 15 | }; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 16 | |
Stephen Hemminger | 977bdf0 | 2006-02-22 11:44:58 -0800 | [diff] [blame] | 17 | enum { |
| 18 | PEX_DEV_CAP = 0xe4, |
| 19 | PEX_DEV_CTRL = 0xe8, |
| 20 | PEX_DEV_STA = 0xea, |
| 21 | PEX_LNK_STAT = 0xf2, |
| 22 | PEX_UNC_ERR_STAT= 0x104, |
| 23 | }; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 24 | |
| 25 | /* Yukon-2 */ |
| 26 | enum pci_dev_reg_1 { |
| 27 | PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ |
| 28 | PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ |
| 29 | PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ |
| 30 | PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ |
| 31 | PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ |
| 32 | PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ |
| 33 | }; |
| 34 | |
| 35 | enum pci_dev_reg_2 { |
| 36 | PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ |
| 37 | PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ |
| 38 | PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ |
| 39 | |
| 40 | PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ |
| 41 | PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ |
| 42 | PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ |
| 43 | PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ |
| 44 | |
| 45 | PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ |
| 46 | }; |
| 47 | |
Stephen Hemminger | 977bdf0 | 2006-02-22 11:44:58 -0800 | [diff] [blame] | 48 | /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ |
| 49 | enum pci_dev_reg_4 { |
| 50 | /* (Link Training & Status State Machine) */ |
| 51 | P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ |
| 52 | /* (Active State Power Management) */ |
| 53 | P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ |
| 54 | P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ |
| 55 | P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ |
| 56 | P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ |
| 57 | |
| 58 | P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ |
| 59 | P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ |
| 60 | P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ |
| 61 | P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ |
| 62 | P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ |
| 63 | P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN |
| 64 | | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, |
| 65 | }; |
| 66 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 67 | |
| 68 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ |
| 69 | PCI_STATUS_SIG_SYSTEM_ERROR | \ |
| 70 | PCI_STATUS_REC_MASTER_ABORT | \ |
| 71 | PCI_STATUS_REC_TARGET_ABORT | \ |
| 72 | PCI_STATUS_PARITY) |
| 73 | |
| 74 | enum pex_dev_ctrl { |
| 75 | PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */ |
| 76 | PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */ |
| 77 | PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */ |
| 78 | PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */ |
| 79 | PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */ |
| 80 | PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */ |
| 81 | PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */ |
| 82 | PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */ |
| 83 | PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */ |
| 84 | PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */ |
| 85 | PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */ |
| 86 | }; |
| 87 | #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK) |
| 88 | |
| 89 | /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ |
| 90 | enum pex_err { |
| 91 | PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */ |
| 92 | |
| 93 | PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */ |
| 94 | |
| 95 | PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */ |
| 96 | |
| 97 | PEX_COMP_TO = 1<<14, /* Completion Timeout */ |
| 98 | PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */ |
| 99 | PEX_POIS_TLP = 1<<12, /* Poisoned TLP */ |
| 100 | |
| 101 | PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */ |
| 102 | PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P), |
| 103 | }; |
| 104 | |
| 105 | |
| 106 | enum csr_regs { |
| 107 | B0_RAP = 0x0000, |
| 108 | B0_CTST = 0x0004, |
| 109 | B0_Y2LED = 0x0005, |
| 110 | B0_POWER_CTRL = 0x0007, |
| 111 | B0_ISRC = 0x0008, |
| 112 | B0_IMSK = 0x000c, |
| 113 | B0_HWE_ISRC = 0x0010, |
| 114 | B0_HWE_IMSK = 0x0014, |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 115 | |
| 116 | /* Special ISR registers (Yukon-2 only) */ |
| 117 | B0_Y2_SP_ISRC2 = 0x001c, |
| 118 | B0_Y2_SP_ISRC3 = 0x0020, |
| 119 | B0_Y2_SP_EISR = 0x0024, |
| 120 | B0_Y2_SP_LISR = 0x0028, |
| 121 | B0_Y2_SP_ICR = 0x002c, |
| 122 | |
| 123 | B2_MAC_1 = 0x0100, |
| 124 | B2_MAC_2 = 0x0108, |
| 125 | B2_MAC_3 = 0x0110, |
| 126 | B2_CONN_TYP = 0x0118, |
| 127 | B2_PMD_TYP = 0x0119, |
| 128 | B2_MAC_CFG = 0x011a, |
| 129 | B2_CHIP_ID = 0x011b, |
| 130 | B2_E_0 = 0x011c, |
shemminger@osdl.org | 488f84f | 2005-10-26 12:16:07 -0700 | [diff] [blame] | 131 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 132 | B2_Y2_CLK_GATE = 0x011d, |
| 133 | B2_Y2_HW_RES = 0x011e, |
| 134 | B2_E_3 = 0x011f, |
| 135 | B2_Y2_CLK_CTRL = 0x0120, |
shemminger@osdl.org | 488f84f | 2005-10-26 12:16:07 -0700 | [diff] [blame] | 136 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 137 | B2_TI_INI = 0x0130, |
| 138 | B2_TI_VAL = 0x0134, |
| 139 | B2_TI_CTRL = 0x0138, |
| 140 | B2_TI_TEST = 0x0139, |
shemminger@osdl.org | 488f84f | 2005-10-26 12:16:07 -0700 | [diff] [blame] | 141 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 142 | B2_TST_CTRL1 = 0x0158, |
| 143 | B2_TST_CTRL2 = 0x0159, |
| 144 | B2_GP_IO = 0x015c, |
shemminger@osdl.org | 488f84f | 2005-10-26 12:16:07 -0700 | [diff] [blame] | 145 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 146 | B2_I2C_CTRL = 0x0160, |
| 147 | B2_I2C_DATA = 0x0164, |
| 148 | B2_I2C_IRQ = 0x0168, |
| 149 | B2_I2C_SW = 0x016c, |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 150 | |
| 151 | B3_RAM_ADDR = 0x0180, |
| 152 | B3_RAM_DATA_LO = 0x0184, |
| 153 | B3_RAM_DATA_HI = 0x0188, |
| 154 | |
| 155 | /* RAM Interface Registers */ |
| 156 | /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ |
| 157 | /* |
| 158 | * The HW-Spec. calls this registers Timeout Value 0..11. But this names are |
| 159 | * not usable in SW. Please notice these are NOT real timeouts, these are |
| 160 | * the number of qWords transferred continuously. |
| 161 | */ |
| 162 | #define RAM_BUFFER(port, reg) (reg | (port <<6)) |
| 163 | |
| 164 | B3_RI_WTO_R1 = 0x0190, |
| 165 | B3_RI_WTO_XA1 = 0x0191, |
| 166 | B3_RI_WTO_XS1 = 0x0192, |
| 167 | B3_RI_RTO_R1 = 0x0193, |
| 168 | B3_RI_RTO_XA1 = 0x0194, |
| 169 | B3_RI_RTO_XS1 = 0x0195, |
| 170 | B3_RI_WTO_R2 = 0x0196, |
| 171 | B3_RI_WTO_XA2 = 0x0197, |
| 172 | B3_RI_WTO_XS2 = 0x0198, |
| 173 | B3_RI_RTO_R2 = 0x0199, |
| 174 | B3_RI_RTO_XA2 = 0x019a, |
| 175 | B3_RI_RTO_XS2 = 0x019b, |
| 176 | B3_RI_TO_VAL = 0x019c, |
| 177 | B3_RI_CTRL = 0x01a0, |
| 178 | B3_RI_TEST = 0x01a2, |
| 179 | B3_MA_TOINI_RX1 = 0x01b0, |
| 180 | B3_MA_TOINI_RX2 = 0x01b1, |
| 181 | B3_MA_TOINI_TX1 = 0x01b2, |
| 182 | B3_MA_TOINI_TX2 = 0x01b3, |
| 183 | B3_MA_TOVAL_RX1 = 0x01b4, |
| 184 | B3_MA_TOVAL_RX2 = 0x01b5, |
| 185 | B3_MA_TOVAL_TX1 = 0x01b6, |
| 186 | B3_MA_TOVAL_TX2 = 0x01b7, |
| 187 | B3_MA_TO_CTRL = 0x01b8, |
| 188 | B3_MA_TO_TEST = 0x01ba, |
| 189 | B3_MA_RCINI_RX1 = 0x01c0, |
| 190 | B3_MA_RCINI_RX2 = 0x01c1, |
| 191 | B3_MA_RCINI_TX1 = 0x01c2, |
| 192 | B3_MA_RCINI_TX2 = 0x01c3, |
| 193 | B3_MA_RCVAL_RX1 = 0x01c4, |
| 194 | B3_MA_RCVAL_RX2 = 0x01c5, |
| 195 | B3_MA_RCVAL_TX1 = 0x01c6, |
| 196 | B3_MA_RCVAL_TX2 = 0x01c7, |
| 197 | B3_MA_RC_CTRL = 0x01c8, |
| 198 | B3_MA_RC_TEST = 0x01ca, |
| 199 | B3_PA_TOINI_RX1 = 0x01d0, |
| 200 | B3_PA_TOINI_RX2 = 0x01d4, |
| 201 | B3_PA_TOINI_TX1 = 0x01d8, |
| 202 | B3_PA_TOINI_TX2 = 0x01dc, |
| 203 | B3_PA_TOVAL_RX1 = 0x01e0, |
| 204 | B3_PA_TOVAL_RX2 = 0x01e4, |
| 205 | B3_PA_TOVAL_TX1 = 0x01e8, |
| 206 | B3_PA_TOVAL_TX2 = 0x01ec, |
| 207 | B3_PA_CTRL = 0x01f0, |
| 208 | B3_PA_TEST = 0x01f2, |
| 209 | |
| 210 | Y2_CFG_SPC = 0x1c00, |
| 211 | }; |
| 212 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 213 | /* B0_CTST 16 bit Control/Status register */ |
| 214 | enum { |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 215 | Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 216 | Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ |
| 217 | Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ |
| 218 | Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ |
| 219 | Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ |
| 220 | Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ |
| 221 | Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ |
| 222 | Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ |
| 223 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 224 | CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ |
| 225 | CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ |
| 226 | CS_STOP_DONE = 1<<5, /* Stop Master is finished */ |
| 227 | CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ |
| 228 | CS_MRST_CLR = 1<<3, /* Clear Master reset */ |
| 229 | CS_MRST_SET = 1<<2, /* Set Master reset */ |
| 230 | CS_RST_CLR = 1<<1, /* Clear Software reset */ |
| 231 | CS_RST_SET = 1, /* Set Software reset */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 232 | }; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 233 | |
| 234 | /* B0_LED 8 Bit LED register */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 235 | enum { |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 236 | /* Bit 7.. 2: reserved */ |
| 237 | LED_STAT_ON = 1<<1, /* Status LED on */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 238 | LED_STAT_OFF = 1, /* Status LED off */ |
| 239 | }; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 240 | |
| 241 | /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 242 | enum { |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 243 | PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ |
| 244 | PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ |
| 245 | PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ |
| 246 | PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ |
| 247 | PC_VAUX_ON = 1<<3, /* Switch VAUX On */ |
| 248 | PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ |
| 249 | PC_VCC_ON = 1<<1, /* Switch VCC On */ |
| 250 | PC_VCC_OFF = 1<<0, /* Switch VCC Off */ |
| 251 | }; |
| 252 | |
| 253 | /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ |
| 254 | |
| 255 | /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ |
| 256 | /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ |
| 257 | /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ |
| 258 | /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ |
| 259 | enum { |
| 260 | Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ |
| 261 | Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ |
| 262 | Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ |
| 263 | |
| 264 | Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ |
| 265 | Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ |
| 266 | Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ |
| 267 | Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ |
| 268 | |
| 269 | Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ |
| 270 | Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ |
| 271 | Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ |
| 272 | Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ |
| 273 | Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ |
| 274 | |
| 275 | Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ |
| 276 | Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ |
| 277 | Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ |
| 278 | Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ |
| 279 | Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ |
| 280 | |
| 281 | Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU | |
| 282 | Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY | |
| 283 | Y2_IS_IRQ_SW | Y2_IS_TIMINT, |
| 284 | Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | |
| 285 | Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1, |
| 286 | Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | |
| 287 | Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2, |
| 288 | }; |
| 289 | |
| 290 | /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ |
| 291 | enum { |
| 292 | IS_ERR_MSK = 0x00003fff,/* All Error bits */ |
| 293 | |
| 294 | IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ |
| 295 | IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ |
| 296 | IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ |
| 297 | IS_IRQ_STAT = 1<<10, /* IRQ status exception */ |
| 298 | IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ |
| 299 | IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ |
| 300 | IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ |
| 301 | IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ |
| 302 | IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ |
| 303 | IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ |
| 304 | IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ |
| 305 | IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ |
| 306 | IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ |
| 307 | IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ |
| 308 | }; |
| 309 | |
| 310 | /* Hardware error interrupt mask for Yukon 2 */ |
| 311 | enum { |
| 312 | Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ |
| 313 | Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ |
| 314 | Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ |
| 315 | Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ |
| 316 | Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ |
| 317 | Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ |
| 318 | /* Link 2 */ |
| 319 | Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ |
| 320 | Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ |
| 321 | Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ |
| 322 | Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ |
| 323 | Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ |
| 324 | Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ |
| 325 | /* Link 1 */ |
| 326 | Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ |
| 327 | Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ |
| 328 | Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ |
| 329 | Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ |
| 330 | Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ |
| 331 | Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ |
| 332 | |
| 333 | Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | |
| 334 | Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, |
| 335 | Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | |
| 336 | Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, |
| 337 | |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 338 | Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | |
shemminger@osdl.org | 5a5b1ea | 2005-11-30 11:45:15 -0800 | [diff] [blame] | 339 | Y2_IS_PCI_EXP | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 340 | Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, |
| 341 | }; |
| 342 | |
| 343 | /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ |
| 344 | enum { |
| 345 | DPT_START = 1<<1, |
| 346 | DPT_STOP = 1<<0, |
| 347 | }; |
| 348 | |
| 349 | /* B2_TST_CTRL1 8 bit Test Control Register 1 */ |
| 350 | enum { |
| 351 | TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ |
| 352 | TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ |
| 353 | TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ |
| 354 | TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ |
| 355 | TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ |
| 356 | TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ |
| 357 | TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ |
| 358 | TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ |
| 359 | }; |
| 360 | |
| 361 | /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ |
| 362 | enum { |
| 363 | CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ |
| 364 | /* Bit 3.. 2: reserved */ |
| 365 | CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ |
| 366 | CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ |
| 367 | }; |
| 368 | |
| 369 | /* B2_CHIP_ID 8 bit Chip Identification Number */ |
| 370 | enum { |
| 371 | CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */ |
| 372 | CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */ |
| 373 | CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */ |
| 374 | CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */ |
| 375 | CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ |
shemminger@osdl.org | 5a5b1ea | 2005-11-30 11:45:15 -0800 | [diff] [blame] | 376 | CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 377 | CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ |
| 378 | CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ |
| 379 | |
| 380 | CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ |
| 381 | CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ |
| 382 | CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ |
| 383 | }; |
| 384 | |
| 385 | /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ |
| 386 | enum { |
shemminger@osdl.org | d571b69 | 2005-10-26 12:16:09 -0700 | [diff] [blame] | 387 | Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 388 | Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ |
| 389 | Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ |
| 390 | Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ |
shemminger@osdl.org | d571b69 | 2005-10-26 12:16:09 -0700 | [diff] [blame] | 391 | Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 392 | Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ |
| 393 | Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ |
| 394 | Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ |
| 395 | }; |
| 396 | |
| 397 | /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ |
| 398 | enum { |
| 399 | CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ |
| 400 | CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ |
| 401 | CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ |
| 402 | }; |
| 403 | #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) |
| 404 | #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) |
| 405 | |
| 406 | |
| 407 | /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ |
| 408 | enum { |
| 409 | Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ |
| 410 | #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) |
| 411 | Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ |
| 412 | Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ |
| 413 | #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) |
| 414 | #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) |
| 415 | Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ |
| 416 | Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ |
| 417 | }; |
| 418 | |
| 419 | /* B2_TI_CTRL 8 bit Timer control */ |
| 420 | /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ |
| 421 | enum { |
| 422 | TIM_START = 1<<2, /* Start Timer */ |
| 423 | TIM_STOP = 1<<1, /* Stop Timer */ |
| 424 | TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ |
| 425 | }; |
| 426 | |
| 427 | /* B2_TI_TEST 8 Bit Timer Test */ |
| 428 | /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ |
| 429 | /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ |
| 430 | enum { |
| 431 | TIM_T_ON = 1<<2, /* Test mode on */ |
| 432 | TIM_T_OFF = 1<<1, /* Test mode off */ |
| 433 | TIM_T_STEP = 1<<0, /* Test step */ |
| 434 | }; |
| 435 | |
| 436 | /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ |
| 437 | /* Bit 31..19: reserved */ |
| 438 | #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ |
| 439 | /* RAM Interface Registers */ |
| 440 | |
shemminger@osdl.org | d571b69 | 2005-10-26 12:16:09 -0700 | [diff] [blame] | 441 | /* B3_RI_CTRL 16 bit RAM Interface Control Register */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 442 | enum { |
| 443 | RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ |
| 444 | RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ |
| 445 | |
| 446 | RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ |
| 447 | RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ |
| 448 | }; |
| 449 | |
| 450 | #define SK_RI_TO_53 36 /* RAM interface timeout */ |
| 451 | |
| 452 | |
| 453 | /* Port related registers FIFO, and Arbiter */ |
| 454 | #define SK_REG(port,reg) (((port)<<7)+(reg)) |
| 455 | |
| 456 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ |
| 457 | /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ |
| 458 | /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ |
| 459 | /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ |
| 460 | /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ |
| 461 | |
| 462 | #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ |
| 463 | |
| 464 | /* TXA_CTRL 8 bit Tx Arbiter Control Register */ |
| 465 | enum { |
| 466 | TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ |
| 467 | TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ |
| 468 | TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ |
| 469 | TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ |
| 470 | TXA_START_RC = 1<<3, /* Start sync Rate Control */ |
| 471 | TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ |
| 472 | TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ |
| 473 | TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ |
| 474 | }; |
| 475 | |
| 476 | /* |
| 477 | * Bank 4 - 5 |
| 478 | */ |
| 479 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ |
| 480 | enum { |
| 481 | TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ |
| 482 | TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ |
| 483 | TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ |
| 484 | TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ |
| 485 | TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ |
| 486 | TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ |
| 487 | TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ |
| 488 | }; |
| 489 | |
| 490 | |
| 491 | enum { |
| 492 | B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ |
| 493 | B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ |
| 494 | B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ |
| 495 | B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ |
| 496 | B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ |
| 497 | B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ |
| 498 | B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ |
| 499 | B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ |
| 500 | B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ |
| 501 | }; |
| 502 | |
| 503 | /* Queue Register Offsets, use Q_ADDR() to access */ |
| 504 | enum { |
| 505 | B8_Q_REGS = 0x0400, /* base of Queue registers */ |
| 506 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ |
| 507 | Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ |
| 508 | Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ |
| 509 | Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ |
| 510 | Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ |
| 511 | Q_BC = 0x30, /* 32 bit Current Byte Counter */ |
| 512 | Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ |
| 513 | Q_F = 0x38, /* 32 bit Flag Register */ |
| 514 | Q_T1 = 0x3c, /* 32 bit Test Register 1 */ |
| 515 | Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ |
| 516 | Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ |
| 517 | Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ |
| 518 | Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ |
| 519 | Q_T2 = 0x40, /* 32 bit Test Register 2 */ |
| 520 | Q_T3 = 0x44, /* 32 bit Test Register 3 */ |
| 521 | |
| 522 | /* Yukon-2 */ |
| 523 | Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */ |
| 524 | Q_WM = 0x40, /* 16 bit FIFO Watermark */ |
| 525 | Q_AL = 0x42, /* 8 bit FIFO Alignment */ |
| 526 | Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ |
| 527 | Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ |
| 528 | Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ |
| 529 | Q_RL = 0x4a, /* 8 bit FIFO Read Level */ |
| 530 | Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ |
| 531 | Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ |
| 532 | Q_WL = 0x4e, /* 8 bit FIFO Write Level */ |
| 533 | Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ |
| 534 | }; |
| 535 | #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) |
| 536 | |
Stephen Hemminger | 977bdf0 | 2006-02-22 11:44:58 -0800 | [diff] [blame] | 537 | /* Q_F 32 bit Flag Register */ |
| 538 | enum { |
| 539 | F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ |
| 540 | F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ |
| 541 | F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ |
| 542 | F_WM_REACHED = 1<<25, /* Watermark reached */ |
| 543 | F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ |
| 544 | F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ |
| 545 | F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ |
| 546 | }; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 547 | |
| 548 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ |
| 549 | enum { |
| 550 | Y2_B8_PREF_REGS = 0x0450, |
| 551 | |
| 552 | PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ |
| 553 | PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ |
| 554 | PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ |
| 555 | PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ |
| 556 | PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ |
| 557 | PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ |
| 558 | PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ |
| 559 | PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ |
| 560 | PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ |
| 561 | PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ |
| 562 | |
| 563 | PREF_UNIT_MASK_IDX = 0x0fff, |
| 564 | }; |
| 565 | #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) |
| 566 | |
| 567 | /* RAM Buffer Register Offsets */ |
| 568 | enum { |
| 569 | |
| 570 | RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ |
| 571 | RB_END = 0x04,/* 32 bit RAM Buffer End Address */ |
| 572 | RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ |
| 573 | RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ |
| 574 | RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ |
| 575 | RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ |
| 576 | RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ |
| 577 | RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ |
| 578 | /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ |
| 579 | RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ |
| 580 | RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ |
| 581 | RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ |
| 582 | RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ |
| 583 | RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ |
| 584 | }; |
| 585 | |
| 586 | /* Receive and Transmit Queues */ |
| 587 | enum { |
| 588 | Q_R1 = 0x0000, /* Receive Queue 1 */ |
| 589 | Q_R2 = 0x0080, /* Receive Queue 2 */ |
| 590 | Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ |
| 591 | Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ |
| 592 | Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ |
| 593 | Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ |
| 594 | }; |
| 595 | |
| 596 | /* Different PHY Types */ |
| 597 | enum { |
| 598 | PHY_ADDR_MARV = 0, |
| 599 | }; |
| 600 | |
| 601 | #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs)) |
| 602 | |
| 603 | |
| 604 | enum { |
| 605 | LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ |
| 606 | LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ |
| 607 | LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ |
| 608 | LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ |
| 609 | |
| 610 | LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ |
| 611 | |
| 612 | /* Receive GMAC FIFO (YUKON and Yukon-2) */ |
| 613 | |
| 614 | RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ |
| 615 | RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ |
| 616 | RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ |
| 617 | RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ |
| 618 | RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ |
| 619 | RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ |
shemminger@osdl.org | 5a5b1ea | 2005-11-30 11:45:15 -0800 | [diff] [blame] | 620 | RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ |
| 621 | RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 622 | RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ |
| 623 | RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ |
| 624 | |
| 625 | RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ |
| 626 | |
| 627 | RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ |
| 628 | |
| 629 | RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ |
| 630 | }; |
| 631 | |
| 632 | |
| 633 | /* Q_BC 32 bit Current Byte Counter */ |
| 634 | |
| 635 | /* BMU Control Status Registers */ |
| 636 | /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ |
| 637 | /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ |
| 638 | /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ |
| 639 | /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ |
| 640 | /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ |
| 641 | /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ |
| 642 | /* Q_CSR 32 bit BMU Control/Status Register */ |
| 643 | |
| 644 | /* Rx BMU Control / Status Registers (Yukon-2) */ |
| 645 | enum { |
| 646 | BMU_IDLE = 1<<31, /* BMU Idle State */ |
| 647 | BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ |
| 648 | BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ |
| 649 | |
| 650 | BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ |
| 651 | BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ |
| 652 | BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ |
| 653 | BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ |
| 654 | BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ |
shemminger@osdl.org | d571b69 | 2005-10-26 12:16:09 -0700 | [diff] [blame] | 655 | BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 656 | BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ |
| 657 | BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ |
| 658 | BMU_START = 1<<8, /* Start Rx/Tx Queue */ |
| 659 | BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ |
| 660 | BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ |
| 661 | BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ |
| 662 | BMU_FIFO_RST = 1<<4, /* Reset FIFO */ |
| 663 | BMU_OP_ON = 1<<3, /* BMU Operational On */ |
| 664 | BMU_OP_OFF = 1<<2, /* BMU Operational Off */ |
| 665 | BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ |
| 666 | BMU_RST_SET = 1<<0, /* Set BMU Reset */ |
| 667 | |
| 668 | BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, |
| 669 | BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | |
| 670 | BMU_FIFO_ENA | BMU_OP_ON, |
shemminger@osdl.org | af4ed7e | 2005-11-30 11:45:21 -0800 | [diff] [blame] | 671 | |
| 672 | BMU_WM_DEFAULT = 0x600, |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 673 | }; |
| 674 | |
| 675 | /* Tx BMU Control / Status Registers (Yukon-2) */ |
| 676 | /* Bit 31: same as for Rx */ |
| 677 | enum { |
| 678 | BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ |
| 679 | BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ |
shemminger@osdl.org | d571b69 | 2005-10-26 12:16:09 -0700 | [diff] [blame] | 680 | BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 681 | }; |
| 682 | |
| 683 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ |
| 684 | /* PREF_UNIT_CTRL 32 bit Prefetch Control register */ |
| 685 | enum { |
| 686 | PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ |
| 687 | PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ |
| 688 | PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ |
| 689 | PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ |
| 690 | }; |
| 691 | |
| 692 | /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ |
| 693 | /* RB_START 32 bit RAM Buffer Start Address */ |
| 694 | /* RB_END 32 bit RAM Buffer End Address */ |
| 695 | /* RB_WP 32 bit RAM Buffer Write Pointer */ |
| 696 | /* RB_RP 32 bit RAM Buffer Read Pointer */ |
| 697 | /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ |
| 698 | /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ |
| 699 | /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ |
| 700 | /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ |
| 701 | /* RB_PC 32 bit RAM Buffer Packet Counter */ |
| 702 | /* RB_LEV 32 bit RAM Buffer Level Register */ |
| 703 | |
| 704 | #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ |
| 705 | /* RB_TST2 8 bit RAM Buffer Test Register 2 */ |
| 706 | /* RB_TST1 8 bit RAM Buffer Test Register 1 */ |
| 707 | |
| 708 | /* RB_CTRL 8 bit RAM Buffer Control Register */ |
| 709 | enum { |
| 710 | RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ |
| 711 | RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ |
| 712 | RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ |
| 713 | RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ |
| 714 | RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ |
| 715 | RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ |
| 716 | }; |
| 717 | |
| 718 | |
| 719 | /* Transmit GMAC FIFO (YUKON only) */ |
| 720 | enum { |
| 721 | TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ |
| 722 | TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ |
| 723 | TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ |
| 724 | |
| 725 | TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ |
| 726 | TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ |
| 727 | TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ |
| 728 | |
| 729 | TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ |
| 730 | TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ |
| 731 | TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ |
| 732 | }; |
| 733 | |
| 734 | /* Descriptor Poll Timer Registers */ |
| 735 | enum { |
| 736 | B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ |
| 737 | B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ |
| 738 | B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ |
| 739 | |
| 740 | B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ |
| 741 | }; |
| 742 | |
| 743 | /* Time Stamp Timer Registers (YUKON only) */ |
| 744 | enum { |
| 745 | GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ |
| 746 | GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ |
| 747 | GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ |
| 748 | }; |
| 749 | |
| 750 | /* Polling Unit Registers (Yukon-2 only) */ |
| 751 | enum { |
| 752 | POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ |
| 753 | POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ |
| 754 | |
| 755 | POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ |
| 756 | POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ |
| 757 | }; |
| 758 | |
| 759 | /* ASF Subsystem Registers (Yukon-2 only) */ |
| 760 | enum { |
| 761 | B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ |
| 762 | B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ |
| 763 | B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ |
| 764 | |
| 765 | B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ |
| 766 | B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ |
| 767 | B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ |
| 768 | B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ |
| 769 | B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ |
| 770 | B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ |
| 771 | }; |
| 772 | |
| 773 | /* Status BMU Registers (Yukon-2 only)*/ |
| 774 | enum { |
| 775 | STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ |
| 776 | STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ |
| 777 | |
| 778 | STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ |
| 779 | STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ |
| 780 | STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ |
| 781 | STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ |
| 782 | STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ |
| 783 | STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ |
| 784 | STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ |
| 785 | STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ |
| 786 | |
| 787 | /* FIFO Control/Status Registers (Yukon-2 only)*/ |
| 788 | STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ |
| 789 | STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ |
| 790 | STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ |
| 791 | STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ |
| 792 | STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ |
| 793 | STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ |
| 794 | STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ |
| 795 | |
| 796 | /* Level and ISR Timer Registers (Yukon-2 only)*/ |
| 797 | STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ |
| 798 | STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ |
| 799 | STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ |
| 800 | STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ |
| 801 | STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ |
| 802 | STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ |
| 803 | STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ |
| 804 | STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ |
| 805 | STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ |
| 806 | STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ |
| 807 | STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ |
| 808 | STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 809 | }; |
| 810 | |
| 811 | enum { |
| 812 | LINKLED_OFF = 0x01, |
| 813 | LINKLED_ON = 0x02, |
| 814 | LINKLED_LINKSYNC_OFF = 0x04, |
| 815 | LINKLED_LINKSYNC_ON = 0x08, |
| 816 | LINKLED_BLINK_OFF = 0x10, |
| 817 | LINKLED_BLINK_ON = 0x20, |
| 818 | }; |
| 819 | |
| 820 | /* GMAC and GPHY Control Registers (YUKON only) */ |
| 821 | enum { |
| 822 | GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ |
| 823 | GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ |
| 824 | GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ |
| 825 | GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ |
| 826 | GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ |
| 827 | |
| 828 | /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ |
| 829 | |
| 830 | WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */ |
| 831 | |
| 832 | WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ |
| 833 | WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ |
| 834 | WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ |
| 835 | WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ |
| 836 | WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */ |
| 837 | WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */ |
| 838 | WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ |
| 839 | |
| 840 | /* WOL Pattern Length Registers (YUKON only) */ |
| 841 | |
| 842 | WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ |
| 843 | WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ |
| 844 | |
| 845 | /* WOL Pattern Counter Registers (YUKON only) */ |
| 846 | |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 847 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 848 | WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ |
| 849 | WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ |
| 850 | }; |
| 851 | |
| 852 | enum { |
| 853 | WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ |
| 854 | WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ |
| 855 | }; |
| 856 | |
| 857 | enum { |
| 858 | BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ |
| 859 | BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ |
| 860 | }; |
| 861 | |
| 862 | /* |
| 863 | * Marvel-PHY Registers, indirect addressed over GMAC |
| 864 | */ |
| 865 | enum { |
| 866 | PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ |
| 867 | PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ |
| 868 | PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ |
| 869 | PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ |
| 870 | PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ |
| 871 | PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ |
| 872 | PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ |
| 873 | PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ |
| 874 | PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ |
| 875 | /* Marvel-specific registers */ |
| 876 | PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ |
| 877 | PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ |
| 878 | PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ |
| 879 | PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ |
| 880 | PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ |
| 881 | PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ |
| 882 | PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ |
| 883 | PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ |
| 884 | PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ |
| 885 | PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ |
| 886 | PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ |
| 887 | PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ |
| 888 | PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ |
| 889 | PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ |
| 890 | PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ |
| 891 | PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ |
| 892 | PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ |
| 893 | PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ |
| 894 | |
| 895 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 896 | PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ |
| 897 | PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ |
| 898 | PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ |
| 899 | PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ |
| 900 | PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ |
| 901 | }; |
| 902 | |
| 903 | enum { |
| 904 | PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ |
| 905 | PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ |
| 906 | PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ |
| 907 | PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ |
| 908 | PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ |
| 909 | PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ |
| 910 | PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ |
| 911 | PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ |
| 912 | PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ |
| 913 | PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ |
| 914 | }; |
| 915 | |
| 916 | enum { |
| 917 | PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ |
| 918 | PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ |
| 919 | PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ |
| 920 | }; |
| 921 | |
| 922 | enum { |
| 923 | PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ |
| 924 | |
| 925 | PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ |
| 926 | PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ |
| 927 | PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ |
| 928 | PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ |
| 929 | PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ |
| 930 | PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ |
| 931 | PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ |
| 932 | }; |
| 933 | |
| 934 | enum { |
| 935 | PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ |
| 936 | PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ |
| 937 | PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ |
| 938 | }; |
| 939 | |
| 940 | /* different Marvell PHY Ids */ |
| 941 | enum { |
| 942 | PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ |
| 943 | |
| 944 | PHY_BCOM_ID1_A1 = 0x6041, |
| 945 | PHY_BCOM_ID1_B2 = 0x6043, |
| 946 | PHY_BCOM_ID1_C0 = 0x6044, |
| 947 | PHY_BCOM_ID1_C5 = 0x6047, |
| 948 | |
Stephen Hemminger | 977bdf0 | 2006-02-22 11:44:58 -0800 | [diff] [blame] | 949 | PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 950 | PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ |
Stephen Hemminger | 977bdf0 | 2006-02-22 11:44:58 -0800 | [diff] [blame] | 951 | PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ |
| 952 | PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ |
| 953 | PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ |
| 954 | PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 955 | }; |
| 956 | |
| 957 | /* Advertisement register bits */ |
| 958 | enum { |
| 959 | PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ |
| 960 | PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ |
| 961 | PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ |
| 962 | |
| 963 | PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ |
| 964 | PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ |
| 965 | PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ |
| 966 | PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ |
| 967 | PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ |
| 968 | PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ |
| 969 | PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ |
| 970 | PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ |
| 971 | PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ |
| 972 | PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, |
| 973 | PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | |
| 974 | PHY_AN_100HALF | PHY_AN_100FULL, |
| 975 | }; |
| 976 | |
| 977 | /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ |
| 978 | /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ |
| 979 | enum { |
| 980 | PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ |
| 981 | PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ |
| 982 | PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ |
| 983 | PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ |
| 984 | PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ |
| 985 | PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ |
| 986 | /* Bit 9..8: reserved */ |
| 987 | PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ |
| 988 | }; |
| 989 | |
| 990 | /** Marvell-Specific */ |
| 991 | enum { |
| 992 | PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ |
| 993 | PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ |
| 994 | PHY_M_AN_RF = 1<<13, /* Remote Fault */ |
| 995 | |
| 996 | PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ |
| 997 | PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ |
| 998 | PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ |
| 999 | PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ |
| 1000 | PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ |
| 1001 | PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ |
| 1002 | PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ |
| 1003 | PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ |
| 1004 | }; |
| 1005 | |
| 1006 | /* special defines for FIBER (88E1011S only) */ |
| 1007 | enum { |
| 1008 | PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ |
| 1009 | PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ |
| 1010 | PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ |
| 1011 | PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ |
| 1012 | }; |
| 1013 | |
| 1014 | /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ |
| 1015 | enum { |
| 1016 | PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ |
| 1017 | PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ |
| 1018 | PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ |
| 1019 | PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ |
| 1020 | }; |
| 1021 | |
| 1022 | /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ |
| 1023 | enum { |
| 1024 | PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ |
| 1025 | PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ |
| 1026 | PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ |
| 1027 | PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ |
| 1028 | PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ |
| 1029 | PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ |
| 1030 | }; |
| 1031 | |
| 1032 | /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ |
| 1033 | enum { |
| 1034 | PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ |
| 1035 | PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ |
| 1036 | PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ |
| 1037 | PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ |
| 1038 | PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ |
| 1039 | PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ |
| 1040 | PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ |
| 1041 | PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ |
| 1042 | PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ |
| 1043 | PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ |
| 1044 | PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ |
| 1045 | PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ |
| 1046 | }; |
| 1047 | |
| 1048 | enum { |
| 1049 | PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ |
| 1050 | PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ |
| 1051 | }; |
| 1052 | |
| 1053 | #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) |
| 1054 | |
| 1055 | enum { |
| 1056 | PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ |
| 1057 | PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ |
| 1058 | PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ |
| 1059 | }; |
| 1060 | |
| 1061 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1062 | enum { |
| 1063 | PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ |
| 1064 | PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ |
| 1065 | PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ |
| 1066 | PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ |
| 1067 | PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ |
| 1068 | |
| 1069 | PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ |
| 1070 | PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ |
| 1071 | |
| 1072 | PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ |
| 1073 | PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ |
| 1074 | }; |
| 1075 | |
| 1076 | /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ |
| 1077 | enum { |
| 1078 | PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ |
| 1079 | PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ |
| 1080 | PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ |
| 1081 | PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ |
| 1082 | PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ |
| 1083 | PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ |
| 1084 | PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ |
| 1085 | PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ |
| 1086 | PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ |
| 1087 | PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ |
| 1088 | PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ |
| 1089 | PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ |
| 1090 | PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ |
| 1091 | PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ |
| 1092 | PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ |
| 1093 | PHY_M_PS_JABBER = 1<<0, /* Jabber */ |
| 1094 | }; |
| 1095 | |
| 1096 | #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) |
| 1097 | |
| 1098 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1099 | enum { |
| 1100 | PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ |
| 1101 | PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ |
| 1102 | }; |
| 1103 | |
| 1104 | enum { |
| 1105 | PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ |
| 1106 | PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ |
| 1107 | PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ |
| 1108 | PHY_M_IS_AN_PR = 1<<12, /* Page Received */ |
| 1109 | PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ |
| 1110 | PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ |
| 1111 | PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ |
| 1112 | PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ |
| 1113 | PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ |
| 1114 | PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ |
| 1115 | PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ |
| 1116 | PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ |
| 1117 | |
| 1118 | PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ |
| 1119 | PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ |
| 1120 | PHY_M_IS_JABBER = 1<<0, /* Jabber */ |
| 1121 | |
| 1122 | PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE |
| 1123 | | PHY_M_IS_FIFO_ERROR, |
| 1124 | PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, |
| 1125 | }; |
| 1126 | |
| 1127 | |
| 1128 | /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ |
| 1129 | enum { |
| 1130 | PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ |
| 1131 | PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ |
| 1132 | |
| 1133 | PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ |
| 1134 | PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ |
| 1135 | /* (88E1011 only) */ |
| 1136 | PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ |
| 1137 | /* (88E1011 only) */ |
| 1138 | PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ |
| 1139 | /* (88E1111 only) */ |
| 1140 | PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ |
| 1141 | /* !!! Errata in spec. (1 = disable) */ |
| 1142 | PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ |
| 1143 | PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ |
| 1144 | PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ |
| 1145 | PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ |
| 1146 | PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ |
| 1147 | PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; |
| 1148 | |
| 1149 | #define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK) |
| 1150 | /* 00=1x; 01=2x; 10=3x; 11=4x */ |
| 1151 | #define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK) |
| 1152 | /* 00=dis; 01=1x; 10=2x; 11=3x */ |
| 1153 | #define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2) |
| 1154 | /* 000=1x; 001=2x; 010=3x; 011=4x */ |
| 1155 | #define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK) |
| 1156 | /* 01X=0; 110=2.5; 111=25 (MHz) */ |
| 1157 | |
| 1158 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
| 1159 | enum { |
| 1160 | PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */ |
| 1161 | PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */ |
| 1162 | PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */ |
| 1163 | }; |
| 1164 | /* !!! Errata in spec. (1 = disable) */ |
| 1165 | |
| 1166 | #define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK) |
| 1167 | /* 100=5x; 101=6x; 110=7x; 111=8x */ |
| 1168 | enum { |
| 1169 | MAC_TX_CLK_0_MHZ = 2, |
| 1170 | MAC_TX_CLK_2_5_MHZ = 6, |
| 1171 | MAC_TX_CLK_25_MHZ = 7, |
| 1172 | }; |
| 1173 | |
| 1174 | /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ |
| 1175 | enum { |
| 1176 | PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ |
| 1177 | PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ |
| 1178 | PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ |
| 1179 | PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ |
| 1180 | PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ |
| 1181 | PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ |
| 1182 | PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ |
| 1183 | /* (88E1111 only) */ |
| 1184 | }; |
| 1185 | |
| 1186 | enum { |
| 1187 | PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ |
| 1188 | /* (88E1011 only) */ |
| 1189 | PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ |
| 1190 | PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ |
| 1191 | PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ |
| 1192 | PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ |
| 1193 | PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ |
| 1194 | }; |
| 1195 | |
| 1196 | #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK) |
| 1197 | |
| 1198 | /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ |
| 1199 | enum { |
| 1200 | PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */ |
| 1201 | PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ |
| 1202 | PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ |
| 1203 | PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ |
| 1204 | PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ |
| 1205 | PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ |
| 1206 | }; |
| 1207 | |
| 1208 | #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) |
| 1209 | #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) |
| 1210 | #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) |
| 1211 | #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) |
| 1212 | #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) |
| 1213 | #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) |
| 1214 | |
| 1215 | enum { |
| 1216 | PULS_NO_STR = 0,/* no pulse stretching */ |
| 1217 | PULS_21MS = 1,/* 21 ms to 42 ms */ |
| 1218 | PULS_42MS = 2,/* 42 ms to 84 ms */ |
| 1219 | PULS_84MS = 3,/* 84 ms to 170 ms */ |
| 1220 | PULS_170MS = 4,/* 170 ms to 340 ms */ |
| 1221 | PULS_340MS = 5,/* 340 ms to 670 ms */ |
| 1222 | PULS_670MS = 6,/* 670 ms to 1.3 s */ |
| 1223 | PULS_1300MS = 7,/* 1.3 s to 2.7 s */ |
| 1224 | }; |
| 1225 | |
| 1226 | #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK) |
| 1227 | |
| 1228 | enum { |
| 1229 | BLINK_42MS = 0,/* 42 ms */ |
| 1230 | BLINK_84MS = 1,/* 84 ms */ |
| 1231 | BLINK_170MS = 2,/* 170 ms */ |
| 1232 | BLINK_340MS = 3,/* 340 ms */ |
| 1233 | BLINK_670MS = 4,/* 670 ms */ |
| 1234 | }; |
| 1235 | |
| 1236 | /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ |
| 1237 | #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ |
| 1238 | /* Bit 13..12: reserved */ |
| 1239 | #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ |
| 1240 | #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ |
| 1241 | #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ |
| 1242 | #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ |
| 1243 | #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ |
| 1244 | #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ |
| 1245 | |
| 1246 | enum { |
| 1247 | MO_LED_NORM = 0, |
| 1248 | MO_LED_BLINK = 1, |
| 1249 | MO_LED_OFF = 2, |
| 1250 | MO_LED_ON = 3, |
| 1251 | }; |
| 1252 | |
| 1253 | /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ |
| 1254 | enum { |
| 1255 | PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ |
| 1256 | PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ |
| 1257 | PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ |
| 1258 | PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ |
| 1259 | PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ |
| 1260 | }; |
| 1261 | |
| 1262 | /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ |
| 1263 | enum { |
| 1264 | PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ |
| 1265 | PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ |
| 1266 | PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ |
| 1267 | PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ |
| 1268 | PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ |
| 1269 | PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ |
| 1270 | PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ |
| 1271 | /* (88E1111 only) */ |
| 1272 | |
| 1273 | PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ |
| 1274 | PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ |
| 1275 | PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ |
| 1276 | }; |
| 1277 | |
| 1278 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1279 | /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ |
| 1280 | /* Bit 15..12: reserved (used internally) */ |
| 1281 | enum { |
| 1282 | PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ |
| 1283 | PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ |
| 1284 | PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ |
| 1285 | }; |
| 1286 | |
| 1287 | #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK) |
| 1288 | #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK) |
| 1289 | #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK) |
| 1290 | |
| 1291 | enum { |
| 1292 | LED_PAR_CTRL_COLX = 0x00, |
| 1293 | LED_PAR_CTRL_ERROR = 0x01, |
| 1294 | LED_PAR_CTRL_DUPLEX = 0x02, |
| 1295 | LED_PAR_CTRL_DP_COL = 0x03, |
| 1296 | LED_PAR_CTRL_SPEED = 0x04, |
| 1297 | LED_PAR_CTRL_LINK = 0x05, |
| 1298 | LED_PAR_CTRL_TX = 0x06, |
| 1299 | LED_PAR_CTRL_RX = 0x07, |
| 1300 | LED_PAR_CTRL_ACT = 0x08, |
| 1301 | LED_PAR_CTRL_LNK_RX = 0x09, |
| 1302 | LED_PAR_CTRL_LNK_AC = 0x0a, |
| 1303 | LED_PAR_CTRL_ACT_BL = 0x0b, |
| 1304 | LED_PAR_CTRL_TX_BL = 0x0c, |
| 1305 | LED_PAR_CTRL_RX_BL = 0x0d, |
| 1306 | LED_PAR_CTRL_COL_BL = 0x0e, |
| 1307 | LED_PAR_CTRL_INACT = 0x0f |
| 1308 | }; |
| 1309 | |
| 1310 | /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ |
| 1311 | enum { |
| 1312 | PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ |
| 1313 | PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ |
| 1314 | PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ |
| 1315 | }; |
| 1316 | |
| 1317 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
| 1318 | /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ |
| 1319 | enum { |
| 1320 | PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ |
| 1321 | PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ |
| 1322 | PHY_M_MAC_MD_COPPER = 5,/* Copper only */ |
| 1323 | PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ |
| 1324 | }; |
| 1325 | #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) |
| 1326 | |
| 1327 | /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ |
| 1328 | enum { |
| 1329 | PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ |
| 1330 | PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ |
| 1331 | PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ |
| 1332 | PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ |
| 1333 | }; |
| 1334 | |
| 1335 | #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) |
| 1336 | #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) |
| 1337 | #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) |
| 1338 | #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) |
| 1339 | |
| 1340 | /* GMAC registers */ |
| 1341 | /* Port Registers */ |
| 1342 | enum { |
| 1343 | GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ |
| 1344 | GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ |
| 1345 | GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ |
| 1346 | GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ |
| 1347 | GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ |
| 1348 | GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ |
| 1349 | GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ |
| 1350 | /* Source Address Registers */ |
| 1351 | GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ |
| 1352 | GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ |
| 1353 | GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ |
| 1354 | GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ |
| 1355 | GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ |
| 1356 | GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ |
| 1357 | |
| 1358 | /* Multicast Address Hash Registers */ |
| 1359 | GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ |
| 1360 | GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ |
| 1361 | GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ |
| 1362 | GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ |
| 1363 | |
| 1364 | /* Interrupt Source Registers */ |
| 1365 | GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ |
| 1366 | GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ |
| 1367 | GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ |
| 1368 | |
| 1369 | /* Interrupt Mask Registers */ |
| 1370 | GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ |
| 1371 | GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ |
| 1372 | GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ |
| 1373 | |
| 1374 | /* Serial Management Interface (SMI) Registers */ |
| 1375 | GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ |
| 1376 | GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ |
| 1377 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ |
| 1378 | }; |
| 1379 | |
| 1380 | /* MIB Counters */ |
| 1381 | #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ |
| 1382 | #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ |
| 1383 | |
| 1384 | /* |
| 1385 | * MIB Counters base address definitions (low word) - |
| 1386 | * use offset 4 for access to high word (32 bit r/o) |
| 1387 | */ |
| 1388 | enum { |
| 1389 | GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ |
| 1390 | GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ |
| 1391 | GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ |
| 1392 | GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ |
| 1393 | GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ |
| 1394 | /* GM_MIB_CNT_BASE + 40: reserved */ |
| 1395 | GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ |
| 1396 | GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ |
| 1397 | GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ |
| 1398 | GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ |
| 1399 | GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ |
| 1400 | GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ |
| 1401 | GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ |
| 1402 | GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */ |
| 1403 | GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */ |
| 1404 | GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */ |
| 1405 | GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */ |
| 1406 | GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */ |
| 1407 | GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */ |
| 1408 | GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */ |
| 1409 | GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */ |
| 1410 | /* GM_MIB_CNT_BASE + 168: reserved */ |
| 1411 | GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */ |
| 1412 | /* GM_MIB_CNT_BASE + 184: reserved */ |
| 1413 | GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */ |
| 1414 | GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */ |
| 1415 | GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */ |
| 1416 | GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */ |
| 1417 | GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */ |
| 1418 | GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */ |
| 1419 | GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */ |
| 1420 | GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */ |
| 1421 | GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */ |
| 1422 | GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */ |
| 1423 | GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */ |
| 1424 | GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */ |
| 1425 | GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */ |
| 1426 | |
| 1427 | GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */ |
| 1428 | GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */ |
| 1429 | GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */ |
| 1430 | GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */ |
| 1431 | GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */ |
| 1432 | GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */ |
| 1433 | }; |
| 1434 | |
| 1435 | /* GMAC Bit Definitions */ |
| 1436 | /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ |
| 1437 | enum { |
| 1438 | GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ |
| 1439 | GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ |
| 1440 | GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ |
| 1441 | GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ |
| 1442 | GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ |
| 1443 | GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ |
| 1444 | GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */ |
| 1445 | GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */ |
| 1446 | |
| 1447 | GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ |
| 1448 | GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ |
| 1449 | GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ |
| 1450 | GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ |
| 1451 | GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ |
| 1452 | }; |
| 1453 | |
| 1454 | /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ |
| 1455 | enum { |
| 1456 | GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ |
| 1457 | GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ |
| 1458 | GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ |
| 1459 | GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ |
| 1460 | GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ |
| 1461 | GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ |
| 1462 | GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ |
| 1463 | GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ |
| 1464 | GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ |
| 1465 | GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ |
| 1466 | GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ |
| 1467 | GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ |
| 1468 | GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ |
| 1469 | GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ |
| 1470 | GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ |
| 1471 | }; |
| 1472 | |
| 1473 | #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) |
| 1474 | #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) |
| 1475 | |
| 1476 | /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ |
| 1477 | enum { |
| 1478 | GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ |
| 1479 | GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ |
| 1480 | GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ |
| 1481 | GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */ |
| 1482 | }; |
| 1483 | |
| 1484 | #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) |
| 1485 | #define TX_COL_DEF 0x04 |
| 1486 | |
| 1487 | /* GM_RX_CTRL 16 bit r/w Receive Control Register */ |
| 1488 | enum { |
| 1489 | GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ |
| 1490 | GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ |
| 1491 | GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ |
| 1492 | GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ |
| 1493 | }; |
| 1494 | |
| 1495 | /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ |
| 1496 | enum { |
| 1497 | GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ |
| 1498 | GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ |
| 1499 | GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ |
| 1500 | GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */ |
| 1501 | |
| 1502 | TX_JAM_LEN_DEF = 0x03, |
| 1503 | TX_JAM_IPG_DEF = 0x0b, |
| 1504 | TX_IPG_JAM_DEF = 0x1c, |
| 1505 | TX_BOF_LIM_DEF = 0x04, |
| 1506 | }; |
| 1507 | |
| 1508 | #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) |
| 1509 | #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) |
| 1510 | #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) |
| 1511 | #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) |
| 1512 | |
| 1513 | |
| 1514 | /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ |
| 1515 | enum { |
| 1516 | GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ |
| 1517 | GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ |
| 1518 | GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ |
| 1519 | GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ |
| 1520 | GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ |
| 1521 | }; |
| 1522 | |
| 1523 | #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) |
| 1524 | #define DATA_BLIND_DEF 0x04 |
| 1525 | |
| 1526 | #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) |
| 1527 | #define IPG_DATA_DEF 0x1e |
| 1528 | |
| 1529 | /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ |
| 1530 | enum { |
| 1531 | GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ |
| 1532 | GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ |
| 1533 | GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ |
| 1534 | GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ |
| 1535 | GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ |
| 1536 | }; |
| 1537 | |
| 1538 | #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) |
| 1539 | #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) |
| 1540 | |
| 1541 | /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ |
| 1542 | enum { |
| 1543 | GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ |
| 1544 | GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ |
| 1545 | }; |
| 1546 | |
| 1547 | /* Receive Frame Status Encoding */ |
| 1548 | enum { |
| 1549 | GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1550 | GMR_FS_VLAN = 1<<13, /* VLAN Packet */ |
| 1551 | GMR_FS_JABBER = 1<<12, /* Jabber Packet */ |
| 1552 | GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */ |
| 1553 | GMR_FS_MC = 1<<10, /* Multicast Packet */ |
| 1554 | GMR_FS_BC = 1<<9, /* Broadcast Packet */ |
| 1555 | GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */ |
| 1556 | GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */ |
| 1557 | GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */ |
| 1558 | GMR_FS_MII_ERR = 1<<5, /* MII Error */ |
| 1559 | GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */ |
| 1560 | GMR_FS_FRAGMENT = 1<<3, /* Fragment */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1561 | |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1562 | GMR_FS_CRC_ERR = 1<<1, /* CRC Error */ |
| 1563 | GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1564 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1565 | GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | |
| 1566 | GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | |
| 1567 | GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | |
| 1568 | GMR_FS_UN_SIZE | GMR_FS_JABBER, |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1569 | }; |
| 1570 | |
| 1571 | /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ |
| 1572 | enum { |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1573 | RX_TRUNC_ON = 1<<27, /* enable packet truncation */ |
| 1574 | RX_TRUNC_OFF = 1<<26, /* disable packet truncation */ |
| 1575 | RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */ |
| 1576 | RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */ |
| 1577 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1578 | GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ |
| 1579 | GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ |
| 1580 | GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ |
| 1581 | |
| 1582 | GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ |
| 1583 | GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ |
| 1584 | GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ |
| 1585 | GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ |
| 1586 | GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ |
| 1587 | GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1588 | GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */ |
| 1589 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1590 | GMF_OPER_ON = 1<<3, /* Operational Mode On */ |
| 1591 | GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ |
| 1592 | GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ |
| 1593 | GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ |
| 1594 | |
| 1595 | RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ |
shemminger@osdl.org | d1f1370 | 2005-09-27 15:02:57 -0700 | [diff] [blame] | 1596 | |
| 1597 | GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON, |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1598 | }; |
| 1599 | |
| 1600 | |
| 1601 | /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ |
| 1602 | enum { |
shemminger@osdl.org | 5a5b1ea | 2005-11-30 11:45:15 -0800 | [diff] [blame] | 1603 | TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ |
| 1604 | TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ |
| 1605 | |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1606 | TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ |
| 1607 | TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ |
| 1608 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1609 | GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ |
| 1610 | GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ |
| 1611 | GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ |
| 1612 | |
| 1613 | GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ |
| 1614 | GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ |
| 1615 | GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ |
| 1616 | }; |
| 1617 | |
| 1618 | /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ |
| 1619 | enum { |
| 1620 | GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ |
| 1621 | GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ |
| 1622 | GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ |
| 1623 | }; |
| 1624 | |
| 1625 | /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ |
| 1626 | enum { |
| 1627 | Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */ |
| 1628 | Y2_ASF_RESET = 1<<3, /* ASF system in reset state */ |
| 1629 | Y2_ASF_RUNNING = 1<<2, /* ASF system operational */ |
| 1630 | Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */ |
| 1631 | Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */ |
| 1632 | |
| 1633 | Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */ |
| 1634 | Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */ |
| 1635 | }; |
| 1636 | |
| 1637 | /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ |
| 1638 | enum { |
| 1639 | Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ |
| 1640 | Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ |
| 1641 | }; |
| 1642 | |
| 1643 | /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ |
| 1644 | enum { |
| 1645 | SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */ |
| 1646 | SC_STAT_OP_ON = 1<<3, /* Operational Mode On */ |
| 1647 | SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */ |
| 1648 | SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ |
| 1649 | SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ |
| 1650 | }; |
| 1651 | |
| 1652 | /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ |
| 1653 | enum { |
| 1654 | GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ |
| 1655 | GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ |
| 1656 | GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ |
| 1657 | GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ |
| 1658 | GMC_PAUSE_ON = 1<<3, /* Pause On */ |
| 1659 | GMC_PAUSE_OFF = 1<<2, /* Pause Off */ |
| 1660 | GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ |
| 1661 | GMC_RST_SET = 1<<0, /* Set GMAC Reset */ |
| 1662 | }; |
| 1663 | |
| 1664 | /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ |
| 1665 | enum { |
| 1666 | GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */ |
| 1667 | GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */ |
| 1668 | GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */ |
| 1669 | GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */ |
| 1670 | GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */ |
| 1671 | GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */ |
| 1672 | GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */ |
| 1673 | GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */ |
| 1674 | GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */ |
| 1675 | GPC_ANEG_0 = 1<<19, /* ANEG[0] */ |
| 1676 | GPC_ENA_XC = 1<<18, /* Enable MDI crossover */ |
| 1677 | GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */ |
| 1678 | GPC_ANEG_3 = 1<<16, /* ANEG[3] */ |
| 1679 | GPC_ANEG_2 = 1<<15, /* ANEG[2] */ |
| 1680 | GPC_ANEG_1 = 1<<14, /* ANEG[1] */ |
| 1681 | GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */ |
| 1682 | GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */ |
| 1683 | GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */ |
| 1684 | GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */ |
| 1685 | GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */ |
| 1686 | GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */ |
| 1687 | /* Bits 7..2: reserved */ |
| 1688 | GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ |
| 1689 | GPC_RST_SET = 1<<0, /* Set GPHY Reset */ |
| 1690 | }; |
| 1691 | |
| 1692 | /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ |
| 1693 | /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ |
| 1694 | enum { |
| 1695 | GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ |
| 1696 | GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ |
| 1697 | GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ |
| 1698 | GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ |
| 1699 | GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ |
| 1700 | GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ |
| 1701 | |
Stephen Hemminger | 79e57d3 | 2005-09-19 15:42:33 -0700 | [diff] [blame] | 1702 | #define GMAC_DEF_MSK GM_IS_TX_FF_UR |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1703 | |
| 1704 | /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ |
| 1705 | /* Bits 15.. 2: reserved */ |
| 1706 | GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ |
| 1707 | GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ |
| 1708 | |
| 1709 | |
| 1710 | /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ |
| 1711 | WOL_CTL_LINK_CHG_OCC = 1<<15, |
| 1712 | WOL_CTL_MAGIC_PKT_OCC = 1<<14, |
| 1713 | WOL_CTL_PATTERN_OCC = 1<<13, |
| 1714 | WOL_CTL_CLEAR_RESULT = 1<<12, |
| 1715 | WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, |
| 1716 | WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, |
| 1717 | WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, |
| 1718 | WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, |
| 1719 | WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, |
| 1720 | WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, |
| 1721 | WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, |
| 1722 | WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, |
| 1723 | WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, |
| 1724 | WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, |
| 1725 | WOL_CTL_ENA_PATTERN_UNIT = 1<<1, |
| 1726 | WOL_CTL_DIS_PATTERN_UNIT = 1<<0, |
| 1727 | }; |
| 1728 | |
| 1729 | #define WOL_CTL_DEFAULT \ |
| 1730 | (WOL_CTL_DIS_PME_ON_LINK_CHG | \ |
| 1731 | WOL_CTL_DIS_PME_ON_PATTERN | \ |
| 1732 | WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ |
| 1733 | WOL_CTL_DIS_LINK_CHG_UNIT | \ |
| 1734 | WOL_CTL_DIS_PATTERN_UNIT | \ |
| 1735 | WOL_CTL_DIS_MAGIC_PKT_UNIT) |
| 1736 | |
| 1737 | /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ |
| 1738 | #define WOL_CTL_PATT_ENA(x) (1 << (x)) |
| 1739 | |
| 1740 | |
| 1741 | /* Control flags */ |
| 1742 | enum { |
| 1743 | UDPTCP = 1<<0, |
| 1744 | CALSUM = 1<<1, |
| 1745 | WR_SUM = 1<<2, |
| 1746 | INIT_SUM= 1<<3, |
| 1747 | LOCK_SUM= 1<<4, |
| 1748 | INS_VLAN= 1<<5, |
| 1749 | FRC_STAT= 1<<6, |
| 1750 | EOP = 1<<7, |
| 1751 | }; |
| 1752 | |
| 1753 | enum { |
| 1754 | HW_OWNER = 1<<7, |
| 1755 | OP_TCPWRITE = 0x11, |
| 1756 | OP_TCPSTART = 0x12, |
| 1757 | OP_TCPINIT = 0x14, |
| 1758 | OP_TCPLCK = 0x18, |
| 1759 | OP_TCPCHKSUM = OP_TCPSTART, |
| 1760 | OP_TCPIS = OP_TCPINIT | OP_TCPSTART, |
| 1761 | OP_TCPLW = OP_TCPLCK | OP_TCPWRITE, |
| 1762 | OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, |
| 1763 | OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, |
| 1764 | |
| 1765 | OP_ADDR64 = 0x21, |
| 1766 | OP_VLAN = 0x22, |
| 1767 | OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, |
| 1768 | OP_LRGLEN = 0x24, |
| 1769 | OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, |
| 1770 | OP_BUFFER = 0x40, |
| 1771 | OP_PACKET = 0x41, |
| 1772 | OP_LARGESEND = 0x43, |
| 1773 | |
| 1774 | /* YUKON-2 STATUS opcodes defines */ |
| 1775 | OP_RXSTAT = 0x60, |
| 1776 | OP_RXTIMESTAMP = 0x61, |
| 1777 | OP_RXVLAN = 0x62, |
| 1778 | OP_RXCHKS = 0x64, |
| 1779 | OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, |
| 1780 | OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, |
| 1781 | OP_RSS_HASH = 0x65, |
| 1782 | OP_TXINDEXLE = 0x68, |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1783 | }; |
| 1784 | |
| 1785 | /* Yukon 2 hardware interface |
| 1786 | * Not tested on big endian |
| 1787 | */ |
| 1788 | struct sky2_tx_le { |
| 1789 | union { |
shemminger@osdl.org | 65497da | 2005-11-30 11:45:20 -0800 | [diff] [blame] | 1790 | __le32 addr; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1791 | struct { |
shemminger@osdl.org | 65497da | 2005-11-30 11:45:20 -0800 | [diff] [blame] | 1792 | __le16 offset; |
| 1793 | __le16 start; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1794 | } csum __attribute((packed)); |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1795 | struct { |
shemminger@osdl.org | 65497da | 2005-11-30 11:45:20 -0800 | [diff] [blame] | 1796 | __le16 size; |
| 1797 | __le16 rsvd; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1798 | } tso __attribute((packed)); |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1799 | } tx; |
shemminger@osdl.org | 65497da | 2005-11-30 11:45:20 -0800 | [diff] [blame] | 1800 | __le16 length; /* also vlan tag or checksum start */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1801 | u8 ctrl; |
| 1802 | u8 opcode; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1803 | } __attribute((packed)); |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1804 | |
| 1805 | struct sky2_rx_le { |
shemminger@osdl.org | 65497da | 2005-11-30 11:45:20 -0800 | [diff] [blame] | 1806 | __le32 addr; |
| 1807 | __le16 length; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1808 | u8 ctrl; |
| 1809 | u8 opcode; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1810 | } __attribute((packed));; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1811 | |
| 1812 | struct sky2_status_le { |
shemminger@osdl.org | 65497da | 2005-11-30 11:45:20 -0800 | [diff] [blame] | 1813 | __le32 status; /* also checksum */ |
| 1814 | __le16 length; /* also vlan tag */ |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1815 | u8 link; |
| 1816 | u8 opcode; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1817 | } __attribute((packed)); |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1818 | |
Stephen Hemminger | 6cdbbdf | 2005-12-09 11:35:01 -0800 | [diff] [blame] | 1819 | struct tx_ring_info { |
| 1820 | struct sk_buff *skb; |
| 1821 | DECLARE_PCI_UNMAP_ADDR(mapaddr); |
| 1822 | u16 idx; |
| 1823 | }; |
| 1824 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1825 | struct ring_info { |
| 1826 | struct sk_buff *skb; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1827 | dma_addr_t mapaddr; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1828 | }; |
| 1829 | |
| 1830 | struct sky2_port { |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1831 | struct sky2_hw *hw; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1832 | struct net_device *netdev; |
| 1833 | unsigned port; |
| 1834 | u32 msg_enable; |
| 1835 | |
Stephen Hemminger | 6e23231 | 2005-12-09 11:34:54 -0800 | [diff] [blame] | 1836 | spinlock_t tx_lock ____cacheline_aligned_in_smp; |
Stephen Hemminger | 6cdbbdf | 2005-12-09 11:35:01 -0800 | [diff] [blame] | 1837 | struct tx_ring_info *tx_ring; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1838 | struct sky2_tx_le *tx_le; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1839 | u16 tx_cons; /* next le to check */ |
| 1840 | u16 tx_prod; /* next le to use */ |
Stephen Hemminger | 6e23231 | 2005-12-09 11:34:54 -0800 | [diff] [blame] | 1841 | u32 tx_addr64; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1842 | u16 tx_pending; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1843 | u16 tx_last_put; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1844 | u16 tx_last_mss; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1845 | |
Stephen Hemminger | 6e23231 | 2005-12-09 11:34:54 -0800 | [diff] [blame] | 1846 | struct ring_info *rx_ring ____cacheline_aligned_in_smp; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1847 | struct sky2_rx_le *rx_le; |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1848 | u32 rx_addr64; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1849 | u16 rx_next; /* next re to check */ |
| 1850 | u16 rx_put; /* next le index to use */ |
Stephen Hemminger | 793b883 | 2005-09-14 16:06:14 -0700 | [diff] [blame] | 1851 | u16 rx_pending; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1852 | u16 rx_last_put; |
Stephen Hemminger | 734d186 | 2005-12-09 11:35:00 -0800 | [diff] [blame] | 1853 | u16 rx_bufsize; |
shemminger@osdl.org | d1f1370 | 2005-09-27 15:02:57 -0700 | [diff] [blame] | 1854 | #ifdef SKY2_VLAN_TAG_USED |
| 1855 | u16 rx_tag; |
| 1856 | struct vlan_group *vlgrp; |
| 1857 | #endif |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1858 | |
| 1859 | dma_addr_t rx_le_map; |
| 1860 | dma_addr_t tx_le_map; |
| 1861 | u32 advertising; /* ADVERTISED_ bits */ |
| 1862 | u16 speed; /* SPEED_1000, SPEED_100, ... */ |
| 1863 | u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */ |
| 1864 | u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ |
| 1865 | u8 rx_pause; |
| 1866 | u8 tx_pause; |
| 1867 | u8 rx_csum; |
| 1868 | u8 wol; |
| 1869 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1870 | struct net_device_stats net_stats; |
Stephen Hemminger | 91c86df | 2005-12-09 11:34:57 -0800 | [diff] [blame] | 1871 | |
| 1872 | struct work_struct phy_task; |
| 1873 | struct semaphore phy_sema; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1874 | }; |
| 1875 | |
| 1876 | struct sky2_hw { |
| 1877 | void __iomem *regs; |
| 1878 | struct pci_dev *pdev; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1879 | struct net_device *dev[2]; |
Stephen Hemminger | 791917d | 2006-02-22 11:45:03 -0800 | [diff] [blame] | 1880 | spinlock_t hw_lock; |
| 1881 | u32 intr_mask; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1882 | |
shemminger@osdl.org | 5afa0a9 | 2005-09-27 15:03:00 -0700 | [diff] [blame] | 1883 | int pm_cap; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1884 | u8 chip_id; |
| 1885 | u8 chip_rev; |
| 1886 | u8 copper; |
| 1887 | u8 ports; |
| 1888 | |
| 1889 | struct sky2_status_le *st_le; |
| 1890 | u32 st_idx; |
| 1891 | dma_addr_t st_dma; |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1892 | }; |
| 1893 | |
| 1894 | /* Register accessor for memory mapped device */ |
| 1895 | static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) |
| 1896 | { |
| 1897 | return readl(hw->regs + reg); |
| 1898 | } |
| 1899 | |
| 1900 | static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) |
| 1901 | { |
| 1902 | return readw(hw->regs + reg); |
| 1903 | } |
| 1904 | |
| 1905 | static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) |
| 1906 | { |
| 1907 | return readb(hw->regs + reg); |
| 1908 | } |
| 1909 | |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1910 | static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) |
| 1911 | { |
| 1912 | writel(val, hw->regs + reg); |
| 1913 | } |
| 1914 | |
| 1915 | static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) |
| 1916 | { |
| 1917 | writew(val, hw->regs + reg); |
| 1918 | } |
| 1919 | |
| 1920 | static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) |
| 1921 | { |
| 1922 | writeb(val, hw->regs + reg); |
| 1923 | } |
| 1924 | |
| 1925 | /* Yukon PHY related registers */ |
| 1926 | #define SK_GMAC_REG(port,reg) \ |
| 1927 | (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) |
| 1928 | #define GM_PHY_RETRIES 100 |
| 1929 | |
| 1930 | static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) |
| 1931 | { |
| 1932 | return sky2_read16(hw, SK_GMAC_REG(port,reg)); |
| 1933 | } |
| 1934 | |
| 1935 | static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) |
| 1936 | { |
| 1937 | unsigned base = SK_GMAC_REG(port, reg); |
| 1938 | return (u32) sky2_read16(hw, base) |
| 1939 | | (u32) sky2_read16(hw, base+4) << 16; |
| 1940 | } |
| 1941 | |
| 1942 | static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) |
| 1943 | { |
| 1944 | sky2_write16(hw, SK_GMAC_REG(port,r), v); |
| 1945 | } |
| 1946 | |
| 1947 | static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, |
| 1948 | const u8 *addr) |
| 1949 | { |
| 1950 | gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); |
| 1951 | gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); |
| 1952 | gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); |
| 1953 | } |
Stephen Hemminger | 56a645c | 2006-02-22 11:45:02 -0800 | [diff] [blame] | 1954 | |
| 1955 | /* PCI config space access */ |
| 1956 | static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) |
| 1957 | { |
| 1958 | return sky2_read32(hw, Y2_CFG_SPC + reg); |
| 1959 | } |
| 1960 | |
| 1961 | static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) |
| 1962 | { |
| 1963 | return sky2_read16(hw, Y2_CFG_SPC + reg); |
| 1964 | } |
| 1965 | |
| 1966 | static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) |
| 1967 | { |
| 1968 | sky2_write32(hw, Y2_CFG_SPC + reg, val); |
| 1969 | } |
| 1970 | |
| 1971 | static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) |
| 1972 | { |
| 1973 | sky2_write16(hw, Y2_CFG_SPC + reg, val); |
| 1974 | } |
Stephen Hemminger | cd28ab6 | 2005-08-16 16:36:49 -0700 | [diff] [blame] | 1975 | #endif |