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gerrit-public.fairphone.software / kernel / msm-4.19 / 032d774575dfed145e4477b47579fd51d9c102b3 / . / arch / arm / boot / dts / dra7xx-clocks.dtsi
blob: c7676871d9c0240032261ed40f0db7c431a583d8 [file] [log] [blame]
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1/*
2 * Device Tree Source for DRA7xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&cm_core_aon_clocks {
11 atl_clkin0_ck: atl_clkin0_ck {
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <0>;
15 };
16
17 atl_clkin1_ck: atl_clkin1_ck {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
21 };
22
23 atl_clkin2_ck: atl_clkin2_ck {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <0>;
27 };
28
29 atlclkin3_ck: atlclkin3_ck {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <0>;
33 };
34
35 hdmi_clkin_ck: hdmi_clkin_ck {
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
39 };
40
41 mlb_clkin_ck: mlb_clkin_ck {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
45 };
46
47 mlbp_clkin_ck: mlbp_clkin_ck {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
51 };
52
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
57 };
58
59 ref_clkin0_ck: ref_clkin0_ck {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
63 };
64
65 ref_clkin1_ck: ref_clkin1_ck {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
69 };
70
71 ref_clkin2_ck: ref_clkin2_ck {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 ref_clkin3_ck: ref_clkin3_ck {
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
81 };
82
83 rmii_clk_ck: rmii_clk_ck {
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
87 };
88
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
93 };
94
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 };
100
101 sys_32k_ck: sys_32k_ck {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
105 };
106
107 virt_12000000_ck: virt_12000000_ck {
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
110 clock-frequency = <12000000>;
111 };
112
113 virt_13000000_ck: virt_13000000_ck {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <13000000>;
117 };
118
119 virt_16800000_ck: virt_16800000_ck {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 clock-frequency = <16800000>;
123 };
124
125 virt_19200000_ck: virt_19200000_ck {
126 #clock-cells = <0>;
127 compatible = "fixed-clock";
128 clock-frequency = <19200000>;
129 };
130
131 virt_20000000_ck: virt_20000000_ck {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <20000000>;
135 };
136
137 virt_26000000_ck: virt_26000000_ck {
138 #clock-cells = <0>;
139 compatible = "fixed-clock";
140 clock-frequency = <26000000>;
141 };
142
143 virt_27000000_ck: virt_27000000_ck {
144 #clock-cells = <0>;
145 compatible = "fixed-clock";
146 clock-frequency = <27000000>;
147 };
148
149 virt_38400000_ck: virt_38400000_ck {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <38400000>;
153 };
154
155 sys_clkin2: sys_clkin2 {
156 #clock-cells = <0>;
157 compatible = "fixed-clock";
158 clock-frequency = <22579200>;
159 };
160
161 usb_otg_clkin_ck: usb_otg_clkin_ck {
162 #clock-cells = <0>;
163 compatible = "fixed-clock";
164 clock-frequency = <0>;
165 };
166
167 video1_clkin_ck: video1_clkin_ck {
168 #clock-cells = <0>;
169 compatible = "fixed-clock";
170 clock-frequency = <0>;
171 };
172
173 video1_m2_clkin_ck: video1_m2_clkin_ck {
174 #clock-cells = <0>;
175 compatible = "fixed-clock";
176 clock-frequency = <0>;
177 };
178
179 video2_clkin_ck: video2_clkin_ck {
180 #clock-cells = <0>;
181 compatible = "fixed-clock";
182 clock-frequency = <0>;
183 };
184
185 video2_m2_clkin_ck: video2_m2_clkin_ck {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-frequency = <0>;
189 };
190
191 dpll_abe_ck: dpll_abe_ck {
192 #clock-cells = <0>;
193 compatible = "ti,omap4-dpll-m4xen-clock";
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
195 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
196 };
197
198 dpll_abe_x2_ck: dpll_abe_x2_ck {
199 #clock-cells = <0>;
200 compatible = "ti,omap4-dpll-x2-clock";
201 clocks = <&dpll_abe_ck>;
202 };
203
204 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
205 #clock-cells = <0>;
206 compatible = "ti,divider-clock";
207 clocks = <&dpll_abe_x2_ck>;
208 ti,max-div = <31>;
209 ti,autoidle-shift = <8>;
210 reg = <0x01f0>;
211 ti,index-starts-at-one;
212 ti,invert-autoidle-bit;
213 };
214
215 abe_clk: abe_clk {
216 #clock-cells = <0>;
217 compatible = "ti,divider-clock";
218 clocks = <&dpll_abe_m2x2_ck>;
219 ti,max-div = <4>;
220 reg = <0x0108>;
221 ti,index-power-of-two;
222 };
223
224 dpll_abe_m2_ck: dpll_abe_m2_ck {
225 #clock-cells = <0>;
226 compatible = "ti,divider-clock";
227 clocks = <&dpll_abe_ck>;
228 ti,max-div = <31>;
229 ti,autoidle-shift = <8>;
230 reg = <0x01f0>;
231 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
233 };
234
235 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
236 #clock-cells = <0>;
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_abe_x2_ck>;
239 ti,max-div = <31>;
240 ti,autoidle-shift = <8>;
241 reg = <0x01f4>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
244 };
245
246 dpll_core_ck: dpll_core_ck {
247 #clock-cells = <0>;
248 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
251 };
252
253 dpll_core_x2_ck: dpll_core_x2_ck {
254 #clock-cells = <0>;
255 compatible = "ti,omap4-dpll-x2-clock";
256 clocks = <&dpll_core_ck>;
257 };
258
259 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
260 #clock-cells = <0>;
261 compatible = "ti,divider-clock";
262 clocks = <&dpll_core_x2_ck>;
263 ti,max-div = <63>;
264 ti,autoidle-shift = <8>;
265 reg = <0x013c>;
266 ti,index-starts-at-one;
267 ti,invert-autoidle-bit;
268 };
269
270 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
271 #clock-cells = <0>;
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll_core_h12x2_ck>;
274 clock-mult = <1>;
275 clock-div = <1>;
276 };
277
278 dpll_mpu_ck: dpll_mpu_ck {
279 #clock-cells = <0>;
280 compatible = "ti,omap4-dpll-clock";
281 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
282 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
283 };
284
285 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
286 #clock-cells = <0>;
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_mpu_ck>;
289 ti,max-div = <31>;
290 ti,autoidle-shift = <8>;
291 reg = <0x0170>;
292 ti,index-starts-at-one;
293 ti,invert-autoidle-bit;
294 };
295
296 mpu_dclk_div: mpu_dclk_div {
297 #clock-cells = <0>;
298 compatible = "fixed-factor-clock";
299 clocks = <&dpll_mpu_m2_ck>;
300 clock-mult = <1>;
301 clock-div = <1>;
302 };
303
304 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
305 #clock-cells = <0>;
306 compatible = "fixed-factor-clock";
307 clocks = <&dpll_core_h12x2_ck>;
308 clock-mult = <1>;
309 clock-div = <1>;
310 };
311
312 dpll_dsp_ck: dpll_dsp_ck {
313 #clock-cells = <0>;
314 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
317 };
318
319 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
320 #clock-cells = <0>;
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_dsp_ck>;
323 ti,max-div = <31>;
324 ti,autoidle-shift = <8>;
325 reg = <0x0244>;
326 ti,index-starts-at-one;
327 ti,invert-autoidle-bit;
328 };
329
330 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
331 #clock-cells = <0>;
332 compatible = "fixed-factor-clock";
333 clocks = <&dpll_core_h12x2_ck>;
334 clock-mult = <1>;
335 clock-div = <1>;
336 };
337
338 dpll_iva_ck: dpll_iva_ck {
339 #clock-cells = <0>;
340 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
343 };
344
345 dpll_iva_m2_ck: dpll_iva_m2_ck {
346 #clock-cells = <0>;
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_iva_ck>;
349 ti,max-div = <31>;
350 ti,autoidle-shift = <8>;
351 reg = <0x01b0>;
352 ti,index-starts-at-one;
353 ti,invert-autoidle-bit;
354 };
355
356 iva_dclk: iva_dclk {
357 #clock-cells = <0>;
358 compatible = "fixed-factor-clock";
359 clocks = <&dpll_iva_m2_ck>;
360 clock-mult = <1>;
361 clock-div = <1>;
362 };
363
364 dpll_gpu_ck: dpll_gpu_ck {
365 #clock-cells = <0>;
366 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
369 };
370
371 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
372 #clock-cells = <0>;
373 compatible = "ti,divider-clock";
374 clocks = <&dpll_gpu_ck>;
375 ti,max-div = <31>;
376 ti,autoidle-shift = <8>;
377 reg = <0x02e8>;
378 ti,index-starts-at-one;
379 ti,invert-autoidle-bit;
380 };
381
382 dpll_core_m2_ck: dpll_core_m2_ck {
383 #clock-cells = <0>;
384 compatible = "ti,divider-clock";
385 clocks = <&dpll_core_ck>;
386 ti,max-div = <31>;
387 ti,autoidle-shift = <8>;
388 reg = <0x0130>;
389 ti,index-starts-at-one;
390 ti,invert-autoidle-bit;
391 };
392
393 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
394 #clock-cells = <0>;
395 compatible = "fixed-factor-clock";
396 clocks = <&dpll_core_m2_ck>;
397 clock-mult = <1>;
398 clock-div = <1>;
399 };
400
401 dpll_ddr_ck: dpll_ddr_ck {
402 #clock-cells = <0>;
403 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
406 };
407
408 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
409 #clock-cells = <0>;
410 compatible = "ti,divider-clock";
411 clocks = <&dpll_ddr_ck>;
412 ti,max-div = <31>;
413 ti,autoidle-shift = <8>;
414 reg = <0x0220>;
415 ti,index-starts-at-one;
416 ti,invert-autoidle-bit;
417 };
418
419 dpll_gmac_ck: dpll_gmac_ck {
420 #clock-cells = <0>;
421 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
424 };
425
426 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
427 #clock-cells = <0>;
428 compatible = "ti,divider-clock";
429 clocks = <&dpll_gmac_ck>;
430 ti,max-div = <31>;
431 ti,autoidle-shift = <8>;
432 reg = <0x02b8>;
433 ti,index-starts-at-one;
434 ti,invert-autoidle-bit;
435 };
436
437 video2_dclk_div: video2_dclk_div {
438 #clock-cells = <0>;
439 compatible = "fixed-factor-clock";
440 clocks = <&video2_m2_clkin_ck>;
441 clock-mult = <1>;
442 clock-div = <1>;
443 };
444
445 video1_dclk_div: video1_dclk_div {
446 #clock-cells = <0>;
447 compatible = "fixed-factor-clock";
448 clocks = <&video1_m2_clkin_ck>;
449 clock-mult = <1>;
450 clock-div = <1>;
451 };
452
453 hdmi_dclk_div: hdmi_dclk_div {
454 #clock-cells = <0>;
455 compatible = "fixed-factor-clock";
456 clocks = <&hdmi_clkin_ck>;
457 clock-mult = <1>;
458 clock-div = <1>;
459 };
460
461 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
462 #clock-cells = <0>;
463 compatible = "fixed-factor-clock";
464 clocks = <&dpll_abe_m3x2_ck>;
465 clock-mult = <1>;
466 clock-div = <2>;
467 };
468
469 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
470 #clock-cells = <0>;
471 compatible = "fixed-factor-clock";
472 clocks = <&dpll_abe_m3x2_ck>;
473 clock-mult = <1>;
474 clock-div = <3>;
475 };
476
477 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
478 #clock-cells = <0>;
479 compatible = "fixed-factor-clock";
480 clocks = <&dpll_core_h12x2_ck>;
481 clock-mult = <1>;
482 clock-div = <1>;
483 };
484
485 dpll_eve_ck: dpll_eve_ck {
486 #clock-cells = <0>;
487 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
490 };
491
492 dpll_eve_m2_ck: dpll_eve_m2_ck {
493 #clock-cells = <0>;
494 compatible = "ti,divider-clock";
495 clocks = <&dpll_eve_ck>;
496 ti,max-div = <31>;
497 ti,autoidle-shift = <8>;
498 reg = <0x0294>;
499 ti,index-starts-at-one;
500 ti,invert-autoidle-bit;
501 };
502
503 eve_dclk_div: eve_dclk_div {
504 #clock-cells = <0>;
505 compatible = "fixed-factor-clock";
506 clocks = <&dpll_eve_m2_ck>;
507 clock-mult = <1>;
508 clock-div = <1>;
509 };
510
511 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
512 #clock-cells = <0>;
513 compatible = "ti,divider-clock";
514 clocks = <&dpll_core_x2_ck>;
515 ti,max-div = <63>;
516 ti,autoidle-shift = <8>;
517 reg = <0x0140>;
518 ti,index-starts-at-one;
519 ti,invert-autoidle-bit;
520 };
521
522 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
523 #clock-cells = <0>;
524 compatible = "ti,divider-clock";
525 clocks = <&dpll_core_x2_ck>;
526 ti,max-div = <63>;
527 ti,autoidle-shift = <8>;
528 reg = <0x0144>;
529 ti,index-starts-at-one;
530 ti,invert-autoidle-bit;
531 };
532
533 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
534 #clock-cells = <0>;
535 compatible = "ti,divider-clock";
536 clocks = <&dpll_core_x2_ck>;
537 ti,max-div = <63>;
538 ti,autoidle-shift = <8>;
539 reg = <0x0154>;
540 ti,index-starts-at-one;
541 ti,invert-autoidle-bit;
542 };
543
544 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
545 #clock-cells = <0>;
546 compatible = "ti,divider-clock";
547 clocks = <&dpll_core_x2_ck>;
548 ti,max-div = <63>;
549 ti,autoidle-shift = <8>;
550 reg = <0x0158>;
551 ti,index-starts-at-one;
552 ti,invert-autoidle-bit;
553 };
554
555 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
556 #clock-cells = <0>;
557 compatible = "ti,divider-clock";
558 clocks = <&dpll_core_x2_ck>;
559 ti,max-div = <63>;
560 ti,autoidle-shift = <8>;
561 reg = <0x015c>;
562 ti,index-starts-at-one;
563 ti,invert-autoidle-bit;
564 };
565
566 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
567 #clock-cells = <0>;
568 compatible = "ti,omap4-dpll-x2-clock";
569 clocks = <&dpll_ddr_ck>;
570 };
571
572 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
573 #clock-cells = <0>;
574 compatible = "ti,divider-clock";
575 clocks = <&dpll_ddr_x2_ck>;
576 ti,max-div = <63>;
577 ti,autoidle-shift = <8>;
578 reg = <0x0228>;
579 ti,index-starts-at-one;
580 ti,invert-autoidle-bit;
581 };
582
583 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
584 #clock-cells = <0>;
585 compatible = "ti,omap4-dpll-x2-clock";
586 clocks = <&dpll_dsp_ck>;
587 };
588
589 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
590 #clock-cells = <0>;
591 compatible = "ti,divider-clock";
592 clocks = <&dpll_dsp_x2_ck>;
593 ti,max-div = <31>;
594 ti,autoidle-shift = <8>;
595 reg = <0x0248>;
596 ti,index-starts-at-one;
597 ti,invert-autoidle-bit;
598 };
599
600 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
601 #clock-cells = <0>;
602 compatible = "ti,omap4-dpll-x2-clock";
603 clocks = <&dpll_gmac_ck>;
604 };
605
606 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
607 #clock-cells = <0>;
608 compatible = "ti,divider-clock";
609 clocks = <&dpll_gmac_x2_ck>;
610 ti,max-div = <63>;
611 ti,autoidle-shift = <8>;
612 reg = <0x02c0>;
613 ti,index-starts-at-one;
614 ti,invert-autoidle-bit;
615 };
616
617 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
618 #clock-cells = <0>;
619 compatible = "ti,divider-clock";
620 clocks = <&dpll_gmac_x2_ck>;
621 ti,max-div = <63>;
622 ti,autoidle-shift = <8>;
623 reg = <0x02c4>;
624 ti,index-starts-at-one;
625 ti,invert-autoidle-bit;
626 };
627
628 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
629 #clock-cells = <0>;
630 compatible = "ti,divider-clock";
631 clocks = <&dpll_gmac_x2_ck>;
632 ti,max-div = <63>;
633 ti,autoidle-shift = <8>;
634 reg = <0x02c8>;
635 ti,index-starts-at-one;
636 ti,invert-autoidle-bit;
637 };
638
639 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
640 #clock-cells = <0>;
641 compatible = "ti,divider-clock";
642 clocks = <&dpll_gmac_x2_ck>;
643 ti,max-div = <31>;
644 ti,autoidle-shift = <8>;
645 reg = <0x02bc>;
646 ti,index-starts-at-one;
647 ti,invert-autoidle-bit;
648 };
649
650 gmii_m_clk_div: gmii_m_clk_div {
651 #clock-cells = <0>;
652 compatible = "fixed-factor-clock";
653 clocks = <&dpll_gmac_h11x2_ck>;
654 clock-mult = <1>;
655 clock-div = <2>;
656 };
657
658 hdmi_clk2_div: hdmi_clk2_div {
659 #clock-cells = <0>;
660 compatible = "fixed-factor-clock";
661 clocks = <&hdmi_clkin_ck>;
662 clock-mult = <1>;
663 clock-div = <1>;
664 };
665
666 hdmi_div_clk: hdmi_div_clk {
667 #clock-cells = <0>;
668 compatible = "fixed-factor-clock";
669 clocks = <&hdmi_clkin_ck>;
670 clock-mult = <1>;
671 clock-div = <1>;
672 };
673
674 l3_iclk_div: l3_iclk_div {
675 #clock-cells = <0>;
676 compatible = "fixed-factor-clock";
677 clocks = <&dpll_core_h12x2_ck>;
678 clock-mult = <1>;
679 clock-div = <1>;
680 };
681
682 l4_root_clk_div: l4_root_clk_div {
683 #clock-cells = <0>;
684 compatible = "fixed-factor-clock";
685 clocks = <&l3_iclk_div>;
686 clock-mult = <1>;
687 clock-div = <1>;
688 };
689
690 video1_clk2_div: video1_clk2_div {
691 #clock-cells = <0>;
692 compatible = "fixed-factor-clock";
693 clocks = <&video1_clkin_ck>;
694 clock-mult = <1>;
695 clock-div = <1>;
696 };
697
698 video1_div_clk: video1_div_clk {
699 #clock-cells = <0>;
700 compatible = "fixed-factor-clock";
701 clocks = <&video1_clkin_ck>;
702 clock-mult = <1>;
703 clock-div = <1>;
704 };
705
706 video2_clk2_div: video2_clk2_div {
707 #clock-cells = <0>;
708 compatible = "fixed-factor-clock";
709 clocks = <&video2_clkin_ck>;
710 clock-mult = <1>;
711 clock-div = <1>;
712 };
713
714 video2_div_clk: video2_div_clk {
715 #clock-cells = <0>;
716 compatible = "fixed-factor-clock";
717 clocks = <&video2_clkin_ck>;
718 clock-mult = <1>;
719 clock-div = <1>;
720 };
721
722 ipu1_gfclk_mux: ipu1_gfclk_mux {
723 #clock-cells = <0>;
724 compatible = "ti,mux-clock";
725 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
726 ti,bit-shift = <24>;
727 reg = <0x0520>;
728 };
729
730 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
731 #clock-cells = <0>;
732 compatible = "ti,mux-clock";
733 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
734 ti,bit-shift = <28>;
735 reg = <0x0550>;
736 };
737
738 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
739 #clock-cells = <0>;
740 compatible = "ti,mux-clock";
741 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
742 ti,bit-shift = <24>;
743 reg = <0x0550>;
744 };
745
746 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
747 #clock-cells = <0>;
748 compatible = "ti,mux-clock";
749 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
750 ti,bit-shift = <22>;
751 reg = <0x0550>;
752 };
753
754 timer5_gfclk_mux: timer5_gfclk_mux {
755 #clock-cells = <0>;
756 compatible = "ti,mux-clock";
757 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
758 ti,bit-shift = <24>;
759 reg = <0x0558>;
760 };
761
762 timer6_gfclk_mux: timer6_gfclk_mux {
763 #clock-cells = <0>;
764 compatible = "ti,mux-clock";
765 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
766 ti,bit-shift = <24>;
767 reg = <0x0560>;
768 };
769
770 timer7_gfclk_mux: timer7_gfclk_mux {
771 #clock-cells = <0>;
772 compatible = "ti,mux-clock";
773 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
774 ti,bit-shift = <24>;
775 reg = <0x0568>;
776 };
777
778 timer8_gfclk_mux: timer8_gfclk_mux {
779 #clock-cells = <0>;
780 compatible = "ti,mux-clock";
781 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
782 ti,bit-shift = <24>;
783 reg = <0x0570>;
784 };
785
786 uart6_gfclk_mux: uart6_gfclk_mux {
787 #clock-cells = <0>;
788 compatible = "ti,mux-clock";
789 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
790 ti,bit-shift = <24>;
791 reg = <0x0580>;
792 };
793
794 dummy_ck: dummy_ck {
795 #clock-cells = <0>;
796 compatible = "fixed-clock";
797 clock-frequency = <0>;
798 };
799};
800&prm_clocks {
801 sys_clkin1: sys_clkin1 {
802 #clock-cells = <0>;
803 compatible = "ti,mux-clock";
804 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
805 reg = <0x0110>;
806 ti,index-starts-at-one;
807 };
808
809 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
810 #clock-cells = <0>;
811 compatible = "ti,mux-clock";
812 clocks = <&sys_clkin1>, <&sys_clkin2>;
813 reg = <0x0118>;
814 };
815
816 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
817 #clock-cells = <0>;
818 compatible = "ti,mux-clock";
819 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
820 reg = <0x0114>;
821 };
822
823 abe_dpll_clk_mux: abe_dpll_clk_mux {
824 #clock-cells = <0>;
825 compatible = "ti,mux-clock";
826 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
827 reg = <0x010c>;
828 };
829
830 abe_24m_fclk: abe_24m_fclk {
831 #clock-cells = <0>;
832 compatible = "ti,divider-clock";
833 clocks = <&dpll_abe_m2x2_ck>;
834 reg = <0x011c>;
835 ti,dividers = <8>, <16>;
836 };
837
838 aess_fclk: aess_fclk {
839 #clock-cells = <0>;
840 compatible = "ti,divider-clock";
841 clocks = <&abe_clk>;
842 reg = <0x0178>;
843 ti,max-div = <2>;
844 };
845
846 abe_giclk_div: abe_giclk_div {
847 #clock-cells = <0>;
848 compatible = "ti,divider-clock";
849 clocks = <&aess_fclk>;
850 reg = <0x0174>;
851 ti,max-div = <2>;
852 };
853
854 abe_lp_clk_div: abe_lp_clk_div {
855 #clock-cells = <0>;
856 compatible = "ti,divider-clock";
857 clocks = <&dpll_abe_m2x2_ck>;
858 reg = <0x01d8>;
859 ti,dividers = <16>, <32>;
860 };
861
862 abe_sys_clk_div: abe_sys_clk_div {
863 #clock-cells = <0>;
864 compatible = "ti,divider-clock";
865 clocks = <&sys_clkin1>;
866 reg = <0x0120>;
867 ti,max-div = <2>;
868 };
869
870 adc_gfclk_mux: adc_gfclk_mux {
871 #clock-cells = <0>;
872 compatible = "ti,mux-clock";
873 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
874 reg = <0x01dc>;
875 };
876
877 sys_clk1_dclk_div: sys_clk1_dclk_div {
878 #clock-cells = <0>;
879 compatible = "ti,divider-clock";
880 clocks = <&sys_clkin1>;
881 ti,max-div = <64>;
882 reg = <0x01c8>;
883 ti,index-power-of-two;
884 };
885
886 sys_clk2_dclk_div: sys_clk2_dclk_div {
887 #clock-cells = <0>;
888 compatible = "ti,divider-clock";
889 clocks = <&sys_clkin2>;
890 ti,max-div = <64>;
891 reg = <0x01cc>;
892 ti,index-power-of-two;
893 };
894
895 per_abe_x1_dclk_div: per_abe_x1_dclk_div {
896 #clock-cells = <0>;
897 compatible = "ti,divider-clock";
898 clocks = <&dpll_abe_m2_ck>;
899 ti,max-div = <64>;
900 reg = <0x01bc>;
901 ti,index-power-of-two;
902 };
903
904 dsp_gclk_div: dsp_gclk_div {
905 #clock-cells = <0>;
906 compatible = "ti,divider-clock";
907 clocks = <&dpll_dsp_m2_ck>;
908 ti,max-div = <64>;
909 reg = <0x018c>;
910 ti,index-power-of-two;
911 };
912
913 gpu_dclk: gpu_dclk {
914 #clock-cells = <0>;
915 compatible = "ti,divider-clock";
916 clocks = <&dpll_gpu_m2_ck>;
917 ti,max-div = <64>;
918 reg = <0x01a0>;
919 ti,index-power-of-two;
920 };
921
922 emif_phy_dclk_div: emif_phy_dclk_div {
923 #clock-cells = <0>;
924 compatible = "ti,divider-clock";
925 clocks = <&dpll_ddr_m2_ck>;
926 ti,max-div = <64>;
927 reg = <0x0190>;
928 ti,index-power-of-two;
929 };
930
931 gmac_250m_dclk_div: gmac_250m_dclk_div {
932 #clock-cells = <0>;
933 compatible = "ti,divider-clock";
934 clocks = <&dpll_gmac_m2_ck>;
935 ti,max-div = <64>;
936 reg = <0x019c>;
937 ti,index-power-of-two;
938 };
939
940 l3init_480m_dclk_div: l3init_480m_dclk_div {
941 #clock-cells = <0>;
942 compatible = "ti,divider-clock";
943 clocks = <&dpll_usb_m2_ck>;
944 ti,max-div = <64>;
945 reg = <0x01ac>;
946 ti,index-power-of-two;
947 };
948
949 usb_otg_dclk_div: usb_otg_dclk_div {
950 #clock-cells = <0>;
951 compatible = "ti,divider-clock";
952 clocks = <&usb_otg_clkin_ck>;
953 ti,max-div = <64>;
954 reg = <0x0184>;
955 ti,index-power-of-two;
956 };
957
958 sata_dclk_div: sata_dclk_div {
959 #clock-cells = <0>;
960 compatible = "ti,divider-clock";
961 clocks = <&sys_clkin1>;
962 ti,max-div = <64>;
963 reg = <0x01c0>;
964 ti,index-power-of-two;
965 };
966
967 pcie2_dclk_div: pcie2_dclk_div {
968 #clock-cells = <0>;
969 compatible = "ti,divider-clock";
970 clocks = <&dpll_pcie_ref_m2_ck>;
971 ti,max-div = <64>;
972 reg = <0x01b8>;
973 ti,index-power-of-two;
974 };
975
976 pcie_dclk_div: pcie_dclk_div {
977 #clock-cells = <0>;
978 compatible = "ti,divider-clock";
979 clocks = <&apll_pcie_m2_ck>;
980 ti,max-div = <64>;
981 reg = <0x01b4>;
982 ti,index-power-of-two;
983 };
984
985 emu_dclk_div: emu_dclk_div {
986 #clock-cells = <0>;
987 compatible = "ti,divider-clock";
988 clocks = <&sys_clkin1>;
989 ti,max-div = <64>;
990 reg = <0x0194>;
991 ti,index-power-of-two;
992 };
993
994 secure_32k_dclk_div: secure_32k_dclk_div {
995 #clock-cells = <0>;
996 compatible = "ti,divider-clock";
997 clocks = <&secure_32k_clk_src_ck>;
998 ti,max-div = <64>;
999 reg = <0x01c4>;
1000 ti,index-power-of-two;
1001 };
1002
1003 clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1004 #clock-cells = <0>;
1005 compatible = "ti,mux-clock";
1006 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1007 reg = <0x0158>;
1008 };
1009
1010 clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1011 #clock-cells = <0>;
1012 compatible = "ti,mux-clock";
1013 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1014 reg = <0x015c>;
1015 };
1016
1017 clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1018 #clock-cells = <0>;
1019 compatible = "ti,mux-clock";
1020 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1021 reg = <0x0160>;
1022 };
1023
1024 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1025 #clock-cells = <0>;
1026 compatible = "fixed-factor-clock";
1027 clocks = <&sys_clkin1>;
1028 clock-mult = <1>;
1029 clock-div = <2>;
1030 };
1031
1032 eve_clk: eve_clk {
1033 #clock-cells = <0>;
1034 compatible = "ti,mux-clock";
1035 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1036 reg = <0x0180>;
1037 };
1038
1039 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1040 #clock-cells = <0>;
1041 compatible = "ti,mux-clock";
1042 clocks = <&sys_clkin1>, <&sys_clkin2>;
1043 reg = <0x01a4>;
1044 };
1045
1046 mlb_clk: mlb_clk {
1047 #clock-cells = <0>;
1048 compatible = "ti,divider-clock";
1049 clocks = <&mlb_clkin_ck>;
1050 ti,max-div = <64>;
1051 reg = <0x0134>;
1052 ti,index-power-of-two;
1053 };
1054
1055 mlbp_clk: mlbp_clk {
1056 #clock-cells = <0>;
1057 compatible = "ti,divider-clock";
1058 clocks = <&mlbp_clkin_ck>;
1059 ti,max-div = <64>;
1060 reg = <0x0130>;
1061 ti,index-power-of-two;
1062 };
1063
1064 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1065 #clock-cells = <0>;
1066 compatible = "ti,divider-clock";
1067 clocks = <&dpll_abe_m2_ck>;
1068 ti,max-div = <64>;
1069 reg = <0x0138>;
1070 ti,index-power-of-two;
1071 };
1072
1073 timer_sys_clk_div: timer_sys_clk_div {
1074 #clock-cells = <0>;
1075 compatible = "ti,divider-clock";
1076 clocks = <&sys_clkin1>;
1077 reg = <0x0144>;
1078 ti,max-div = <2>;
1079 };
1080
1081 video1_dpll_clk_mux: video1_dpll_clk_mux {
1082 #clock-cells = <0>;
1083 compatible = "ti,mux-clock";
1084 clocks = <&sys_clkin1>, <&sys_clkin2>;
1085 reg = <0x01d0>;
1086 };
1087
1088 video2_dpll_clk_mux: video2_dpll_clk_mux {
1089 #clock-cells = <0>;
1090 compatible = "ti,mux-clock";
1091 clocks = <&sys_clkin1>, <&sys_clkin2>;
1092 reg = <0x01d4>;
1093 };
1094
1095 wkupaon_iclk_mux: wkupaon_iclk_mux {
1096 #clock-cells = <0>;
1097 compatible = "ti,mux-clock";
1098 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1099 reg = <0x0108>;
1100 };
1101
1102 gpio1_dbclk: gpio1_dbclk {
1103 #clock-cells = <0>;
1104 compatible = "ti,gate-clock";
1105 clocks = <&sys_32k_ck>;
1106 ti,bit-shift = <8>;
1107 reg = <0x1838>;
1108 };
1109
1110 dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1111 #clock-cells = <0>;
1112 compatible = "ti,mux-clock";
1113 clocks = <&sys_clkin1>, <&sys_clkin2>;
1114 ti,bit-shift = <24>;
1115 reg = <0x1888>;
1116 };
1117
1118 timer1_gfclk_mux: timer1_gfclk_mux {
1119 #clock-cells = <0>;
1120 compatible = "ti,mux-clock";
1121 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1122 ti,bit-shift = <24>;
1123 reg = <0x1840>;
1124 };
1125
1126 uart10_gfclk_mux: uart10_gfclk_mux {
1127 #clock-cells = <0>;
1128 compatible = "ti,mux-clock";
1129 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1130 ti,bit-shift = <24>;
1131 reg = <0x1880>;
1132 };
1133};
1134&cm_core_clocks {
1135 dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1136 #clock-cells = <0>;
1137 compatible = "ti,omap4-dpll-clock";
1138 clocks = <&sys_clkin1>, <&sys_clkin1>;
1139 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1140 };
1141
1142 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1143 #clock-cells = <0>;
1144 compatible = "ti,divider-clock";
1145 clocks = <&dpll_pcie_ref_ck>;
1146 ti,max-div = <31>;
1147 ti,autoidle-shift = <8>;
1148 reg = <0x0210>;
1149 ti,index-starts-at-one;
1150 ti,invert-autoidle-bit;
1151 };
1152
J Keerthy7d138d32013-07-23 12:05:38 +0530[diff] [blame]1153 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1154 compatible = "ti,mux-clock";
1155 clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
1156 #clock-cells = <0>;
1157 reg = <0x021c 0x4>;
1158 ti,bit-shift = <7>;
1159 };
1160
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1161 apll_pcie_ck: apll_pcie_ck {
1162 #clock-cells = <0>;
J Keerthy7d138d32013-07-23 12:05:38 +0530[diff] [blame]1163 compatible = "ti,dra7-apll-clock";
1164 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1165 reg = <0x021c>, <0x0220>;
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1166 };
1167
J Keerthya0289f92013-07-23 12:05:40 +0530[diff] [blame]1168 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1169 compatible = "ti,divider-clock";
1170 clocks = <&apll_pcie_ck>;
1171 #clock-cells = <0>;
1172 reg = <0x021c>;
1173 ti,bit-shift = <8>;
1174 ti,max-div = <2>;
1175 };
1176
1177 optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
1178 compatible = "ti,gate-clock";
1179 clocks = <&apll_pcie_ck>;
1180 #clock-cells = <0>;
1181 reg = <0x13b0>;
1182 ti,bit-shift = <9>;
1183 };
1184
1185 optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
1186 compatible = "ti,gate-clock";
1187 clocks = <&optfclk_pciephy_div>;
1188 #clock-cells = <0>;
1189 reg = <0x13b0>;
1190 ti,bit-shift = <10>;
1191 };
1192
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1193 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1194 #clock-cells = <0>;
1195 compatible = "fixed-factor-clock";
1196 clocks = <&apll_pcie_ck>;
1197 clock-mult = <1>;
1198 clock-div = <1>;
1199 };
1200
1201 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1202 #clock-cells = <0>;
1203 compatible = "fixed-factor-clock";
1204 clocks = <&apll_pcie_ck>;
1205 clock-mult = <1>;
1206 clock-div = <1>;
1207 };
1208
1209 apll_pcie_m2_ck: apll_pcie_m2_ck {
1210 #clock-cells = <0>;
J Keerthyc3be7ac2013-07-23 12:05:39 +0530[diff] [blame]1211 compatible = "fixed-factor-clock";
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1212 clocks = <&apll_pcie_ck>;
J Keerthyc3be7ac2013-07-23 12:05:39 +0530[diff] [blame]1213 clock-mult = <1>;
1214 clock-div = <1>;
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1215 };
1216
1217 dpll_per_ck: dpll_per_ck {
1218 #clock-cells = <0>;
1219 compatible = "ti,omap4-dpll-clock";
1220 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1221 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1222 };
1223
1224 dpll_per_m2_ck: dpll_per_m2_ck {
1225 #clock-cells = <0>;
1226 compatible = "ti,divider-clock";
1227 clocks = <&dpll_per_ck>;
1228 ti,max-div = <31>;
1229 ti,autoidle-shift = <8>;
1230 reg = <0x0150>;
1231 ti,index-starts-at-one;
1232 ti,invert-autoidle-bit;
1233 };
1234
1235 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1236 #clock-cells = <0>;
1237 compatible = "fixed-factor-clock";
1238 clocks = <&dpll_per_m2_ck>;
1239 clock-mult = <1>;
1240 clock-div = <1>;
1241 };
1242
1243 dpll_usb_ck: dpll_usb_ck {
1244 #clock-cells = <0>;
1245 compatible = "ti,omap4-dpll-j-type-clock";
1246 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1247 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1248 };
1249
1250 dpll_usb_m2_ck: dpll_usb_m2_ck {
1251 #clock-cells = <0>;
1252 compatible = "ti,divider-clock";
1253 clocks = <&dpll_usb_ck>;
1254 ti,max-div = <127>;
1255 ti,autoidle-shift = <8>;
1256 reg = <0x0190>;
1257 ti,index-starts-at-one;
1258 ti,invert-autoidle-bit;
1259 };
1260
1261 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1262 #clock-cells = <0>;
1263 compatible = "ti,divider-clock";
1264 clocks = <&dpll_pcie_ref_ck>;
1265 ti,max-div = <127>;
1266 ti,autoidle-shift = <8>;
1267 reg = <0x0210>;
1268 ti,index-starts-at-one;
1269 ti,invert-autoidle-bit;
1270 };
1271
1272 dpll_per_x2_ck: dpll_per_x2_ck {
1273 #clock-cells = <0>;
1274 compatible = "ti,omap4-dpll-x2-clock";
1275 clocks = <&dpll_per_ck>;
1276 };
1277
1278 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1279 #clock-cells = <0>;
1280 compatible = "ti,divider-clock";
1281 clocks = <&dpll_per_x2_ck>;
1282 ti,max-div = <63>;
1283 ti,autoidle-shift = <8>;
1284 reg = <0x0158>;
1285 ti,index-starts-at-one;
1286 ti,invert-autoidle-bit;
1287 };
1288
1289 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1290 #clock-cells = <0>;
1291 compatible = "ti,divider-clock";
1292 clocks = <&dpll_per_x2_ck>;
1293 ti,max-div = <63>;
1294 ti,autoidle-shift = <8>;
1295 reg = <0x015c>;
1296 ti,index-starts-at-one;
1297 ti,invert-autoidle-bit;
1298 };
1299
1300 dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1301 #clock-cells = <0>;
1302 compatible = "ti,divider-clock";
1303 clocks = <&dpll_per_x2_ck>;
1304 ti,max-div = <63>;
1305 ti,autoidle-shift = <8>;
1306 reg = <0x0160>;
1307 ti,index-starts-at-one;
1308 ti,invert-autoidle-bit;
1309 };
1310
1311 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1312 #clock-cells = <0>;
1313 compatible = "ti,divider-clock";
1314 clocks = <&dpll_per_x2_ck>;
1315 ti,max-div = <63>;
1316 ti,autoidle-shift = <8>;
1317 reg = <0x0164>;
1318 ti,index-starts-at-one;
1319 ti,invert-autoidle-bit;
1320 };
1321
1322 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1323 #clock-cells = <0>;
1324 compatible = "ti,divider-clock";
1325 clocks = <&dpll_per_x2_ck>;
1326 ti,max-div = <31>;
1327 ti,autoidle-shift = <8>;
1328 reg = <0x0150>;
1329 ti,index-starts-at-one;
1330 ti,invert-autoidle-bit;
1331 };
1332
1333 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1334 #clock-cells = <0>;
1335 compatible = "fixed-factor-clock";
1336 clocks = <&dpll_usb_ck>;
1337 clock-mult = <1>;
1338 clock-div = <1>;
1339 };
1340
1341 func_128m_clk: func_128m_clk {
1342 #clock-cells = <0>;
1343 compatible = "fixed-factor-clock";
1344 clocks = <&dpll_per_h11x2_ck>;
1345 clock-mult = <1>;
1346 clock-div = <2>;
1347 };
1348
1349 func_12m_fclk: func_12m_fclk {
1350 #clock-cells = <0>;
1351 compatible = "fixed-factor-clock";
1352 clocks = <&dpll_per_m2x2_ck>;
1353 clock-mult = <1>;
1354 clock-div = <16>;
1355 };
1356
1357 func_24m_clk: func_24m_clk {
1358 #clock-cells = <0>;
1359 compatible = "fixed-factor-clock";
1360 clocks = <&dpll_per_m2_ck>;
1361 clock-mult = <1>;
1362 clock-div = <4>;
1363 };
1364
1365 func_48m_fclk: func_48m_fclk {
1366 #clock-cells = <0>;
1367 compatible = "fixed-factor-clock";
1368 clocks = <&dpll_per_m2x2_ck>;
1369 clock-mult = <1>;
1370 clock-div = <4>;
1371 };
1372
1373 func_96m_fclk: func_96m_fclk {
1374 #clock-cells = <0>;
1375 compatible = "fixed-factor-clock";
1376 clocks = <&dpll_per_m2x2_ck>;
1377 clock-mult = <1>;
1378 clock-div = <2>;
1379 };
1380
1381 l3init_60m_fclk: l3init_60m_fclk {
1382 #clock-cells = <0>;
1383 compatible = "ti,divider-clock";
1384 clocks = <&dpll_usb_m2_ck>;
1385 reg = <0x0104>;
1386 ti,dividers = <1>, <8>;
1387 };
1388
Roger Quadros032d7742014-05-05 12:54:43 +0300[diff] [blame^]1389 l3init_960m_gfclk: l3init_960m_gfclk {
1390 #clock-cells = <0>;
1391 compatible = "ti,gate-clock";
1392 clocks = <&dpll_usb_clkdcoldo>;
1393 ti,bit-shift = <8>;
1394 reg = <0x06c0>;
1395 };
1396
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1397 dss_32khz_clk: dss_32khz_clk {
1398 #clock-cells = <0>;
1399 compatible = "ti,gate-clock";
1400 clocks = <&sys_32k_ck>;
1401 ti,bit-shift = <11>;
1402 reg = <0x1120>;
1403 };
1404
1405 dss_48mhz_clk: dss_48mhz_clk {
1406 #clock-cells = <0>;
1407 compatible = "ti,gate-clock";
1408 clocks = <&func_48m_fclk>;
1409 ti,bit-shift = <9>;
1410 reg = <0x1120>;
1411 };
1412
1413 dss_dss_clk: dss_dss_clk {
1414 #clock-cells = <0>;
1415 compatible = "ti,gate-clock";
1416 clocks = <&dpll_per_h12x2_ck>;
1417 ti,bit-shift = <8>;
1418 reg = <0x1120>;
1419 };
1420
1421 dss_hdmi_clk: dss_hdmi_clk {
1422 #clock-cells = <0>;
1423 compatible = "ti,gate-clock";
1424 clocks = <&hdmi_dpll_clk_mux>;
1425 ti,bit-shift = <10>;
1426 reg = <0x1120>;
1427 };
1428
1429 dss_video1_clk: dss_video1_clk {
1430 #clock-cells = <0>;
1431 compatible = "ti,gate-clock";
1432 clocks = <&video1_dpll_clk_mux>;
1433 ti,bit-shift = <12>;
1434 reg = <0x1120>;
1435 };
1436
1437 dss_video2_clk: dss_video2_clk {
1438 #clock-cells = <0>;
1439 compatible = "ti,gate-clock";
1440 clocks = <&video2_dpll_clk_mux>;
1441 ti,bit-shift = <13>;
1442 reg = <0x1120>;
1443 };
1444
1445 gpio2_dbclk: gpio2_dbclk {
1446 #clock-cells = <0>;
1447 compatible = "ti,gate-clock";
1448 clocks = <&sys_32k_ck>;
1449 ti,bit-shift = <8>;
1450 reg = <0x1760>;
1451 };
1452
1453 gpio3_dbclk: gpio3_dbclk {
1454 #clock-cells = <0>;
1455 compatible = "ti,gate-clock";
1456 clocks = <&sys_32k_ck>;
1457 ti,bit-shift = <8>;
1458 reg = <0x1768>;
1459 };
1460
1461 gpio4_dbclk: gpio4_dbclk {
1462 #clock-cells = <0>;
1463 compatible = "ti,gate-clock";
1464 clocks = <&sys_32k_ck>;
1465 ti,bit-shift = <8>;
1466 reg = <0x1770>;
1467 };
1468
1469 gpio5_dbclk: gpio5_dbclk {
1470 #clock-cells = <0>;
1471 compatible = "ti,gate-clock";
1472 clocks = <&sys_32k_ck>;
1473 ti,bit-shift = <8>;
1474 reg = <0x1778>;
1475 };
1476
1477 gpio6_dbclk: gpio6_dbclk {
1478 #clock-cells = <0>;
1479 compatible = "ti,gate-clock";
1480 clocks = <&sys_32k_ck>;
1481 ti,bit-shift = <8>;
1482 reg = <0x1780>;
1483 };
1484
1485 gpio7_dbclk: gpio7_dbclk {
1486 #clock-cells = <0>;
1487 compatible = "ti,gate-clock";
1488 clocks = <&sys_32k_ck>;
1489 ti,bit-shift = <8>;
1490 reg = <0x1810>;
1491 };
1492
1493 gpio8_dbclk: gpio8_dbclk {
1494 #clock-cells = <0>;
1495 compatible = "ti,gate-clock";
1496 clocks = <&sys_32k_ck>;
1497 ti,bit-shift = <8>;
1498 reg = <0x1818>;
1499 };
1500
1501 mmc1_clk32k: mmc1_clk32k {
1502 #clock-cells = <0>;
1503 compatible = "ti,gate-clock";
1504 clocks = <&sys_32k_ck>;
1505 ti,bit-shift = <8>;
1506 reg = <0x1328>;
1507 };
1508
1509 mmc2_clk32k: mmc2_clk32k {
1510 #clock-cells = <0>;
1511 compatible = "ti,gate-clock";
1512 clocks = <&sys_32k_ck>;
1513 ti,bit-shift = <8>;
1514 reg = <0x1330>;
1515 };
1516
1517 mmc3_clk32k: mmc3_clk32k {
1518 #clock-cells = <0>;
1519 compatible = "ti,gate-clock";
1520 clocks = <&sys_32k_ck>;
1521 ti,bit-shift = <8>;
1522 reg = <0x1820>;
1523 };
1524
1525 mmc4_clk32k: mmc4_clk32k {
1526 #clock-cells = <0>;
1527 compatible = "ti,gate-clock";
1528 clocks = <&sys_32k_ck>;
1529 ti,bit-shift = <8>;
1530 reg = <0x1828>;
1531 };
1532
1533 sata_ref_clk: sata_ref_clk {
1534 #clock-cells = <0>;
1535 compatible = "ti,gate-clock";
1536 clocks = <&sys_clkin1>;
1537 ti,bit-shift = <8>;
1538 reg = <0x1388>;
1539 };
1540
1541 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1542 #clock-cells = <0>;
1543 compatible = "ti,gate-clock";
Roger Quadros032d7742014-05-05 12:54:43 +0300[diff] [blame^]1544 clocks = <&l3init_960m_gfclk>;
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1545 ti,bit-shift = <8>;
1546 reg = <0x13f0>;
1547 };
1548
1549 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1550 #clock-cells = <0>;
1551 compatible = "ti,gate-clock";
Roger Quadros032d7742014-05-05 12:54:43 +0300[diff] [blame^]1552 clocks = <&l3init_960m_gfclk>;
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1553 ti,bit-shift = <8>;
1554 reg = <0x1340>;
1555 };
1556
1557 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1558 #clock-cells = <0>;
1559 compatible = "ti,gate-clock";
1560 clocks = <&sys_32k_ck>;
1561 ti,bit-shift = <8>;
1562 reg = <0x0640>;
1563 };
1564
1565 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1566 #clock-cells = <0>;
1567 compatible = "ti,gate-clock";
1568 clocks = <&sys_32k_ck>;
1569 ti,bit-shift = <8>;
1570 reg = <0x0688>;
1571 };
1572
1573 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1574 #clock-cells = <0>;
1575 compatible = "ti,gate-clock";
1576 clocks = <&sys_32k_ck>;
1577 ti,bit-shift = <8>;
1578 reg = <0x0698>;
1579 };
1580
1581 atl_dpll_clk_mux: atl_dpll_clk_mux {
1582 #clock-cells = <0>;
1583 compatible = "ti,mux-clock";
1584 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1585 ti,bit-shift = <24>;
1586 reg = <0x0c00>;
1587 };
1588
1589 atl_gfclk_mux: atl_gfclk_mux {
1590 #clock-cells = <0>;
1591 compatible = "ti,mux-clock";
1592 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1593 ti,bit-shift = <26>;
1594 reg = <0x0c00>;
1595 };
1596
1597 gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1598 #clock-cells = <0>;
1599 compatible = "ti,divider-clock";
1600 clocks = <&dpll_gmac_m2_ck>;
1601 ti,bit-shift = <24>;
1602 reg = <0x13d0>;
1603 ti,dividers = <2>;
1604 };
1605
1606 gmac_rft_clk_mux: gmac_rft_clk_mux {
1607 #clock-cells = <0>;
1608 compatible = "ti,mux-clock";
1609 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1610 ti,bit-shift = <25>;
1611 reg = <0x13d0>;
1612 };
1613
1614 gpu_core_gclk_mux: gpu_core_gclk_mux {
1615 #clock-cells = <0>;
1616 compatible = "ti,mux-clock";
1617 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1618 ti,bit-shift = <24>;
1619 reg = <0x1220>;
1620 };
1621
1622 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1623 #clock-cells = <0>;
1624 compatible = "ti,mux-clock";
1625 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1626 ti,bit-shift = <26>;
1627 reg = <0x1220>;
1628 };
1629
1630 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1631 #clock-cells = <0>;
1632 compatible = "ti,divider-clock";
1633 clocks = <&wkupaon_iclk_mux>;
1634 ti,bit-shift = <24>;
1635 reg = <0x0e50>;
1636 ti,dividers = <8>, <16>, <32>;
1637 };
1638
1639 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1640 #clock-cells = <0>;
1641 compatible = "ti,mux-clock";
1642 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1643 ti,bit-shift = <28>;
1644 reg = <0x1860>;
1645 };
1646
1647 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1648 #clock-cells = <0>;
1649 compatible = "ti,mux-clock";
1650 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
Peter Ujfalusi8c0b4fd2014-04-02 16:46:25 +0300[diff] [blame]1651 ti,bit-shift = <24>;
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]1652 reg = <0x1860>;
1653 };
1654
1655 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1656 #clock-cells = <0>;
1657 compatible = "ti,mux-clock";
1658 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1659 ti,bit-shift = <22>;
1660 reg = <0x1860>;
1661 };
1662
1663 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1664 #clock-cells = <0>;
1665 compatible = "ti,mux-clock";
1666 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1667 ti,bit-shift = <24>;
1668 reg = <0x1868>;
1669 };
1670
1671 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1672 #clock-cells = <0>;
1673 compatible = "ti,mux-clock";
1674 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1675 ti,bit-shift = <22>;
1676 reg = <0x1868>;
1677 };
1678
1679 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1680 #clock-cells = <0>;
1681 compatible = "ti,mux-clock";
1682 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1683 ti,bit-shift = <24>;
1684 reg = <0x1898>;
1685 };
1686
1687 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1688 #clock-cells = <0>;
1689 compatible = "ti,mux-clock";
1690 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1691 ti,bit-shift = <22>;
1692 reg = <0x1898>;
1693 };
1694
1695 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1696 #clock-cells = <0>;
1697 compatible = "ti,mux-clock";
1698 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1699 ti,bit-shift = <24>;
1700 reg = <0x1878>;
1701 };
1702
1703 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1704 #clock-cells = <0>;
1705 compatible = "ti,mux-clock";
1706 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1707 ti,bit-shift = <22>;
1708 reg = <0x1878>;
1709 };
1710
1711 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1712 #clock-cells = <0>;
1713 compatible = "ti,mux-clock";
1714 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1715 ti,bit-shift = <24>;
1716 reg = <0x1904>;
1717 };
1718
1719 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1720 #clock-cells = <0>;
1721 compatible = "ti,mux-clock";
1722 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1723 ti,bit-shift = <22>;
1724 reg = <0x1904>;
1725 };
1726
1727 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1728 #clock-cells = <0>;
1729 compatible = "ti,mux-clock";
1730 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1731 ti,bit-shift = <24>;
1732 reg = <0x1908>;
1733 };
1734
1735 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1736 #clock-cells = <0>;
1737 compatible = "ti,mux-clock";
1738 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1739 ti,bit-shift = <22>;
1740 reg = <0x1908>;
1741 };
1742
1743 mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1744 #clock-cells = <0>;
1745 compatible = "ti,mux-clock";
1746 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1747 ti,bit-shift = <22>;
1748 reg = <0x1890>;
1749 };
1750
1751 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1752 #clock-cells = <0>;
1753 compatible = "ti,mux-clock";
1754 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1755 ti,bit-shift = <24>;
1756 reg = <0x1890>;
1757 };
1758
1759 mmc1_fclk_mux: mmc1_fclk_mux {
1760 #clock-cells = <0>;
1761 compatible = "ti,mux-clock";
1762 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1763 ti,bit-shift = <24>;
1764 reg = <0x1328>;
1765 };
1766
1767 mmc1_fclk_div: mmc1_fclk_div {
1768 #clock-cells = <0>;
1769 compatible = "ti,divider-clock";
1770 clocks = <&mmc1_fclk_mux>;
1771 ti,bit-shift = <25>;
1772 ti,max-div = <4>;
1773 reg = <0x1328>;
1774 ti,index-power-of-two;
1775 };
1776
1777 mmc2_fclk_mux: mmc2_fclk_mux {
1778 #clock-cells = <0>;
1779 compatible = "ti,mux-clock";
1780 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1781 ti,bit-shift = <24>;
1782 reg = <0x1330>;
1783 };
1784
1785 mmc2_fclk_div: mmc2_fclk_div {
1786 #clock-cells = <0>;
1787 compatible = "ti,divider-clock";
1788 clocks = <&mmc2_fclk_mux>;
1789 ti,bit-shift = <25>;
1790 ti,max-div = <4>;
1791 reg = <0x1330>;
1792 ti,index-power-of-two;
1793 };
1794
1795 mmc3_gfclk_mux: mmc3_gfclk_mux {
1796 #clock-cells = <0>;
1797 compatible = "ti,mux-clock";
1798 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1799 ti,bit-shift = <24>;
1800 reg = <0x1820>;
1801 };
1802
1803 mmc3_gfclk_div: mmc3_gfclk_div {
1804 #clock-cells = <0>;
1805 compatible = "ti,divider-clock";
1806 clocks = <&mmc3_gfclk_mux>;
1807 ti,bit-shift = <25>;
1808 ti,max-div = <4>;
1809 reg = <0x1820>;
1810 ti,index-power-of-two;
1811 };
1812
1813 mmc4_gfclk_mux: mmc4_gfclk_mux {
1814 #clock-cells = <0>;
1815 compatible = "ti,mux-clock";
1816 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1817 ti,bit-shift = <24>;
1818 reg = <0x1828>;
1819 };
1820
1821 mmc4_gfclk_div: mmc4_gfclk_div {
1822 #clock-cells = <0>;
1823 compatible = "ti,divider-clock";
1824 clocks = <&mmc4_gfclk_mux>;
1825 ti,bit-shift = <25>;
1826 ti,max-div = <4>;
1827 reg = <0x1828>;
1828 ti,index-power-of-two;
1829 };
1830
1831 qspi_gfclk_mux: qspi_gfclk_mux {
1832 #clock-cells = <0>;
1833 compatible = "ti,mux-clock";
1834 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1835 ti,bit-shift = <24>;
1836 reg = <0x1838>;
1837 };
1838
1839 qspi_gfclk_div: qspi_gfclk_div {
1840 #clock-cells = <0>;
1841 compatible = "ti,divider-clock";
1842 clocks = <&qspi_gfclk_mux>;
1843 ti,bit-shift = <25>;
1844 ti,max-div = <4>;
1845 reg = <0x1838>;
1846 ti,index-power-of-two;
1847 };
1848
1849 timer10_gfclk_mux: timer10_gfclk_mux {
1850 #clock-cells = <0>;
1851 compatible = "ti,mux-clock";
1852 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1853 ti,bit-shift = <24>;
1854 reg = <0x1728>;
1855 };
1856
1857 timer11_gfclk_mux: timer11_gfclk_mux {
1858 #clock-cells = <0>;
1859 compatible = "ti,mux-clock";
1860 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1861 ti,bit-shift = <24>;
1862 reg = <0x1730>;
1863 };
1864
1865 timer13_gfclk_mux: timer13_gfclk_mux {
1866 #clock-cells = <0>;
1867 compatible = "ti,mux-clock";
1868 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1869 ti,bit-shift = <24>;
1870 reg = <0x17c8>;
1871 };
1872
1873 timer14_gfclk_mux: timer14_gfclk_mux {
1874 #clock-cells = <0>;
1875 compatible = "ti,mux-clock";
1876 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1877 ti,bit-shift = <24>;
1878 reg = <0x17d0>;
1879 };
1880
1881 timer15_gfclk_mux: timer15_gfclk_mux {
1882 #clock-cells = <0>;
1883 compatible = "ti,mux-clock";
1884 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1885 ti,bit-shift = <24>;
1886 reg = <0x17d8>;
1887 };
1888
1889 timer16_gfclk_mux: timer16_gfclk_mux {
1890 #clock-cells = <0>;
1891 compatible = "ti,mux-clock";
1892 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1893 ti,bit-shift = <24>;
1894 reg = <0x1830>;
1895 };
1896
1897 timer2_gfclk_mux: timer2_gfclk_mux {
1898 #clock-cells = <0>;
1899 compatible = "ti,mux-clock";
1900 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1901 ti,bit-shift = <24>;
1902 reg = <0x1738>;
1903 };
1904
1905 timer3_gfclk_mux: timer3_gfclk_mux {
1906 #clock-cells = <0>;
1907 compatible = "ti,mux-clock";
1908 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1909 ti,bit-shift = <24>;
1910 reg = <0x1740>;
1911 };
1912
1913 timer4_gfclk_mux: timer4_gfclk_mux {
1914 #clock-cells = <0>;
1915 compatible = "ti,mux-clock";
1916 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1917 ti,bit-shift = <24>;
1918 reg = <0x1748>;
1919 };
1920
1921 timer9_gfclk_mux: timer9_gfclk_mux {
1922 #clock-cells = <0>;
1923 compatible = "ti,mux-clock";
1924 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1925 ti,bit-shift = <24>;
1926 reg = <0x1750>;
1927 };
1928
1929 uart1_gfclk_mux: uart1_gfclk_mux {
1930 #clock-cells = <0>;
1931 compatible = "ti,mux-clock";
1932 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1933 ti,bit-shift = <24>;
1934 reg = <0x1840>;
1935 };
1936
1937 uart2_gfclk_mux: uart2_gfclk_mux {
1938 #clock-cells = <0>;
1939 compatible = "ti,mux-clock";
1940 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1941 ti,bit-shift = <24>;
1942 reg = <0x1848>;
1943 };
1944
1945 uart3_gfclk_mux: uart3_gfclk_mux {
1946 #clock-cells = <0>;
1947 compatible = "ti,mux-clock";
1948 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1949 ti,bit-shift = <24>;
1950 reg = <0x1850>;
1951 };
1952
1953 uart4_gfclk_mux: uart4_gfclk_mux {
1954 #clock-cells = <0>;
1955 compatible = "ti,mux-clock";
1956 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1957 ti,bit-shift = <24>;
1958 reg = <0x1858>;
1959 };
1960
1961 uart5_gfclk_mux: uart5_gfclk_mux {
1962 #clock-cells = <0>;
1963 compatible = "ti,mux-clock";
1964 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1965 ti,bit-shift = <24>;
1966 reg = <0x1870>;
1967 };
1968
1969 uart7_gfclk_mux: uart7_gfclk_mux {
1970 #clock-cells = <0>;
1971 compatible = "ti,mux-clock";
1972 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1973 ti,bit-shift = <24>;
1974 reg = <0x18d0>;
1975 };
1976
1977 uart8_gfclk_mux: uart8_gfclk_mux {
1978 #clock-cells = <0>;
1979 compatible = "ti,mux-clock";
1980 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1981 ti,bit-shift = <24>;
1982 reg = <0x18e0>;
1983 };
1984
1985 uart9_gfclk_mux: uart9_gfclk_mux {
1986 #clock-cells = <0>;
1987 compatible = "ti,mux-clock";
1988 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1989 ti,bit-shift = <24>;
1990 reg = <0x18e8>;
1991 };
1992
1993 vip1_gclk_mux: vip1_gclk_mux {
1994 #clock-cells = <0>;
1995 compatible = "ti,mux-clock";
1996 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1997 ti,bit-shift = <24>;
1998 reg = <0x1020>;
1999 };
2000
2001 vip2_gclk_mux: vip2_gclk_mux {
2002 #clock-cells = <0>;
2003 compatible = "ti,mux-clock";
2004 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2005 ti,bit-shift = <24>;
2006 reg = <0x1028>;
2007 };
2008
2009 vip3_gclk_mux: vip3_gclk_mux {
2010 #clock-cells = <0>;
2011 compatible = "ti,mux-clock";
2012 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2013 ti,bit-shift = <24>;
2014 reg = <0x1030>;
2015 };
2016};
2017
2018&cm_core_clockdomains {
2019 coreaon_clkdm: coreaon_clkdm {
2020 compatible = "ti,clockdomain";
2021 clocks = <&dpll_usb_ck>;
2022 };
2023};