Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "radeon_drm.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 33 | #include "radeon_reg.h" |
| 34 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 35 | #include "radeon_asic.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 36 | #include "r100d.h" |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 37 | #include "rs100d.h" |
| 38 | #include "rv200d.h" |
| 39 | #include "rv250d.h" |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 40 | #include "atom.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 41 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 42 | #include <linux/firmware.h> |
| 43 | #include <linux/platform_device.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 44 | #include <linux/module.h> |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 45 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 46 | #include "r100_reg_safe.h" |
| 47 | #include "rn50_reg_safe.h" |
| 48 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 49 | /* Firmware Names */ |
| 50 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
| 51 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
| 52 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
| 53 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
| 54 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
| 55 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
| 56 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
| 57 | |
| 58 | MODULE_FIRMWARE(FIRMWARE_R100); |
| 59 | MODULE_FIRMWARE(FIRMWARE_R200); |
| 60 | MODULE_FIRMWARE(FIRMWARE_R300); |
| 61 | MODULE_FIRMWARE(FIRMWARE_R420); |
| 62 | MODULE_FIRMWARE(FIRMWARE_RS690); |
| 63 | MODULE_FIRMWARE(FIRMWARE_RS600); |
| 64 | MODULE_FIRMWARE(FIRMWARE_R520); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 65 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 66 | #include "r100_track.h" |
| 67 | |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 68 | void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) |
| 69 | { |
| 70 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; |
| 71 | int i; |
| 72 | |
| 73 | if (radeon_crtc->crtc_id == 0) { |
| 74 | if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { |
| 75 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 76 | if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)) |
| 77 | break; |
| 78 | udelay(1); |
| 79 | } |
| 80 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 81 | if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) |
| 82 | break; |
| 83 | udelay(1); |
| 84 | } |
| 85 | } |
| 86 | } else { |
| 87 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { |
| 88 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 89 | if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) |
| 90 | break; |
| 91 | udelay(1); |
| 92 | } |
| 93 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 94 | if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) |
| 95 | break; |
| 96 | udelay(1); |
| 97 | } |
| 98 | } |
| 99 | } |
| 100 | } |
| 101 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 102 | /* This files gather functions specifics to: |
| 103 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 106 | int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
| 107 | struct radeon_cs_packet *pkt, |
| 108 | unsigned idx, |
| 109 | unsigned reg) |
| 110 | { |
| 111 | int r; |
| 112 | u32 tile_flags = 0; |
| 113 | u32 tmp; |
| 114 | struct radeon_cs_reloc *reloc; |
| 115 | u32 value; |
| 116 | |
| 117 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 118 | if (r) { |
| 119 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 120 | idx, reg); |
| 121 | r100_cs_dump_packet(p, pkt); |
| 122 | return r; |
| 123 | } |
Alex Deucher | c9068eb | 2012-02-02 10:11:11 -0500 | [diff] [blame] | 124 | |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 125 | value = radeon_get_ib_value(p, idx); |
| 126 | tmp = value & 0x003fffff; |
| 127 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
| 128 | |
Alex Deucher | c9068eb | 2012-02-02 10:11:11 -0500 | [diff] [blame] | 129 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| 130 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| 131 | tile_flags |= RADEON_DST_TILE_MACRO; |
| 132 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { |
| 133 | if (reg == RADEON_SRC_PITCH_OFFSET) { |
| 134 | DRM_ERROR("Cannot src blit from microtiled surface\n"); |
| 135 | r100_cs_dump_packet(p, pkt); |
| 136 | return -EINVAL; |
| 137 | } |
| 138 | tile_flags |= RADEON_DST_TILE_MICRO; |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 139 | } |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 140 | |
Alex Deucher | c9068eb | 2012-02-02 10:11:11 -0500 | [diff] [blame] | 141 | tmp |= tile_flags; |
| 142 | p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; |
| 143 | } else |
| 144 | p->ib->ptr[idx] = (value & 0xffc00000) | tmp; |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, |
| 149 | struct radeon_cs_packet *pkt, |
| 150 | int idx) |
| 151 | { |
| 152 | unsigned c, i; |
| 153 | struct radeon_cs_reloc *reloc; |
| 154 | struct r100_cs_track *track; |
| 155 | int r = 0; |
| 156 | volatile uint32_t *ib; |
| 157 | u32 idx_value; |
| 158 | |
| 159 | ib = p->ib->ptr; |
| 160 | track = (struct r100_cs_track *)p->track; |
| 161 | c = radeon_get_ib_value(p, idx++) & 0x1F; |
| 162 | if (c > 16) { |
| 163 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", |
| 164 | pkt->opcode); |
| 165 | r100_cs_dump_packet(p, pkt); |
| 166 | return -EINVAL; |
| 167 | } |
| 168 | track->num_arrays = c; |
| 169 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
| 170 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 171 | if (r) { |
| 172 | DRM_ERROR("No reloc for packet3 %d\n", |
| 173 | pkt->opcode); |
| 174 | r100_cs_dump_packet(p, pkt); |
| 175 | return r; |
| 176 | } |
| 177 | idx_value = radeon_get_ib_value(p, idx); |
| 178 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
| 179 | |
| 180 | track->arrays[i + 0].esize = idx_value >> 8; |
| 181 | track->arrays[i + 0].robj = reloc->robj; |
| 182 | track->arrays[i + 0].esize &= 0x7F; |
| 183 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 184 | if (r) { |
| 185 | DRM_ERROR("No reloc for packet3 %d\n", |
| 186 | pkt->opcode); |
| 187 | r100_cs_dump_packet(p, pkt); |
| 188 | return r; |
| 189 | } |
| 190 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); |
| 191 | track->arrays[i + 1].robj = reloc->robj; |
| 192 | track->arrays[i + 1].esize = idx_value >> 24; |
| 193 | track->arrays[i + 1].esize &= 0x7F; |
| 194 | } |
| 195 | if (c & 1) { |
| 196 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 197 | if (r) { |
| 198 | DRM_ERROR("No reloc for packet3 %d\n", |
| 199 | pkt->opcode); |
| 200 | r100_cs_dump_packet(p, pkt); |
| 201 | return r; |
| 202 | } |
| 203 | idx_value = radeon_get_ib_value(p, idx); |
| 204 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
| 205 | track->arrays[i + 0].robj = reloc->robj; |
| 206 | track->arrays[i + 0].esize = idx_value >> 8; |
| 207 | track->arrays[i + 0].esize &= 0x7F; |
| 208 | } |
| 209 | return r; |
| 210 | } |
| 211 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 212 | void r100_pre_page_flip(struct radeon_device *rdev, int crtc) |
| 213 | { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 214 | /* enable the pflip int */ |
| 215 | radeon_irq_kms_pflip_irq_get(rdev, crtc); |
| 216 | } |
| 217 | |
| 218 | void r100_post_page_flip(struct radeon_device *rdev, int crtc) |
| 219 | { |
| 220 | /* disable the pflip int */ |
| 221 | radeon_irq_kms_pflip_irq_put(rdev, crtc); |
| 222 | } |
| 223 | |
| 224 | u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
| 225 | { |
| 226 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
| 227 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; |
Alex Deucher | f649647 | 2011-11-28 14:49:26 -0500 | [diff] [blame] | 228 | int i; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 229 | |
| 230 | /* Lock the graphics update lock */ |
| 231 | /* update the scanout addresses */ |
| 232 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
| 233 | |
Alex Deucher | acb3250 | 2010-11-23 00:41:00 -0500 | [diff] [blame] | 234 | /* Wait for update_pending to go high. */ |
Alex Deucher | f649647 | 2011-11-28 14:49:26 -0500 | [diff] [blame] | 235 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 236 | if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) |
| 237 | break; |
| 238 | udelay(1); |
| 239 | } |
Alex Deucher | acb3250 | 2010-11-23 00:41:00 -0500 | [diff] [blame] | 240 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 241 | |
| 242 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
| 243 | tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; |
| 244 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
| 245 | |
| 246 | /* Return current update_pending status: */ |
| 247 | return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; |
| 248 | } |
| 249 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 250 | void r100_pm_get_dynpm_state(struct radeon_device *rdev) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 251 | { |
| 252 | int i; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 253 | rdev->pm.dynpm_can_upclock = true; |
| 254 | rdev->pm.dynpm_can_downclock = true; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 255 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 256 | switch (rdev->pm.dynpm_planned_action) { |
| 257 | case DYNPM_ACTION_MINIMUM: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 258 | rdev->pm.requested_power_state_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 259 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 260 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 261 | case DYNPM_ACTION_DOWNCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 262 | if (rdev->pm.current_power_state_index == 0) { |
| 263 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 264 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 265 | } else { |
| 266 | if (rdev->pm.active_crtc_count > 1) { |
| 267 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 268 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 269 | continue; |
| 270 | else if (i >= rdev->pm.current_power_state_index) { |
| 271 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
| 272 | break; |
| 273 | } else { |
| 274 | rdev->pm.requested_power_state_index = i; |
| 275 | break; |
| 276 | } |
| 277 | } |
| 278 | } else |
| 279 | rdev->pm.requested_power_state_index = |
| 280 | rdev->pm.current_power_state_index - 1; |
| 281 | } |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 282 | /* don't use the power state if crtcs are active and no display flag is set */ |
| 283 | if ((rdev->pm.active_crtc_count > 0) && |
| 284 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & |
| 285 | RADEON_PM_MODE_NO_DISPLAY)) { |
| 286 | rdev->pm.requested_power_state_index++; |
| 287 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 288 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 289 | case DYNPM_ACTION_UPCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 290 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
| 291 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 292 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 293 | } else { |
| 294 | if (rdev->pm.active_crtc_count > 1) { |
| 295 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 296 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 297 | continue; |
| 298 | else if (i <= rdev->pm.current_power_state_index) { |
| 299 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
| 300 | break; |
| 301 | } else { |
| 302 | rdev->pm.requested_power_state_index = i; |
| 303 | break; |
| 304 | } |
| 305 | } |
| 306 | } else |
| 307 | rdev->pm.requested_power_state_index = |
| 308 | rdev->pm.current_power_state_index + 1; |
| 309 | } |
| 310 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 311 | case DYNPM_ACTION_DEFAULT: |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 312 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 313 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 314 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 315 | case DYNPM_ACTION_NONE: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 316 | default: |
| 317 | DRM_ERROR("Requested mode for not defined action\n"); |
| 318 | return; |
| 319 | } |
| 320 | /* only one clock mode per power state */ |
| 321 | rdev->pm.requested_clock_mode_index = 0; |
| 322 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 323 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
Alex Deucher | ce8a3eb | 2010-05-07 16:58:27 -0400 | [diff] [blame] | 324 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 325 | clock_info[rdev->pm.requested_clock_mode_index].sclk, |
| 326 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 327 | clock_info[rdev->pm.requested_clock_mode_index].mclk, |
| 328 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 329 | pcie_lanes); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 330 | } |
| 331 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 332 | void r100_pm_init_profile(struct radeon_device *rdev) |
Alex Deucher | bae6b562 | 2010-04-22 13:38:05 -0400 | [diff] [blame] | 333 | { |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 334 | /* default */ |
| 335 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 336 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 337 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 338 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 339 | /* low sh */ |
| 340 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
| 341 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
| 342 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 343 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 344 | /* mid sh */ |
| 345 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
| 346 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; |
| 347 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 348 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 349 | /* high sh */ |
| 350 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
| 351 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 352 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 353 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 354 | /* low mh */ |
| 355 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
| 356 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 357 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 358 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 359 | /* mid mh */ |
| 360 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
| 361 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 362 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 363 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 364 | /* high mh */ |
| 365 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
| 366 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 367 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 368 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | bae6b562 | 2010-04-22 13:38:05 -0400 | [diff] [blame] | 369 | } |
| 370 | |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 371 | void r100_pm_misc(struct radeon_device *rdev) |
| 372 | { |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 373 | int requested_index = rdev->pm.requested_power_state_index; |
| 374 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; |
| 375 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; |
| 376 | u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; |
| 377 | |
| 378 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { |
| 379 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
| 380 | tmp = RREG32(voltage->gpio.reg); |
| 381 | if (voltage->active_high) |
| 382 | tmp |= voltage->gpio.mask; |
| 383 | else |
| 384 | tmp &= ~(voltage->gpio.mask); |
| 385 | WREG32(voltage->gpio.reg, tmp); |
| 386 | if (voltage->delay) |
| 387 | udelay(voltage->delay); |
| 388 | } else { |
| 389 | tmp = RREG32(voltage->gpio.reg); |
| 390 | if (voltage->active_high) |
| 391 | tmp &= ~voltage->gpio.mask; |
| 392 | else |
| 393 | tmp |= voltage->gpio.mask; |
| 394 | WREG32(voltage->gpio.reg, tmp); |
| 395 | if (voltage->delay) |
| 396 | udelay(voltage->delay); |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | sclk_cntl = RREG32_PLL(SCLK_CNTL); |
| 401 | sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); |
| 402 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); |
| 403 | sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); |
| 404 | sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); |
| 405 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { |
| 406 | sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; |
| 407 | if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) |
| 408 | sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; |
| 409 | else |
| 410 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; |
| 411 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) |
| 412 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); |
| 413 | else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) |
| 414 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); |
| 415 | } else |
| 416 | sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; |
| 417 | |
| 418 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { |
| 419 | sclk_more_cntl |= IO_CG_VOLTAGE_DROP; |
| 420 | if (voltage->delay) { |
| 421 | sclk_more_cntl |= VOLTAGE_DROP_SYNC; |
| 422 | switch (voltage->delay) { |
| 423 | case 33: |
| 424 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); |
| 425 | break; |
| 426 | case 66: |
| 427 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); |
| 428 | break; |
| 429 | case 99: |
| 430 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); |
| 431 | break; |
| 432 | case 132: |
| 433 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); |
| 434 | break; |
| 435 | } |
| 436 | } else |
| 437 | sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; |
| 438 | } else |
| 439 | sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; |
| 440 | |
| 441 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) |
| 442 | sclk_cntl &= ~FORCE_HDP; |
| 443 | else |
| 444 | sclk_cntl |= FORCE_HDP; |
| 445 | |
| 446 | WREG32_PLL(SCLK_CNTL, sclk_cntl); |
| 447 | WREG32_PLL(SCLK_CNTL2, sclk_cntl2); |
| 448 | WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); |
| 449 | |
| 450 | /* set pcie lanes */ |
| 451 | if ((rdev->flags & RADEON_IS_PCIE) && |
| 452 | !(rdev->flags & RADEON_IS_IGP) && |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 453 | rdev->asic->pm.set_pcie_lanes && |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 454 | (ps->pcie_lanes != |
| 455 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
| 456 | radeon_set_pcie_lanes(rdev, |
| 457 | ps->pcie_lanes); |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 458 | DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 459 | } |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | void r100_pm_prepare(struct radeon_device *rdev) |
| 463 | { |
| 464 | struct drm_device *ddev = rdev->ddev; |
| 465 | struct drm_crtc *crtc; |
| 466 | struct radeon_crtc *radeon_crtc; |
| 467 | u32 tmp; |
| 468 | |
| 469 | /* disable any active CRTCs */ |
| 470 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
| 471 | radeon_crtc = to_radeon_crtc(crtc); |
| 472 | if (radeon_crtc->enabled) { |
| 473 | if (radeon_crtc->crtc_id) { |
| 474 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 475 | tmp |= RADEON_CRTC2_DISP_REQ_EN_B; |
| 476 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
| 477 | } else { |
| 478 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); |
| 479 | tmp |= RADEON_CRTC_DISP_REQ_EN_B; |
| 480 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); |
| 481 | } |
| 482 | } |
| 483 | } |
| 484 | } |
| 485 | |
| 486 | void r100_pm_finish(struct radeon_device *rdev) |
| 487 | { |
| 488 | struct drm_device *ddev = rdev->ddev; |
| 489 | struct drm_crtc *crtc; |
| 490 | struct radeon_crtc *radeon_crtc; |
| 491 | u32 tmp; |
| 492 | |
| 493 | /* enable any active CRTCs */ |
| 494 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
| 495 | radeon_crtc = to_radeon_crtc(crtc); |
| 496 | if (radeon_crtc->enabled) { |
| 497 | if (radeon_crtc->crtc_id) { |
| 498 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 499 | tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; |
| 500 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
| 501 | } else { |
| 502 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); |
| 503 | tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; |
| 504 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); |
| 505 | } |
| 506 | } |
| 507 | } |
| 508 | } |
| 509 | |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 510 | bool r100_gui_idle(struct radeon_device *rdev) |
| 511 | { |
| 512 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) |
| 513 | return false; |
| 514 | else |
| 515 | return true; |
| 516 | } |
| 517 | |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 518 | /* hpd for digital panel detect/disconnect */ |
| 519 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
| 520 | { |
| 521 | bool connected = false; |
| 522 | |
| 523 | switch (hpd) { |
| 524 | case RADEON_HPD_1: |
| 525 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
| 526 | connected = true; |
| 527 | break; |
| 528 | case RADEON_HPD_2: |
| 529 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
| 530 | connected = true; |
| 531 | break; |
| 532 | default: |
| 533 | break; |
| 534 | } |
| 535 | return connected; |
| 536 | } |
| 537 | |
| 538 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
| 539 | enum radeon_hpd_id hpd) |
| 540 | { |
| 541 | u32 tmp; |
| 542 | bool connected = r100_hpd_sense(rdev, hpd); |
| 543 | |
| 544 | switch (hpd) { |
| 545 | case RADEON_HPD_1: |
| 546 | tmp = RREG32(RADEON_FP_GEN_CNTL); |
| 547 | if (connected) |
| 548 | tmp &= ~RADEON_FP_DETECT_INT_POL; |
| 549 | else |
| 550 | tmp |= RADEON_FP_DETECT_INT_POL; |
| 551 | WREG32(RADEON_FP_GEN_CNTL, tmp); |
| 552 | break; |
| 553 | case RADEON_HPD_2: |
| 554 | tmp = RREG32(RADEON_FP2_GEN_CNTL); |
| 555 | if (connected) |
| 556 | tmp &= ~RADEON_FP2_DETECT_INT_POL; |
| 557 | else |
| 558 | tmp |= RADEON_FP2_DETECT_INT_POL; |
| 559 | WREG32(RADEON_FP2_GEN_CNTL, tmp); |
| 560 | break; |
| 561 | default: |
| 562 | break; |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | void r100_hpd_init(struct radeon_device *rdev) |
| 567 | { |
| 568 | struct drm_device *dev = rdev->ddev; |
| 569 | struct drm_connector *connector; |
| 570 | |
| 571 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 572 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 573 | switch (radeon_connector->hpd.hpd) { |
| 574 | case RADEON_HPD_1: |
| 575 | rdev->irq.hpd[0] = true; |
| 576 | break; |
| 577 | case RADEON_HPD_2: |
| 578 | rdev->irq.hpd[1] = true; |
| 579 | break; |
| 580 | default: |
| 581 | break; |
| 582 | } |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 583 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 584 | } |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 585 | if (rdev->irq.installed) |
| 586 | r100_irq_set(rdev); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | void r100_hpd_fini(struct radeon_device *rdev) |
| 590 | { |
| 591 | struct drm_device *dev = rdev->ddev; |
| 592 | struct drm_connector *connector; |
| 593 | |
| 594 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 595 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 596 | switch (radeon_connector->hpd.hpd) { |
| 597 | case RADEON_HPD_1: |
| 598 | rdev->irq.hpd[0] = false; |
| 599 | break; |
| 600 | case RADEON_HPD_2: |
| 601 | rdev->irq.hpd[1] = false; |
| 602 | break; |
| 603 | default: |
| 604 | break; |
| 605 | } |
| 606 | } |
| 607 | } |
| 608 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 609 | /* |
| 610 | * PCI GART |
| 611 | */ |
| 612 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
| 613 | { |
| 614 | /* TODO: can we do somethings here ? */ |
| 615 | /* It seems hw only cache one entry so we should discard this |
| 616 | * entry otherwise if first GPU GART read hit this entry it |
| 617 | * could end up in wrong address. */ |
| 618 | } |
| 619 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 620 | int r100_pci_gart_init(struct radeon_device *rdev) |
| 621 | { |
| 622 | int r; |
| 623 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 624 | if (rdev->gart.ptr) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 625 | WARN(1, "R100 PCI GART already initialized\n"); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 626 | return 0; |
| 627 | } |
| 628 | /* Initialize common gart structure */ |
| 629 | r = radeon_gart_init(rdev); |
| 630 | if (r) |
| 631 | return r; |
| 632 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 633 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
| 634 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 635 | return radeon_gart_table_ram_alloc(rdev); |
| 636 | } |
| 637 | |
Dave Airlie | 17e15b0 | 2009-11-05 15:36:53 +1000 | [diff] [blame] | 638 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
| 639 | void r100_enable_bm(struct radeon_device *rdev) |
| 640 | { |
| 641 | uint32_t tmp; |
| 642 | /* Enable bus mastering */ |
| 643 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| 644 | WREG32(RADEON_BUS_CNTL, tmp); |
| 645 | } |
| 646 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 647 | int r100_pci_gart_enable(struct radeon_device *rdev) |
| 648 | { |
| 649 | uint32_t tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 650 | |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 651 | radeon_gart_restore(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 652 | /* discard memory request outside of configured range */ |
| 653 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
| 654 | WREG32(RADEON_AIC_CNTL, tmp); |
| 655 | /* set address range for PCI address translate */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 656 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
| 657 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 658 | /* set PCI GART page-table base address */ |
| 659 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
| 660 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
| 661 | WREG32(RADEON_AIC_CNTL, tmp); |
| 662 | r100_pci_gart_tlb_flush(rdev); |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 663 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 664 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 665 | (unsigned long long)rdev->gart.table_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 666 | rdev->gart.ready = true; |
| 667 | return 0; |
| 668 | } |
| 669 | |
| 670 | void r100_pci_gart_disable(struct radeon_device *rdev) |
| 671 | { |
| 672 | uint32_t tmp; |
| 673 | |
| 674 | /* discard memory request outside of configured range */ |
| 675 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
| 676 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
| 677 | WREG32(RADEON_AIC_LO_ADDR, 0); |
| 678 | WREG32(RADEON_AIC_HI_ADDR, 0); |
| 679 | } |
| 680 | |
| 681 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| 682 | { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 683 | u32 *gtt = rdev->gart.ptr; |
| 684 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 685 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
| 686 | return -EINVAL; |
| 687 | } |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 688 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 689 | return 0; |
| 690 | } |
| 691 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 692 | void r100_pci_gart_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 693 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 694 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 695 | r100_pci_gart_disable(rdev); |
| 696 | radeon_gart_table_ram_free(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 697 | } |
| 698 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 699 | int r100_irq_set(struct radeon_device *rdev) |
| 700 | { |
| 701 | uint32_t tmp = 0; |
| 702 | |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 703 | if (!rdev->irq.installed) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 704 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 705 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 706 | return -EINVAL; |
| 707 | } |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 708 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 709 | tmp |= RADEON_SW_INT_ENABLE; |
| 710 | } |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 711 | if (rdev->irq.gui_idle) { |
| 712 | tmp |= RADEON_GUI_IDLE_MASK; |
| 713 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 714 | if (rdev->irq.crtc_vblank_int[0] || |
| 715 | rdev->irq.pflip[0]) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 716 | tmp |= RADEON_CRTC_VBLANK_MASK; |
| 717 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 718 | if (rdev->irq.crtc_vblank_int[1] || |
| 719 | rdev->irq.pflip[1]) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 720 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
| 721 | } |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 722 | if (rdev->irq.hpd[0]) { |
| 723 | tmp |= RADEON_FP_DETECT_MASK; |
| 724 | } |
| 725 | if (rdev->irq.hpd[1]) { |
| 726 | tmp |= RADEON_FP2_DETECT_MASK; |
| 727 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 728 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
| 729 | return 0; |
| 730 | } |
| 731 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 732 | void r100_irq_disable(struct radeon_device *rdev) |
| 733 | { |
| 734 | u32 tmp; |
| 735 | |
| 736 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 737 | /* Wait and acknowledge irq */ |
| 738 | mdelay(1); |
| 739 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
| 740 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
| 741 | } |
| 742 | |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 743 | static uint32_t r100_irq_ack(struct radeon_device *rdev) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 744 | { |
| 745 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 746 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
| 747 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
| 748 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 749 | |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 750 | /* the interrupt works, but the status bit is permanently asserted */ |
| 751 | if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { |
| 752 | if (!rdev->irq.gui_idle_acked) |
| 753 | irq_mask |= RADEON_GUI_IDLE_STAT; |
| 754 | } |
| 755 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 756 | if (irqs) { |
| 757 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
| 758 | } |
| 759 | return irqs & irq_mask; |
| 760 | } |
| 761 | |
| 762 | int r100_irq_process(struct radeon_device *rdev) |
| 763 | { |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 764 | uint32_t status, msi_rearm; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 765 | bool queue_hotplug = false; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 766 | |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 767 | /* reset gui idle ack. the status bit is broken */ |
| 768 | rdev->irq.gui_idle_acked = false; |
| 769 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 770 | status = r100_irq_ack(rdev); |
| 771 | if (!status) { |
| 772 | return IRQ_NONE; |
| 773 | } |
Jerome Glisse | a513c18 | 2009-09-09 22:23:07 +0200 | [diff] [blame] | 774 | if (rdev->shutdown) { |
| 775 | return IRQ_NONE; |
| 776 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 777 | while (status) { |
| 778 | /* SW interrupt */ |
| 779 | if (status & RADEON_SW_INT_TEST) { |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 780 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 781 | } |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 782 | /* gui idle interrupt */ |
| 783 | if (status & RADEON_GUI_IDLE_STAT) { |
| 784 | rdev->irq.gui_idle_acked = true; |
| 785 | rdev->pm.gui_idle = true; |
| 786 | wake_up(&rdev->irq.idle_queue); |
| 787 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 788 | /* Vertical blank interrupts */ |
| 789 | if (status & RADEON_CRTC_VBLANK_STAT) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 790 | if (rdev->irq.crtc_vblank_int[0]) { |
| 791 | drm_handle_vblank(rdev->ddev, 0); |
| 792 | rdev->pm.vblank_sync = true; |
| 793 | wake_up(&rdev->irq.vblank_queue); |
| 794 | } |
Mario Kleiner | 3e4ea74 | 2010-11-21 10:59:02 -0500 | [diff] [blame] | 795 | if (rdev->irq.pflip[0]) |
| 796 | radeon_crtc_handle_flip(rdev, 0); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 797 | } |
| 798 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 799 | if (rdev->irq.crtc_vblank_int[1]) { |
| 800 | drm_handle_vblank(rdev->ddev, 1); |
| 801 | rdev->pm.vblank_sync = true; |
| 802 | wake_up(&rdev->irq.vblank_queue); |
| 803 | } |
Mario Kleiner | 3e4ea74 | 2010-11-21 10:59:02 -0500 | [diff] [blame] | 804 | if (rdev->irq.pflip[1]) |
| 805 | radeon_crtc_handle_flip(rdev, 1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 806 | } |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 807 | if (status & RADEON_FP_DETECT_STAT) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 808 | queue_hotplug = true; |
| 809 | DRM_DEBUG("HPD1\n"); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 810 | } |
| 811 | if (status & RADEON_FP2_DETECT_STAT) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 812 | queue_hotplug = true; |
| 813 | DRM_DEBUG("HPD2\n"); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 814 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 815 | status = r100_irq_ack(rdev); |
| 816 | } |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 817 | /* reset gui idle ack. the status bit is broken */ |
| 818 | rdev->irq.gui_idle_acked = false; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 819 | if (queue_hotplug) |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 820 | schedule_work(&rdev->hotplug_work); |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 821 | if (rdev->msi_enabled) { |
| 822 | switch (rdev->family) { |
| 823 | case CHIP_RS400: |
| 824 | case CHIP_RS480: |
| 825 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
| 826 | WREG32(RADEON_AIC_CNTL, msi_rearm); |
| 827 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
| 828 | break; |
| 829 | default: |
Alex Deucher | b7f5b7d | 2012-02-13 16:36:34 -0500 | [diff] [blame] | 830 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 831 | break; |
| 832 | } |
| 833 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 834 | return IRQ_HANDLED; |
| 835 | } |
| 836 | |
| 837 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| 838 | { |
| 839 | if (crtc == 0) |
| 840 | return RREG32(RADEON_CRTC_CRNT_FRAME); |
| 841 | else |
| 842 | return RREG32(RADEON_CRTC2_CRNT_FRAME); |
| 843 | } |
| 844 | |
Pauli Nieminen | 9e5b2af | 2010-02-04 19:20:53 +0200 | [diff] [blame] | 845 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
| 846 | * for enough space (today caller are ib schedule and buffer move) */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 847 | void r100_fence_ring_emit(struct radeon_device *rdev, |
| 848 | struct radeon_fence *fence) |
| 849 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 850 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 851 | |
Pauli Nieminen | 9e5b2af | 2010-02-04 19:20:53 +0200 | [diff] [blame] | 852 | /* We have to make sure that caches are flushed before |
| 853 | * CPU might read something from VRAM. */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 854 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
| 855 | radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); |
| 856 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); |
| 857 | radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 858 | /* Wait until IDLE & CLEAN */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 859 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 860 | radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| 861 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
| 862 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl | |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 863 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 864 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
| 865 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 866 | /* Emit fence sequence & fire IRQ */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 867 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
| 868 | radeon_ring_write(ring, fence->seq); |
| 869 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
| 870 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 871 | } |
| 872 | |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 873 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 874 | struct radeon_ring *ring, |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 875 | struct radeon_semaphore *semaphore, |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 876 | bool emit_wait) |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 877 | { |
| 878 | /* Unused on older asics, since we don't have semaphores or multiple rings */ |
| 879 | BUG(); |
| 880 | } |
| 881 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 882 | int r100_copy_blit(struct radeon_device *rdev, |
| 883 | uint64_t src_offset, |
| 884 | uint64_t dst_offset, |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 885 | unsigned num_gpu_pages, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 886 | struct radeon_fence *fence) |
| 887 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 888 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 889 | uint32_t cur_pages; |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 890 | uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 891 | uint32_t pitch; |
| 892 | uint32_t stride_pixels; |
| 893 | unsigned ndw; |
| 894 | int num_loops; |
| 895 | int r = 0; |
| 896 | |
| 897 | /* radeon limited to 16k stride */ |
| 898 | stride_bytes &= 0x3fff; |
| 899 | /* radeon pitch is /64 */ |
| 900 | pitch = stride_bytes / 64; |
| 901 | stride_pixels = stride_bytes / 4; |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 902 | num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 903 | |
| 904 | /* Ask for enough room for blit + flush + fence */ |
| 905 | ndw = 64 + (10 * num_loops); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 906 | r = radeon_ring_lock(rdev, ring, ndw); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 907 | if (r) { |
| 908 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
| 909 | return -EINVAL; |
| 910 | } |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 911 | while (num_gpu_pages > 0) { |
| 912 | cur_pages = num_gpu_pages; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 913 | if (cur_pages > 8191) { |
| 914 | cur_pages = 8191; |
| 915 | } |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 916 | num_gpu_pages -= cur_pages; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 917 | |
| 918 | /* pages are in Y direction - height |
| 919 | page width in X direction - width */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 920 | radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
| 921 | radeon_ring_write(ring, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 922 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| 923 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 924 | RADEON_GMC_SRC_CLIPPING | |
| 925 | RADEON_GMC_DST_CLIPPING | |
| 926 | RADEON_GMC_BRUSH_NONE | |
| 927 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
| 928 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 929 | RADEON_ROP3_S | |
| 930 | RADEON_DP_SRC_SOURCE_MEMORY | |
| 931 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
| 932 | RADEON_GMC_WR_MSK_DIS); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 933 | radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); |
| 934 | radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); |
| 935 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
| 936 | radeon_ring_write(ring, 0); |
| 937 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
| 938 | radeon_ring_write(ring, num_gpu_pages); |
| 939 | radeon_ring_write(ring, num_gpu_pages); |
| 940 | radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 941 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 942 | radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
| 943 | radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); |
| 944 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 945 | radeon_ring_write(ring, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 946 | RADEON_WAIT_2D_IDLECLEAN | |
| 947 | RADEON_WAIT_HOST_IDLECLEAN | |
| 948 | RADEON_WAIT_DMA_GUI_IDLE); |
| 949 | if (fence) { |
| 950 | r = radeon_fence_emit(rdev, fence); |
| 951 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 952 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 953 | return r; |
| 954 | } |
| 955 | |
Jerome Glisse | 4560023 | 2009-09-09 22:23:45 +0200 | [diff] [blame] | 956 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
| 957 | { |
| 958 | unsigned i; |
| 959 | u32 tmp; |
| 960 | |
| 961 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 962 | tmp = RREG32(R_000E40_RBBM_STATUS); |
| 963 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { |
| 964 | return 0; |
| 965 | } |
| 966 | udelay(1); |
| 967 | } |
| 968 | return -1; |
| 969 | } |
| 970 | |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 971 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 972 | { |
| 973 | int r; |
| 974 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 975 | r = radeon_ring_lock(rdev, ring, 2); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 976 | if (r) { |
| 977 | return; |
| 978 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 979 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
| 980 | radeon_ring_write(ring, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 981 | RADEON_ISYNC_ANY2D_IDLE3D | |
| 982 | RADEON_ISYNC_ANY3D_IDLE2D | |
| 983 | RADEON_ISYNC_WAIT_IDLEGUI | |
| 984 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 985 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 986 | } |
| 987 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 988 | |
| 989 | /* Load the microcode for the CP */ |
| 990 | static int r100_cp_init_microcode(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 991 | { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 992 | struct platform_device *pdev; |
| 993 | const char *fw_name = NULL; |
| 994 | int err; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 995 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 996 | DRM_DEBUG_KMS("\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 997 | |
| 998 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| 999 | err = IS_ERR(pdev); |
| 1000 | if (err) { |
| 1001 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| 1002 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1003 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1004 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
| 1005 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
| 1006 | (rdev->family == CHIP_RS200)) { |
| 1007 | DRM_INFO("Loading R100 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1008 | fw_name = FIRMWARE_R100; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1009 | } else if ((rdev->family == CHIP_R200) || |
| 1010 | (rdev->family == CHIP_RV250) || |
| 1011 | (rdev->family == CHIP_RV280) || |
| 1012 | (rdev->family == CHIP_RS300)) { |
| 1013 | DRM_INFO("Loading R200 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1014 | fw_name = FIRMWARE_R200; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1015 | } else if ((rdev->family == CHIP_R300) || |
| 1016 | (rdev->family == CHIP_R350) || |
| 1017 | (rdev->family == CHIP_RV350) || |
| 1018 | (rdev->family == CHIP_RV380) || |
| 1019 | (rdev->family == CHIP_RS400) || |
| 1020 | (rdev->family == CHIP_RS480)) { |
| 1021 | DRM_INFO("Loading R300 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1022 | fw_name = FIRMWARE_R300; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1023 | } else if ((rdev->family == CHIP_R420) || |
| 1024 | (rdev->family == CHIP_R423) || |
| 1025 | (rdev->family == CHIP_RV410)) { |
| 1026 | DRM_INFO("Loading R400 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1027 | fw_name = FIRMWARE_R420; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1028 | } else if ((rdev->family == CHIP_RS690) || |
| 1029 | (rdev->family == CHIP_RS740)) { |
| 1030 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1031 | fw_name = FIRMWARE_RS690; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1032 | } else if (rdev->family == CHIP_RS600) { |
| 1033 | DRM_INFO("Loading RS600 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1034 | fw_name = FIRMWARE_RS600; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1035 | } else if ((rdev->family == CHIP_RV515) || |
| 1036 | (rdev->family == CHIP_R520) || |
| 1037 | (rdev->family == CHIP_RV530) || |
| 1038 | (rdev->family == CHIP_R580) || |
| 1039 | (rdev->family == CHIP_RV560) || |
| 1040 | (rdev->family == CHIP_RV570)) { |
| 1041 | DRM_INFO("Loading R500 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1042 | fw_name = FIRMWARE_R520; |
| 1043 | } |
| 1044 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1045 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1046 | platform_device_unregister(pdev); |
| 1047 | if (err) { |
| 1048 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
| 1049 | fw_name); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1050 | } else if (rdev->me_fw->size % 8) { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1051 | printk(KERN_ERR |
| 1052 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1053 | rdev->me_fw->size, fw_name); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1054 | err = -EINVAL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1055 | release_firmware(rdev->me_fw); |
| 1056 | rdev->me_fw = NULL; |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1057 | } |
| 1058 | return err; |
| 1059 | } |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 1060 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1061 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
| 1062 | { |
| 1063 | const __be32 *fw_data; |
| 1064 | int i, size; |
| 1065 | |
| 1066 | if (r100_gui_wait_for_idle(rdev)) { |
| 1067 | printk(KERN_WARNING "Failed to wait GUI idle while " |
| 1068 | "programming pipes. Bad things might happen.\n"); |
| 1069 | } |
| 1070 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1071 | if (rdev->me_fw) { |
| 1072 | size = rdev->me_fw->size / 4; |
| 1073 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1074 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
| 1075 | for (i = 0; i < size; i += 2) { |
| 1076 | WREG32(RADEON_CP_ME_RAM_DATAH, |
| 1077 | be32_to_cpup(&fw_data[i])); |
| 1078 | WREG32(RADEON_CP_ME_RAM_DATAL, |
| 1079 | be32_to_cpup(&fw_data[i + 1])); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1080 | } |
| 1081 | } |
| 1082 | } |
| 1083 | |
| 1084 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
| 1085 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1086 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1087 | unsigned rb_bufsz; |
| 1088 | unsigned rb_blksz; |
| 1089 | unsigned max_fetch; |
| 1090 | unsigned pre_write_timer; |
| 1091 | unsigned pre_write_limit; |
| 1092 | unsigned indirect2_start; |
| 1093 | unsigned indirect1_start; |
| 1094 | uint32_t tmp; |
| 1095 | int r; |
| 1096 | |
| 1097 | if (r100_debugfs_cp_init(rdev)) { |
| 1098 | DRM_ERROR("Failed to register debugfs file for CP !\n"); |
| 1099 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1100 | if (!rdev->me_fw) { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1101 | r = r100_cp_init_microcode(rdev); |
| 1102 | if (r) { |
| 1103 | DRM_ERROR("Failed to load firmware!\n"); |
| 1104 | return r; |
| 1105 | } |
| 1106 | } |
| 1107 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1108 | /* Align ring size */ |
| 1109 | rb_bufsz = drm_order(ring_size / 8); |
| 1110 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
| 1111 | r100_cp_load_microcode(rdev); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1112 | r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 1113 | RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, |
| 1114 | 0, 0x7fffff, RADEON_CP_PACKET2); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1115 | if (r) { |
| 1116 | return r; |
| 1117 | } |
| 1118 | /* Each time the cp read 1024 bytes (16 dword/quadword) update |
| 1119 | * the rptr copy in system ram */ |
| 1120 | rb_blksz = 9; |
| 1121 | /* cp will read 128bytes at a time (4 dwords) */ |
| 1122 | max_fetch = 1; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1123 | ring->align_mask = 16 - 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1124 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
| 1125 | pre_write_timer = 64; |
| 1126 | /* Force CP_RB_WPTR write if written more than one time before the |
| 1127 | * delay expire |
| 1128 | */ |
| 1129 | pre_write_limit = 0; |
| 1130 | /* Setup the cp cache like this (cache size is 96 dwords) : |
| 1131 | * RING 0 to 15 |
| 1132 | * INDIRECT1 16 to 79 |
| 1133 | * INDIRECT2 80 to 95 |
| 1134 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
| 1135 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
| 1136 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
| 1137 | * Idea being that most of the gpu cmd will be through indirect1 buffer |
| 1138 | * so it gets the bigger cache. |
| 1139 | */ |
| 1140 | indirect2_start = 80; |
| 1141 | indirect1_start = 16; |
| 1142 | /* cp setup */ |
| 1143 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 1144 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1145 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1146 | REG_SET(RADEON_MAX_FETCH, max_fetch)); |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 1147 | #ifdef __BIG_ENDIAN |
| 1148 | tmp |= RADEON_BUF_SWAP_32BIT; |
| 1149 | #endif |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1150 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 1151 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1152 | /* Set ring address */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1153 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); |
| 1154 | WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1155 | /* Force read & write ptr to 0 */ |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1156 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1157 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1158 | ring->wptr = 0; |
| 1159 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1160 | |
| 1161 | /* set the wb address whether it's enabled or not */ |
| 1162 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
| 1163 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); |
| 1164 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); |
| 1165 | |
| 1166 | if (rdev->wb.enabled) |
| 1167 | WREG32(R_000770_SCRATCH_UMSK, 0xff); |
| 1168 | else { |
| 1169 | tmp |= RADEON_RB_NO_UPDATE; |
| 1170 | WREG32(R_000770_SCRATCH_UMSK, 0); |
| 1171 | } |
| 1172 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1173 | WREG32(RADEON_CP_RB_CNTL, tmp); |
| 1174 | udelay(10); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1175 | ring->rptr = RREG32(RADEON_CP_RB_RPTR); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1176 | /* Set cp mode to bus mastering & enable cp*/ |
| 1177 | WREG32(RADEON_CP_CSQ_MODE, |
| 1178 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
| 1179 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 1180 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
| 1181 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1182 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
Dave Airlie | 2099810 | 2012-04-03 11:53:05 +0100 | [diff] [blame] | 1183 | |
| 1184 | /* at this point everything should be setup correctly to enable master */ |
| 1185 | pci_set_master(rdev->pdev); |
| 1186 | |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1187 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
| 1188 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1189 | if (r) { |
| 1190 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
| 1191 | return r; |
| 1192 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1193 | ring->ready = true; |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1194 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1195 | return 0; |
| 1196 | } |
| 1197 | |
| 1198 | void r100_cp_fini(struct radeon_device *rdev) |
| 1199 | { |
Jerome Glisse | 4560023 | 2009-09-09 22:23:45 +0200 | [diff] [blame] | 1200 | if (r100_cp_wait_for_idle(rdev)) { |
| 1201 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); |
| 1202 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1203 | /* Disable ring */ |
Jerome Glisse | a18d7ea | 2009-09-09 22:23:27 +0200 | [diff] [blame] | 1204 | r100_cp_disable(rdev); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1205 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1206 | DRM_INFO("radeon: cp finalized\n"); |
| 1207 | } |
| 1208 | |
| 1209 | void r100_cp_disable(struct radeon_device *rdev) |
| 1210 | { |
| 1211 | /* Disable ring */ |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1212 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1213 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1214 | WREG32(RADEON_CP_CSQ_MODE, 0); |
| 1215 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1216 | WREG32(R_000770_SCRATCH_UMSK, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1217 | if (r100_gui_wait_for_idle(rdev)) { |
| 1218 | printk(KERN_WARNING "Failed to wait GUI idle while " |
| 1219 | "programming pipes. Bad things might happen.\n"); |
| 1220 | } |
| 1221 | } |
| 1222 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1223 | /* |
| 1224 | * CS functions |
| 1225 | */ |
| 1226 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
| 1227 | struct radeon_cs_packet *pkt, |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1228 | const unsigned *auth, unsigned n, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1229 | radeon_packet0_check_t check) |
| 1230 | { |
| 1231 | unsigned reg; |
| 1232 | unsigned i, j, m; |
| 1233 | unsigned idx; |
| 1234 | int r; |
| 1235 | |
| 1236 | idx = pkt->idx + 1; |
| 1237 | reg = pkt->reg; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1238 | /* Check that register fall into register range |
| 1239 | * determined by the number of entry (n) in the |
| 1240 | * safe register bitmap. |
| 1241 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1242 | if (pkt->one_reg_wr) { |
| 1243 | if ((reg >> 7) > n) { |
| 1244 | return -EINVAL; |
| 1245 | } |
| 1246 | } else { |
| 1247 | if (((reg + (pkt->count << 2)) >> 7) > n) { |
| 1248 | return -EINVAL; |
| 1249 | } |
| 1250 | } |
| 1251 | for (i = 0; i <= pkt->count; i++, idx++) { |
| 1252 | j = (reg >> 7); |
| 1253 | m = 1 << ((reg >> 2) & 31); |
| 1254 | if (auth[j] & m) { |
| 1255 | r = check(p, pkt, idx, reg); |
| 1256 | if (r) { |
| 1257 | return r; |
| 1258 | } |
| 1259 | } |
| 1260 | if (pkt->one_reg_wr) { |
| 1261 | if (!(auth[j] & m)) { |
| 1262 | break; |
| 1263 | } |
| 1264 | } else { |
| 1265 | reg += 4; |
| 1266 | } |
| 1267 | } |
| 1268 | return 0; |
| 1269 | } |
| 1270 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1271 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
| 1272 | struct radeon_cs_packet *pkt) |
| 1273 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1274 | volatile uint32_t *ib; |
| 1275 | unsigned i; |
| 1276 | unsigned idx; |
| 1277 | |
| 1278 | ib = p->ib->ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1279 | idx = pkt->idx; |
| 1280 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
| 1281 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
| 1282 | } |
| 1283 | } |
| 1284 | |
| 1285 | /** |
| 1286 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet |
| 1287 | * @parser: parser structure holding parsing context. |
| 1288 | * @pkt: where to store packet informations |
| 1289 | * |
| 1290 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
| 1291 | * if packet is bigger than remaining ib size. or if packets is unknown. |
| 1292 | **/ |
| 1293 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
| 1294 | struct radeon_cs_packet *pkt, |
| 1295 | unsigned idx) |
| 1296 | { |
| 1297 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
Roel Kluin | fa99239 | 2009-08-03 14:20:32 +0200 | [diff] [blame] | 1298 | uint32_t header; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1299 | |
| 1300 | if (idx >= ib_chunk->length_dw) { |
| 1301 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
| 1302 | idx, ib_chunk->length_dw); |
| 1303 | return -EINVAL; |
| 1304 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1305 | header = radeon_get_ib_value(p, idx); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1306 | pkt->idx = idx; |
| 1307 | pkt->type = CP_PACKET_GET_TYPE(header); |
| 1308 | pkt->count = CP_PACKET_GET_COUNT(header); |
| 1309 | switch (pkt->type) { |
| 1310 | case PACKET_TYPE0: |
| 1311 | pkt->reg = CP_PACKET0_GET_REG(header); |
| 1312 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); |
| 1313 | break; |
| 1314 | case PACKET_TYPE3: |
| 1315 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); |
| 1316 | break; |
| 1317 | case PACKET_TYPE2: |
| 1318 | pkt->count = -1; |
| 1319 | break; |
| 1320 | default: |
| 1321 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
| 1322 | return -EINVAL; |
| 1323 | } |
| 1324 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
| 1325 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
| 1326 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
| 1327 | return -EINVAL; |
| 1328 | } |
| 1329 | return 0; |
| 1330 | } |
| 1331 | |
| 1332 | /** |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1333 | * r100_cs_packet_next_vline() - parse userspace VLINE packet |
| 1334 | * @parser: parser structure holding parsing context. |
| 1335 | * |
| 1336 | * Userspace sends a special sequence for VLINE waits. |
| 1337 | * PACKET0 - VLINE_START_END + value |
| 1338 | * PACKET0 - WAIT_UNTIL +_value |
| 1339 | * RELOC (P3) - crtc_id in reloc. |
| 1340 | * |
| 1341 | * This function parses this and relocates the VLINE START END |
| 1342 | * and WAIT UNTIL packets to the correct crtc. |
| 1343 | * It also detects a switched off crtc and nulls out the |
| 1344 | * wait in that case. |
| 1345 | */ |
| 1346 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
| 1347 | { |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1348 | struct drm_mode_object *obj; |
| 1349 | struct drm_crtc *crtc; |
| 1350 | struct radeon_crtc *radeon_crtc; |
| 1351 | struct radeon_cs_packet p3reloc, waitreloc; |
| 1352 | int crtc_id; |
| 1353 | int r; |
| 1354 | uint32_t header, h_idx, reg; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1355 | volatile uint32_t *ib; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1356 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1357 | ib = p->ib->ptr; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1358 | |
| 1359 | /* parse the wait until */ |
| 1360 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
| 1361 | if (r) |
| 1362 | return r; |
| 1363 | |
| 1364 | /* check its a wait until and only 1 count */ |
| 1365 | if (waitreloc.reg != RADEON_WAIT_UNTIL || |
| 1366 | waitreloc.count != 0) { |
| 1367 | DRM_ERROR("vline wait had illegal wait until segment\n"); |
Paul Bolle | a3a88a6 | 2011-03-16 22:10:06 +0100 | [diff] [blame] | 1368 | return -EINVAL; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1369 | } |
| 1370 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1371 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1372 | DRM_ERROR("vline wait had illegal wait until\n"); |
Paul Bolle | a3a88a6 | 2011-03-16 22:10:06 +0100 | [diff] [blame] | 1373 | return -EINVAL; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1374 | } |
| 1375 | |
| 1376 | /* jump over the NOP */ |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 1377 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1378 | if (r) |
| 1379 | return r; |
| 1380 | |
| 1381 | h_idx = p->idx - 2; |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 1382 | p->idx += waitreloc.count + 2; |
| 1383 | p->idx += p3reloc.count + 2; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1384 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1385 | header = radeon_get_ib_value(p, h_idx); |
| 1386 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
Dave Airlie | d4ac6a0 | 2009-10-08 11:32:49 +1000 | [diff] [blame] | 1387 | reg = CP_PACKET0_GET_REG(header); |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1388 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
| 1389 | if (!obj) { |
| 1390 | DRM_ERROR("cannot find crtc %d\n", crtc_id); |
Paul Bolle | a3a88a6 | 2011-03-16 22:10:06 +0100 | [diff] [blame] | 1391 | return -EINVAL; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1392 | } |
| 1393 | crtc = obj_to_crtc(obj); |
| 1394 | radeon_crtc = to_radeon_crtc(crtc); |
| 1395 | crtc_id = radeon_crtc->crtc_id; |
| 1396 | |
| 1397 | if (!crtc->enabled) { |
| 1398 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1399 | ib[h_idx + 2] = PACKET2(0); |
| 1400 | ib[h_idx + 3] = PACKET2(0); |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1401 | } else if (crtc_id == 1) { |
| 1402 | switch (reg) { |
| 1403 | case AVIVO_D1MODE_VLINE_START_END: |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 1404 | header &= ~R300_CP_PACKET0_REG_MASK; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1405 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
| 1406 | break; |
| 1407 | case RADEON_CRTC_GUI_TRIG_VLINE: |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 1408 | header &= ~R300_CP_PACKET0_REG_MASK; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1409 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
| 1410 | break; |
| 1411 | default: |
| 1412 | DRM_ERROR("unknown crtc reloc\n"); |
Paul Bolle | a3a88a6 | 2011-03-16 22:10:06 +0100 | [diff] [blame] | 1413 | return -EINVAL; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1414 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1415 | ib[h_idx] = header; |
| 1416 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1417 | } |
Paul Bolle | a3a88a6 | 2011-03-16 22:10:06 +0100 | [diff] [blame] | 1418 | |
| 1419 | return 0; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1420 | } |
| 1421 | |
| 1422 | /** |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1423 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
| 1424 | * @parser: parser structure holding parsing context. |
| 1425 | * @data: pointer to relocation data |
| 1426 | * @offset_start: starting offset |
| 1427 | * @offset_mask: offset mask (to align start offset on) |
| 1428 | * @reloc: reloc informations |
| 1429 | * |
| 1430 | * Check next packet is relocation packet3, do bo validation and compute |
| 1431 | * GPU offset using the provided start. |
| 1432 | **/ |
| 1433 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| 1434 | struct radeon_cs_reloc **cs_reloc) |
| 1435 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1436 | struct radeon_cs_chunk *relocs_chunk; |
| 1437 | struct radeon_cs_packet p3reloc; |
| 1438 | unsigned idx; |
| 1439 | int r; |
| 1440 | |
| 1441 | if (p->chunk_relocs_idx == -1) { |
| 1442 | DRM_ERROR("No relocation chunk !\n"); |
| 1443 | return -EINVAL; |
| 1444 | } |
| 1445 | *cs_reloc = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1446 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
| 1447 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
| 1448 | if (r) { |
| 1449 | return r; |
| 1450 | } |
| 1451 | p->idx += p3reloc.count + 2; |
| 1452 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { |
| 1453 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
| 1454 | p3reloc.idx); |
| 1455 | r100_cs_dump_packet(p, &p3reloc); |
| 1456 | return -EINVAL; |
| 1457 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1458 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1459 | if (idx >= relocs_chunk->length_dw) { |
| 1460 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
| 1461 | idx, relocs_chunk->length_dw); |
| 1462 | r100_cs_dump_packet(p, &p3reloc); |
| 1463 | return -EINVAL; |
| 1464 | } |
| 1465 | /* FIXME: we assume reloc size is 4 dwords */ |
| 1466 | *cs_reloc = p->relocs_ptr[(idx / 4)]; |
| 1467 | return 0; |
| 1468 | } |
| 1469 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1470 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
| 1471 | { |
| 1472 | int vtx_size; |
| 1473 | vtx_size = 2; |
| 1474 | /* ordered according to bits in spec */ |
| 1475 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) |
| 1476 | vtx_size++; |
| 1477 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) |
| 1478 | vtx_size += 3; |
| 1479 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) |
| 1480 | vtx_size++; |
| 1481 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) |
| 1482 | vtx_size++; |
| 1483 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) |
| 1484 | vtx_size += 3; |
| 1485 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) |
| 1486 | vtx_size++; |
| 1487 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) |
| 1488 | vtx_size++; |
| 1489 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) |
| 1490 | vtx_size += 2; |
| 1491 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) |
| 1492 | vtx_size += 2; |
| 1493 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) |
| 1494 | vtx_size++; |
| 1495 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) |
| 1496 | vtx_size += 2; |
| 1497 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) |
| 1498 | vtx_size++; |
| 1499 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) |
| 1500 | vtx_size += 2; |
| 1501 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) |
| 1502 | vtx_size++; |
| 1503 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) |
| 1504 | vtx_size++; |
| 1505 | /* blend weight */ |
| 1506 | if (vtx_fmt & (0x7 << 15)) |
| 1507 | vtx_size += (vtx_fmt >> 15) & 0x7; |
| 1508 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) |
| 1509 | vtx_size += 3; |
| 1510 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) |
| 1511 | vtx_size += 2; |
| 1512 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) |
| 1513 | vtx_size++; |
| 1514 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) |
| 1515 | vtx_size++; |
| 1516 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) |
| 1517 | vtx_size++; |
| 1518 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) |
| 1519 | vtx_size++; |
| 1520 | return vtx_size; |
| 1521 | } |
| 1522 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1523 | static int r100_packet0_check(struct radeon_cs_parser *p, |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1524 | struct radeon_cs_packet *pkt, |
| 1525 | unsigned idx, unsigned reg) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1526 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1527 | struct radeon_cs_reloc *reloc; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1528 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1529 | volatile uint32_t *ib; |
| 1530 | uint32_t tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1531 | int r; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1532 | int i, face; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1533 | u32 tile_flags = 0; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1534 | u32 idx_value; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1535 | |
| 1536 | ib = p->ib->ptr; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1537 | track = (struct r100_cs_track *)p->track; |
| 1538 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1539 | idx_value = radeon_get_ib_value(p, idx); |
| 1540 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1541 | switch (reg) { |
| 1542 | case RADEON_CRTC_GUI_TRIG_VLINE: |
| 1543 | r = r100_cs_packet_parse_vline(p); |
| 1544 | if (r) { |
| 1545 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1546 | idx, reg); |
| 1547 | r100_cs_dump_packet(p, pkt); |
| 1548 | return r; |
| 1549 | } |
| 1550 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1551 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
| 1552 | * range access */ |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1553 | case RADEON_DST_PITCH_OFFSET: |
| 1554 | case RADEON_SRC_PITCH_OFFSET: |
| 1555 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
| 1556 | if (r) |
| 1557 | return r; |
| 1558 | break; |
| 1559 | case RADEON_RB3D_DEPTHOFFSET: |
| 1560 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1561 | if (r) { |
| 1562 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1563 | idx, reg); |
| 1564 | r100_cs_dump_packet(p, pkt); |
| 1565 | return r; |
| 1566 | } |
| 1567 | track->zb.robj = reloc->robj; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1568 | track->zb.offset = idx_value; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1569 | track->zb_dirty = true; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1570 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1571 | break; |
| 1572 | case RADEON_RB3D_COLOROFFSET: |
| 1573 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1574 | if (r) { |
| 1575 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1576 | idx, reg); |
| 1577 | r100_cs_dump_packet(p, pkt); |
| 1578 | return r; |
| 1579 | } |
| 1580 | track->cb[0].robj = reloc->robj; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1581 | track->cb[0].offset = idx_value; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1582 | track->cb_dirty = true; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1583 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1584 | break; |
| 1585 | case RADEON_PP_TXOFFSET_0: |
| 1586 | case RADEON_PP_TXOFFSET_1: |
| 1587 | case RADEON_PP_TXOFFSET_2: |
| 1588 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
| 1589 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1590 | if (r) { |
| 1591 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1592 | idx, reg); |
| 1593 | r100_cs_dump_packet(p, pkt); |
| 1594 | return r; |
| 1595 | } |
Alex Deucher | f2746f8 | 2012-02-02 10:11:12 -0500 | [diff] [blame] | 1596 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| 1597 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| 1598 | tile_flags |= RADEON_TXO_MACRO_TILE; |
| 1599 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| 1600 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; |
| 1601 | |
| 1602 | tmp = idx_value & ~(0x7 << 2); |
| 1603 | tmp |= tile_flags; |
| 1604 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); |
| 1605 | } else |
| 1606 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1607 | track->textures[i].robj = reloc->robj; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1608 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1609 | break; |
| 1610 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
| 1611 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
| 1612 | case RADEON_PP_CUBIC_OFFSET_T0_2: |
| 1613 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
| 1614 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
| 1615 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
| 1616 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1617 | if (r) { |
| 1618 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1619 | idx, reg); |
| 1620 | r100_cs_dump_packet(p, pkt); |
| 1621 | return r; |
| 1622 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1623 | track->textures[0].cube_info[i].offset = idx_value; |
| 1624 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1625 | track->textures[0].cube_info[i].robj = reloc->robj; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1626 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1627 | break; |
| 1628 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
| 1629 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
| 1630 | case RADEON_PP_CUBIC_OFFSET_T1_2: |
| 1631 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
| 1632 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
| 1633 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
| 1634 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1635 | if (r) { |
| 1636 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1637 | idx, reg); |
| 1638 | r100_cs_dump_packet(p, pkt); |
| 1639 | return r; |
| 1640 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1641 | track->textures[1].cube_info[i].offset = idx_value; |
| 1642 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1643 | track->textures[1].cube_info[i].robj = reloc->robj; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1644 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1645 | break; |
| 1646 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
| 1647 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
| 1648 | case RADEON_PP_CUBIC_OFFSET_T2_2: |
| 1649 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
| 1650 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
| 1651 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
| 1652 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1653 | if (r) { |
| 1654 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1655 | idx, reg); |
| 1656 | r100_cs_dump_packet(p, pkt); |
| 1657 | return r; |
| 1658 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1659 | track->textures[2].cube_info[i].offset = idx_value; |
| 1660 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1661 | track->textures[2].cube_info[i].robj = reloc->robj; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1662 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1663 | break; |
| 1664 | case RADEON_RE_WIDTH_HEIGHT: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1665 | track->maxy = ((idx_value >> 16) & 0x7FF); |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1666 | track->cb_dirty = true; |
| 1667 | track->zb_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1668 | break; |
| 1669 | case RADEON_RB3D_COLORPITCH: |
| 1670 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1671 | if (r) { |
| 1672 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1673 | idx, reg); |
| 1674 | r100_cs_dump_packet(p, pkt); |
| 1675 | return r; |
| 1676 | } |
Alex Deucher | c9068eb | 2012-02-02 10:11:11 -0500 | [diff] [blame] | 1677 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| 1678 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| 1679 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
| 1680 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| 1681 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1682 | |
Alex Deucher | c9068eb | 2012-02-02 10:11:11 -0500 | [diff] [blame] | 1683 | tmp = idx_value & ~(0x7 << 16); |
| 1684 | tmp |= tile_flags; |
| 1685 | ib[idx] = tmp; |
| 1686 | } else |
| 1687 | ib[idx] = idx_value; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1688 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1689 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1690 | track->cb_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1691 | break; |
| 1692 | case RADEON_RB3D_DEPTHPITCH: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1693 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1694 | track->zb_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1695 | break; |
| 1696 | case RADEON_RB3D_CNTL: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1697 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1698 | case 7: |
| 1699 | case 8: |
| 1700 | case 9: |
| 1701 | case 11: |
| 1702 | case 12: |
| 1703 | track->cb[0].cpp = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1704 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1705 | case 3: |
| 1706 | case 4: |
| 1707 | case 15: |
| 1708 | track->cb[0].cpp = 2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1709 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1710 | case 6: |
| 1711 | track->cb[0].cpp = 4; |
Dave Airlie | 17782d9 | 2009-08-21 10:07:54 +1000 | [diff] [blame] | 1712 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1713 | default: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1714 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1715 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1716 | return -EINVAL; |
| 1717 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1718 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1719 | track->cb_dirty = true; |
| 1720 | track->zb_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1721 | break; |
| 1722 | case RADEON_RB3D_ZSTENCILCNTL: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1723 | switch (idx_value & 0xf) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1724 | case 0: |
| 1725 | track->zb.cpp = 2; |
| 1726 | break; |
| 1727 | case 2: |
| 1728 | case 3: |
| 1729 | case 4: |
| 1730 | case 5: |
| 1731 | case 9: |
| 1732 | case 11: |
| 1733 | track->zb.cpp = 4; |
| 1734 | break; |
| 1735 | default: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1736 | break; |
| 1737 | } |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1738 | track->zb_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1739 | break; |
| 1740 | case RADEON_RB3D_ZPASS_ADDR: |
| 1741 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1742 | if (r) { |
| 1743 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1744 | idx, reg); |
| 1745 | r100_cs_dump_packet(p, pkt); |
| 1746 | return r; |
| 1747 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1748 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1749 | break; |
| 1750 | case RADEON_PP_CNTL: |
| 1751 | { |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1752 | uint32_t temp = idx_value >> 4; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1753 | for (i = 0; i < track->num_texture; i++) |
| 1754 | track->textures[i].enabled = !!(temp & (1 << i)); |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1755 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1756 | } |
| 1757 | break; |
| 1758 | case RADEON_SE_VF_CNTL: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1759 | track->vap_vf_cntl = idx_value; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1760 | break; |
| 1761 | case RADEON_SE_VTX_FMT: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1762 | track->vtx_size = r100_get_vtx_size(idx_value); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1763 | break; |
| 1764 | case RADEON_PP_TEX_SIZE_0: |
| 1765 | case RADEON_PP_TEX_SIZE_1: |
| 1766 | case RADEON_PP_TEX_SIZE_2: |
| 1767 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1768 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
| 1769 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1770 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1771 | break; |
| 1772 | case RADEON_PP_TEX_PITCH_0: |
| 1773 | case RADEON_PP_TEX_PITCH_1: |
| 1774 | case RADEON_PP_TEX_PITCH_2: |
| 1775 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1776 | track->textures[i].pitch = idx_value + 32; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1777 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1778 | break; |
| 1779 | case RADEON_PP_TXFILTER_0: |
| 1780 | case RADEON_PP_TXFILTER_1: |
| 1781 | case RADEON_PP_TXFILTER_2: |
| 1782 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1783 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1784 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1785 | tmp = (idx_value >> 23) & 0x7; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1786 | if (tmp == 2 || tmp == 6) |
| 1787 | track->textures[i].roundup_w = false; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1788 | tmp = (idx_value >> 27) & 0x7; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1789 | if (tmp == 2 || tmp == 6) |
| 1790 | track->textures[i].roundup_h = false; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1791 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1792 | break; |
| 1793 | case RADEON_PP_TXFORMAT_0: |
| 1794 | case RADEON_PP_TXFORMAT_1: |
| 1795 | case RADEON_PP_TXFORMAT_2: |
| 1796 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1797 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1798 | track->textures[i].use_pitch = 1; |
| 1799 | } else { |
| 1800 | track->textures[i].use_pitch = 0; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1801 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| 1802 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1803 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1804 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1805 | track->textures[i].tex_coord_type = 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1806 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1807 | case RADEON_TXFORMAT_I8: |
| 1808 | case RADEON_TXFORMAT_RGB332: |
| 1809 | case RADEON_TXFORMAT_Y8: |
| 1810 | track->textures[i].cpp = 1; |
Roland Scheidegger | f9da52d | 2010-06-12 12:12:37 -0400 | [diff] [blame] | 1811 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1812 | break; |
| 1813 | case RADEON_TXFORMAT_AI88: |
| 1814 | case RADEON_TXFORMAT_ARGB1555: |
| 1815 | case RADEON_TXFORMAT_RGB565: |
| 1816 | case RADEON_TXFORMAT_ARGB4444: |
| 1817 | case RADEON_TXFORMAT_VYUY422: |
| 1818 | case RADEON_TXFORMAT_YVYU422: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1819 | case RADEON_TXFORMAT_SHADOW16: |
| 1820 | case RADEON_TXFORMAT_LDUDV655: |
| 1821 | case RADEON_TXFORMAT_DUDV88: |
| 1822 | track->textures[i].cpp = 2; |
Roland Scheidegger | f9da52d | 2010-06-12 12:12:37 -0400 | [diff] [blame] | 1823 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1824 | break; |
| 1825 | case RADEON_TXFORMAT_ARGB8888: |
| 1826 | case RADEON_TXFORMAT_RGBA8888: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1827 | case RADEON_TXFORMAT_SHADOW32: |
| 1828 | case RADEON_TXFORMAT_LDUDUV8888: |
| 1829 | track->textures[i].cpp = 4; |
Roland Scheidegger | f9da52d | 2010-06-12 12:12:37 -0400 | [diff] [blame] | 1830 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1831 | break; |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 1832 | case RADEON_TXFORMAT_DXT1: |
| 1833 | track->textures[i].cpp = 1; |
| 1834 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
| 1835 | break; |
| 1836 | case RADEON_TXFORMAT_DXT23: |
| 1837 | case RADEON_TXFORMAT_DXT45: |
| 1838 | track->textures[i].cpp = 1; |
| 1839 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
| 1840 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1841 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1842 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
| 1843 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1844 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1845 | break; |
| 1846 | case RADEON_PP_CUBIC_FACES_0: |
| 1847 | case RADEON_PP_CUBIC_FACES_1: |
| 1848 | case RADEON_PP_CUBIC_FACES_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1849 | tmp = idx_value; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1850 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
| 1851 | for (face = 0; face < 4; face++) { |
| 1852 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
| 1853 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
| 1854 | } |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 1855 | track->tex_dirty = true; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1856 | break; |
| 1857 | default: |
| 1858 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
| 1859 | reg, idx); |
| 1860 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1861 | } |
| 1862 | return 0; |
| 1863 | } |
| 1864 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1865 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 1866 | struct radeon_cs_packet *pkt, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1867 | struct radeon_bo *robj) |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1868 | { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1869 | unsigned idx; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1870 | u32 value; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1871 | idx = pkt->idx + 1; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1872 | value = radeon_get_ib_value(p, idx + 2); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1873 | if ((value + 1) > radeon_bo_size(robj)) { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1874 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
| 1875 | "(need %u have %lu) !\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1876 | value + 1, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1877 | radeon_bo_size(robj)); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1878 | return -EINVAL; |
| 1879 | } |
| 1880 | return 0; |
| 1881 | } |
| 1882 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1883 | static int r100_packet3_check(struct radeon_cs_parser *p, |
| 1884 | struct radeon_cs_packet *pkt) |
| 1885 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1886 | struct radeon_cs_reloc *reloc; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1887 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1888 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1889 | volatile uint32_t *ib; |
| 1890 | int r; |
| 1891 | |
| 1892 | ib = p->ib->ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1893 | idx = pkt->idx + 1; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1894 | track = (struct r100_cs_track *)p->track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1895 | switch (pkt->opcode) { |
| 1896 | case PACKET3_3D_LOAD_VBPNTR: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1897 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
| 1898 | if (r) |
| 1899 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1900 | break; |
| 1901 | case PACKET3_INDX_BUFFER: |
| 1902 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1903 | if (r) { |
| 1904 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| 1905 | r100_cs_dump_packet(p, pkt); |
| 1906 | return r; |
| 1907 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1908 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1909 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
| 1910 | if (r) { |
| 1911 | return r; |
| 1912 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1913 | break; |
| 1914 | case 0x23: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1915 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
| 1916 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1917 | if (r) { |
| 1918 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| 1919 | r100_cs_dump_packet(p, pkt); |
| 1920 | return r; |
| 1921 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1922 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1923 | track->num_arrays = 1; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1924 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1925 | |
| 1926 | track->arrays[0].robj = reloc->robj; |
| 1927 | track->arrays[0].esize = track->vtx_size; |
| 1928 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1929 | track->max_indx = radeon_get_ib_value(p, idx+1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1930 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1931 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1932 | track->immd_dwords = pkt->count - 1; |
| 1933 | r = r100_cs_track_check(p->rdev, track); |
| 1934 | if (r) |
| 1935 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1936 | break; |
| 1937 | case PACKET3_3D_DRAW_IMMD: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1938 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1939 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| 1940 | return -EINVAL; |
| 1941 | } |
Alex Deucher | cf57fc7 | 2010-01-18 20:20:07 -0500 | [diff] [blame] | 1942 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1943 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1944 | track->immd_dwords = pkt->count - 1; |
| 1945 | r = r100_cs_track_check(p->rdev, track); |
| 1946 | if (r) |
| 1947 | return r; |
| 1948 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1949 | /* triggers drawing using in-packet vertex data */ |
| 1950 | case PACKET3_3D_DRAW_IMMD_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1951 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1952 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| 1953 | return -EINVAL; |
| 1954 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1955 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1956 | track->immd_dwords = pkt->count; |
| 1957 | r = r100_cs_track_check(p->rdev, track); |
| 1958 | if (r) |
| 1959 | return r; |
| 1960 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1961 | /* triggers drawing using in-packet vertex data */ |
| 1962 | case PACKET3_3D_DRAW_VBUF_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1963 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1964 | r = r100_cs_track_check(p->rdev, track); |
| 1965 | if (r) |
| 1966 | return r; |
| 1967 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1968 | /* triggers drawing of vertex buffers setup elsewhere */ |
| 1969 | case PACKET3_3D_DRAW_INDX_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1970 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1971 | r = r100_cs_track_check(p->rdev, track); |
| 1972 | if (r) |
| 1973 | return r; |
| 1974 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1975 | /* triggers drawing using indices to vertex buffer */ |
| 1976 | case PACKET3_3D_DRAW_VBUF: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1977 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1978 | r = r100_cs_track_check(p->rdev, track); |
| 1979 | if (r) |
| 1980 | return r; |
| 1981 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1982 | /* triggers drawing of vertex buffers setup elsewhere */ |
| 1983 | case PACKET3_3D_DRAW_INDX: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1984 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1985 | r = r100_cs_track_check(p->rdev, track); |
| 1986 | if (r) |
| 1987 | return r; |
| 1988 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1989 | /* triggers drawing using indices to vertex buffer */ |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 1990 | case PACKET3_3D_CLEAR_HIZ: |
| 1991 | case PACKET3_3D_CLEAR_ZMASK: |
| 1992 | if (p->rdev->hyperz_filp != p->filp) |
| 1993 | return -EINVAL; |
| 1994 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1995 | case PACKET3_NOP: |
| 1996 | break; |
| 1997 | default: |
| 1998 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
| 1999 | return -EINVAL; |
| 2000 | } |
| 2001 | return 0; |
| 2002 | } |
| 2003 | |
| 2004 | int r100_cs_parse(struct radeon_cs_parser *p) |
| 2005 | { |
| 2006 | struct radeon_cs_packet pkt; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 2007 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2008 | int r; |
| 2009 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 2010 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
| 2011 | r100_cs_track_clear(p->rdev, track); |
| 2012 | p->track = track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2013 | do { |
| 2014 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
| 2015 | if (r) { |
| 2016 | return r; |
| 2017 | } |
| 2018 | p->idx += pkt.count + 2; |
| 2019 | switch (pkt.type) { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2020 | case PACKET_TYPE0: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2021 | if (p->rdev->family >= CHIP_R200) |
| 2022 | r = r100_cs_parse_packet0(p, &pkt, |
| 2023 | p->rdev->config.r100.reg_safe_bm, |
| 2024 | p->rdev->config.r100.reg_safe_bm_size, |
| 2025 | &r200_packet0_check); |
| 2026 | else |
| 2027 | r = r100_cs_parse_packet0(p, &pkt, |
| 2028 | p->rdev->config.r100.reg_safe_bm, |
| 2029 | p->rdev->config.r100.reg_safe_bm_size, |
| 2030 | &r100_packet0_check); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2031 | break; |
| 2032 | case PACKET_TYPE2: |
| 2033 | break; |
| 2034 | case PACKET_TYPE3: |
| 2035 | r = r100_packet3_check(p, &pkt); |
| 2036 | break; |
| 2037 | default: |
| 2038 | DRM_ERROR("Unknown packet type %d !\n", |
| 2039 | pkt.type); |
| 2040 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2041 | } |
| 2042 | if (r) { |
| 2043 | return r; |
| 2044 | } |
| 2045 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
| 2046 | return 0; |
| 2047 | } |
| 2048 | |
| 2049 | |
| 2050 | /* |
| 2051 | * Global GPU functions |
| 2052 | */ |
| 2053 | void r100_errata(struct radeon_device *rdev) |
| 2054 | { |
| 2055 | rdev->pll_errata = 0; |
| 2056 | |
| 2057 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
| 2058 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
| 2059 | } |
| 2060 | |
| 2061 | if (rdev->family == CHIP_RV100 || |
| 2062 | rdev->family == CHIP_RS100 || |
| 2063 | rdev->family == CHIP_RS200) { |
| 2064 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
| 2065 | } |
| 2066 | } |
| 2067 | |
| 2068 | /* Wait for vertical sync on primary CRTC */ |
| 2069 | void r100_gpu_wait_for_vsync(struct radeon_device *rdev) |
| 2070 | { |
| 2071 | uint32_t crtc_gen_cntl, tmp; |
| 2072 | int i; |
| 2073 | |
| 2074 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| 2075 | if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || |
| 2076 | !(crtc_gen_cntl & RADEON_CRTC_EN)) { |
| 2077 | return; |
| 2078 | } |
| 2079 | /* Clear the CRTC_VBLANK_SAVE bit */ |
| 2080 | WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); |
| 2081 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2082 | tmp = RREG32(RADEON_CRTC_STATUS); |
| 2083 | if (tmp & RADEON_CRTC_VBLANK_SAVE) { |
| 2084 | return; |
| 2085 | } |
| 2086 | DRM_UDELAY(1); |
| 2087 | } |
| 2088 | } |
| 2089 | |
| 2090 | /* Wait for vertical sync on secondary CRTC */ |
| 2091 | void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) |
| 2092 | { |
| 2093 | uint32_t crtc2_gen_cntl, tmp; |
| 2094 | int i; |
| 2095 | |
| 2096 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 2097 | if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || |
| 2098 | !(crtc2_gen_cntl & RADEON_CRTC2_EN)) |
| 2099 | return; |
| 2100 | |
| 2101 | /* Clear the CRTC_VBLANK_SAVE bit */ |
| 2102 | WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); |
| 2103 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2104 | tmp = RREG32(RADEON_CRTC2_STATUS); |
| 2105 | if (tmp & RADEON_CRTC2_VBLANK_SAVE) { |
| 2106 | return; |
| 2107 | } |
| 2108 | DRM_UDELAY(1); |
| 2109 | } |
| 2110 | } |
| 2111 | |
| 2112 | int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
| 2113 | { |
| 2114 | unsigned i; |
| 2115 | uint32_t tmp; |
| 2116 | |
| 2117 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2118 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
| 2119 | if (tmp >= n) { |
| 2120 | return 0; |
| 2121 | } |
| 2122 | DRM_UDELAY(1); |
| 2123 | } |
| 2124 | return -1; |
| 2125 | } |
| 2126 | |
| 2127 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
| 2128 | { |
| 2129 | unsigned i; |
| 2130 | uint32_t tmp; |
| 2131 | |
| 2132 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
| 2133 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
| 2134 | " Bad things might happen.\n"); |
| 2135 | } |
| 2136 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2137 | tmp = RREG32(RADEON_RBBM_STATUS); |
Alex Deucher | 4612dc9 | 2010-02-05 01:58:28 -0500 | [diff] [blame] | 2138 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2139 | return 0; |
| 2140 | } |
| 2141 | DRM_UDELAY(1); |
| 2142 | } |
| 2143 | return -1; |
| 2144 | } |
| 2145 | |
| 2146 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
| 2147 | { |
| 2148 | unsigned i; |
| 2149 | uint32_t tmp; |
| 2150 | |
| 2151 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2152 | /* read MC_STATUS */ |
Alex Deucher | 4612dc9 | 2010-02-05 01:58:28 -0500 | [diff] [blame] | 2153 | tmp = RREG32(RADEON_MC_STATUS); |
| 2154 | if (tmp & RADEON_MC_IDLE) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2155 | return 0; |
| 2156 | } |
| 2157 | DRM_UDELAY(1); |
| 2158 | } |
| 2159 | return -1; |
| 2160 | } |
| 2161 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2162 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2163 | { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 2164 | u32 rbbm_status; |
| 2165 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2166 | |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 2167 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
| 2168 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame^] | 2169 | radeon_ring_lockup_update(ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 2170 | return false; |
| 2171 | } |
| 2172 | /* force CP activities */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2173 | r = radeon_ring_lock(rdev, ring, 2); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 2174 | if (!r) { |
| 2175 | /* PACKET2 NOP */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2176 | radeon_ring_write(ring, 0x80000000); |
| 2177 | radeon_ring_write(ring, 0x80000000); |
| 2178 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 2179 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2180 | ring->rptr = RREG32(ring->rptr_reg); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame^] | 2181 | return radeon_ring_test_lockup(rdev, ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 2182 | } |
| 2183 | |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2184 | void r100_bm_disable(struct radeon_device *rdev) |
| 2185 | { |
| 2186 | u32 tmp; |
| 2187 | |
| 2188 | /* disable bus mastering */ |
| 2189 | tmp = RREG32(R_000030_BUS_CNTL); |
| 2190 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2191 | mdelay(1); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2192 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); |
| 2193 | mdelay(1); |
| 2194 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); |
| 2195 | tmp = RREG32(RADEON_BUS_CNTL); |
| 2196 | mdelay(1); |
Michel Dänzer | 642ce52 | 2012-01-12 16:04:11 +0100 | [diff] [blame] | 2197 | pci_clear_master(rdev->pdev); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2198 | mdelay(1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2199 | } |
| 2200 | |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 2201 | int r100_asic_reset(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2202 | { |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2203 | struct r100_mc_save save; |
| 2204 | u32 status, tmp; |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 2205 | int ret = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2206 | |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2207 | status = RREG32(R_000E40_RBBM_STATUS); |
| 2208 | if (!G_000E40_GUI_ACTIVE(status)) { |
| 2209 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2210 | } |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 2211 | r100_mc_stop(rdev, &save); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2212 | status = RREG32(R_000E40_RBBM_STATUS); |
| 2213 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 2214 | /* stop CP */ |
| 2215 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 2216 | tmp = RREG32(RADEON_CP_RB_CNTL); |
| 2217 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
| 2218 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
| 2219 | WREG32(RADEON_CP_RB_WPTR, 0); |
| 2220 | WREG32(RADEON_CP_RB_CNTL, tmp); |
| 2221 | /* save PCI state */ |
| 2222 | pci_save_state(rdev->pdev); |
| 2223 | /* disable bus mastering */ |
| 2224 | r100_bm_disable(rdev); |
| 2225 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | |
| 2226 | S_0000F0_SOFT_RESET_RE(1) | |
| 2227 | S_0000F0_SOFT_RESET_PP(1) | |
| 2228 | S_0000F0_SOFT_RESET_RB(1)); |
| 2229 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 2230 | mdelay(500); |
| 2231 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 2232 | mdelay(1); |
| 2233 | status = RREG32(R_000E40_RBBM_STATUS); |
| 2234 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2235 | /* reset CP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2236 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
| 2237 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 2238 | mdelay(500); |
| 2239 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 2240 | mdelay(1); |
| 2241 | status = RREG32(R_000E40_RBBM_STATUS); |
| 2242 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 2243 | /* restore PCI & busmastering */ |
| 2244 | pci_restore_state(rdev->pdev); |
| 2245 | r100_enable_bm(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2246 | /* Check if GPU is idle */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2247 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || |
| 2248 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { |
| 2249 | dev_err(rdev->dev, "failed to reset GPU\n"); |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 2250 | ret = -1; |
| 2251 | } else |
| 2252 | dev_info(rdev->dev, "GPU reset succeed\n"); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2253 | r100_mc_resume(rdev, &save); |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 2254 | return ret; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2255 | } |
| 2256 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 2257 | void r100_set_common_regs(struct radeon_device *rdev) |
| 2258 | { |
Alex Deucher | 2739d49 | 2010-02-05 03:34:16 -0500 | [diff] [blame] | 2259 | struct drm_device *dev = rdev->ddev; |
| 2260 | bool force_dac2 = false; |
Dave Airlie | d668046 | 2010-03-31 13:41:35 +1000 | [diff] [blame] | 2261 | u32 tmp; |
Alex Deucher | 2739d49 | 2010-02-05 03:34:16 -0500 | [diff] [blame] | 2262 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 2263 | /* set these so they don't interfere with anything */ |
| 2264 | WREG32(RADEON_OV0_SCALE_CNTL, 0); |
| 2265 | WREG32(RADEON_SUBPIC_CNTL, 0); |
| 2266 | WREG32(RADEON_VIPH_CONTROL, 0); |
| 2267 | WREG32(RADEON_I2C_CNTL_1, 0); |
| 2268 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
| 2269 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
| 2270 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
Alex Deucher | 2739d49 | 2010-02-05 03:34:16 -0500 | [diff] [blame] | 2271 | |
| 2272 | /* always set up dac2 on rn50 and some rv100 as lots |
| 2273 | * of servers seem to wire it up to a VGA port but |
| 2274 | * don't report it in the bios connector |
| 2275 | * table. |
| 2276 | */ |
| 2277 | switch (dev->pdev->device) { |
| 2278 | /* RN50 */ |
| 2279 | case 0x515e: |
| 2280 | case 0x5969: |
| 2281 | force_dac2 = true; |
| 2282 | break; |
| 2283 | /* RV100*/ |
| 2284 | case 0x5159: |
| 2285 | case 0x515a: |
| 2286 | /* DELL triple head servers */ |
| 2287 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && |
| 2288 | ((dev->pdev->subsystem_device == 0x016c) || |
| 2289 | (dev->pdev->subsystem_device == 0x016d) || |
| 2290 | (dev->pdev->subsystem_device == 0x016e) || |
| 2291 | (dev->pdev->subsystem_device == 0x016f) || |
| 2292 | (dev->pdev->subsystem_device == 0x0170) || |
| 2293 | (dev->pdev->subsystem_device == 0x017d) || |
| 2294 | (dev->pdev->subsystem_device == 0x017e) || |
| 2295 | (dev->pdev->subsystem_device == 0x0183) || |
| 2296 | (dev->pdev->subsystem_device == 0x018a) || |
| 2297 | (dev->pdev->subsystem_device == 0x019a))) |
| 2298 | force_dac2 = true; |
| 2299 | break; |
| 2300 | } |
| 2301 | |
| 2302 | if (force_dac2) { |
| 2303 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
| 2304 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 2305 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
| 2306 | |
| 2307 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
| 2308 | enable it, even it's detected. |
| 2309 | */ |
| 2310 | |
| 2311 | /* force it to crtc0 */ |
| 2312 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
| 2313 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
| 2314 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 2315 | |
| 2316 | /* set up the TV DAC */ |
| 2317 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | |
| 2318 | RADEON_TV_DAC_STD_MASK | |
| 2319 | RADEON_TV_DAC_RDACPD | |
| 2320 | RADEON_TV_DAC_GDACPD | |
| 2321 | RADEON_TV_DAC_BDACPD | |
| 2322 | RADEON_TV_DAC_BGADJ_MASK | |
| 2323 | RADEON_TV_DAC_DACADJ_MASK); |
| 2324 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
| 2325 | RADEON_TV_DAC_NHOLD | |
| 2326 | RADEON_TV_DAC_STD_PS2 | |
| 2327 | (0x58 << 16)); |
| 2328 | |
| 2329 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 2330 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 2331 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 2332 | } |
Dave Airlie | d668046 | 2010-03-31 13:41:35 +1000 | [diff] [blame] | 2333 | |
| 2334 | /* switch PM block to ACPI mode */ |
| 2335 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
| 2336 | tmp &= ~RADEON_PM_MODE_SEL; |
| 2337 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
| 2338 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 2339 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2340 | |
| 2341 | /* |
| 2342 | * VRAM info |
| 2343 | */ |
| 2344 | static void r100_vram_get_type(struct radeon_device *rdev) |
| 2345 | { |
| 2346 | uint32_t tmp; |
| 2347 | |
| 2348 | rdev->mc.vram_is_ddr = false; |
| 2349 | if (rdev->flags & RADEON_IS_IGP) |
| 2350 | rdev->mc.vram_is_ddr = true; |
| 2351 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
| 2352 | rdev->mc.vram_is_ddr = true; |
| 2353 | if ((rdev->family == CHIP_RV100) || |
| 2354 | (rdev->family == CHIP_RS100) || |
| 2355 | (rdev->family == CHIP_RS200)) { |
| 2356 | tmp = RREG32(RADEON_MEM_CNTL); |
| 2357 | if (tmp & RV100_HALF_MODE) { |
| 2358 | rdev->mc.vram_width = 32; |
| 2359 | } else { |
| 2360 | rdev->mc.vram_width = 64; |
| 2361 | } |
| 2362 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
| 2363 | rdev->mc.vram_width /= 4; |
| 2364 | rdev->mc.vram_is_ddr = true; |
| 2365 | } |
| 2366 | } else if (rdev->family <= CHIP_RV280) { |
| 2367 | tmp = RREG32(RADEON_MEM_CNTL); |
| 2368 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
| 2369 | rdev->mc.vram_width = 128; |
| 2370 | } else { |
| 2371 | rdev->mc.vram_width = 64; |
| 2372 | } |
| 2373 | } else { |
| 2374 | /* newer IGPs */ |
| 2375 | rdev->mc.vram_width = 128; |
| 2376 | } |
| 2377 | } |
| 2378 | |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2379 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2380 | { |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2381 | u32 aper_size; |
| 2382 | u8 byte; |
| 2383 | |
| 2384 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
| 2385 | |
| 2386 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
| 2387 | * that is has the 2nd generation multifunction PCI interface |
| 2388 | */ |
| 2389 | if (rdev->family == CHIP_RV280 || |
| 2390 | rdev->family >= CHIP_RV350) { |
| 2391 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
| 2392 | ~RADEON_HDP_APER_CNTL); |
| 2393 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); |
| 2394 | return aper_size * 2; |
| 2395 | } |
| 2396 | |
| 2397 | /* Older cards have all sorts of funny issues to deal with. First |
| 2398 | * check if it's a multifunction card by reading the PCI config |
| 2399 | * header type... Limit those to one aperture size |
| 2400 | */ |
| 2401 | pci_read_config_byte(rdev->pdev, 0xe, &byte); |
| 2402 | if (byte & 0x80) { |
| 2403 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); |
| 2404 | DRM_INFO("Limiting VRAM to one aperture\n"); |
| 2405 | return aper_size; |
| 2406 | } |
| 2407 | |
| 2408 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
| 2409 | * have set it up. We don't write this as it's broken on some ASICs but |
| 2410 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
| 2411 | */ |
| 2412 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
| 2413 | return aper_size * 2; |
| 2414 | return aper_size; |
| 2415 | } |
| 2416 | |
| 2417 | void r100_vram_init_sizes(struct radeon_device *rdev) |
| 2418 | { |
| 2419 | u64 config_aper_size; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2420 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2421 | /* work out accessible VRAM */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 2422 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 2423 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 2424 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
| 2425 | /* FIXME we don't use the second aperture yet when we could use it */ |
| 2426 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) |
| 2427 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2428 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2429 | if (rdev->flags & RADEON_IS_IGP) { |
| 2430 | uint32_t tom; |
| 2431 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
| 2432 | tom = RREG32(RADEON_NB_TOM); |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2433 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2434 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| 2435 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2436 | } else { |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2437 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2438 | /* Some production boards of m6 will report 0 |
| 2439 | * if it's 8 MB |
| 2440 | */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2441 | if (rdev->mc.real_vram_size == 0) { |
| 2442 | rdev->mc.real_vram_size = 8192 * 1024; |
| 2443 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2444 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2445 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
| 2446 | * Novell bug 204882 + along with lots of ubuntu ones |
| 2447 | */ |
Alex Deucher | b7d8cce | 2010-10-25 19:44:00 -0400 | [diff] [blame] | 2448 | if (rdev->mc.aper_size > config_aper_size) |
| 2449 | config_aper_size = rdev->mc.aper_size; |
| 2450 | |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2451 | if (config_aper_size > rdev->mc.real_vram_size) |
| 2452 | rdev->mc.mc_vram_size = config_aper_size; |
| 2453 | else |
| 2454 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2455 | } |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2456 | } |
| 2457 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2458 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
| 2459 | { |
| 2460 | uint32_t temp; |
| 2461 | |
| 2462 | temp = RREG32(RADEON_CONFIG_CNTL); |
| 2463 | if (state == false) { |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 2464 | temp &= ~RADEON_CFG_VGA_RAM_EN; |
| 2465 | temp |= RADEON_CFG_VGA_IO_DIS; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2466 | } else { |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 2467 | temp &= ~RADEON_CFG_VGA_IO_DIS; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2468 | } |
| 2469 | WREG32(RADEON_CONFIG_CNTL, temp); |
| 2470 | } |
| 2471 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2472 | void r100_mc_init(struct radeon_device *rdev) |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2473 | { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2474 | u64 base; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2475 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2476 | r100_vram_get_type(rdev); |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2477 | r100_vram_init_sizes(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2478 | base = rdev->mc.aper_base; |
| 2479 | if (rdev->flags & RADEON_IS_IGP) |
| 2480 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
| 2481 | radeon_vram_location(rdev, &rdev->mc, base); |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 2482 | rdev->mc.gtt_base_align = 0; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2483 | if (!(rdev->flags & RADEON_IS_AGP)) |
| 2484 | radeon_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 2485 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2486 | } |
| 2487 | |
| 2488 | |
| 2489 | /* |
| 2490 | * Indirect registers accessor |
| 2491 | */ |
| 2492 | void r100_pll_errata_after_index(struct radeon_device *rdev) |
| 2493 | { |
Alex Deucher | 4ce9198 | 2010-06-30 12:13:55 -0400 | [diff] [blame] | 2494 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { |
| 2495 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
| 2496 | (void)RREG32(RADEON_CRTC_GEN_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2497 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2498 | } |
| 2499 | |
| 2500 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
| 2501 | { |
| 2502 | /* This workarounds is necessary on RV100, RS100 and RS200 chips |
| 2503 | * or the chip could hang on a subsequent access |
| 2504 | */ |
| 2505 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 2506 | mdelay(5); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2507 | } |
| 2508 | |
| 2509 | /* This function is required to workaround a hardware bug in some (all?) |
| 2510 | * revisions of the R300. This workaround should be called after every |
| 2511 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
| 2512 | * may not be correct. |
| 2513 | */ |
| 2514 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
| 2515 | uint32_t save, tmp; |
| 2516 | |
| 2517 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
| 2518 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
| 2519 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
| 2520 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
| 2521 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
| 2522 | } |
| 2523 | } |
| 2524 | |
| 2525 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
| 2526 | { |
| 2527 | uint32_t data; |
| 2528 | |
| 2529 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
| 2530 | r100_pll_errata_after_index(rdev); |
| 2531 | data = RREG32(RADEON_CLOCK_CNTL_DATA); |
| 2532 | r100_pll_errata_after_data(rdev); |
| 2533 | return data; |
| 2534 | } |
| 2535 | |
| 2536 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 2537 | { |
| 2538 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
| 2539 | r100_pll_errata_after_index(rdev); |
| 2540 | WREG32(RADEON_CLOCK_CNTL_DATA, v); |
| 2541 | r100_pll_errata_after_data(rdev); |
| 2542 | } |
| 2543 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 2544 | void r100_set_safe_registers(struct radeon_device *rdev) |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2545 | { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2546 | if (ASIC_IS_RN50(rdev)) { |
| 2547 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
| 2548 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); |
| 2549 | } else if (rdev->family < CHIP_R200) { |
| 2550 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
| 2551 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
| 2552 | } else { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 2553 | r200_set_safe_registers(rdev); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2554 | } |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2555 | } |
| 2556 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2557 | /* |
| 2558 | * Debugfs info |
| 2559 | */ |
| 2560 | #if defined(CONFIG_DEBUG_FS) |
| 2561 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) |
| 2562 | { |
| 2563 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2564 | struct drm_device *dev = node->minor->dev; |
| 2565 | struct radeon_device *rdev = dev->dev_private; |
| 2566 | uint32_t reg, value; |
| 2567 | unsigned i; |
| 2568 | |
| 2569 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
| 2570 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); |
| 2571 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
| 2572 | for (i = 0; i < 64; i++) { |
| 2573 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); |
| 2574 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; |
| 2575 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); |
| 2576 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); |
| 2577 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); |
| 2578 | } |
| 2579 | return 0; |
| 2580 | } |
| 2581 | |
| 2582 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
| 2583 | { |
| 2584 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2585 | struct drm_device *dev = node->minor->dev; |
| 2586 | struct radeon_device *rdev = dev->dev_private; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2587 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2588 | uint32_t rdp, wdp; |
| 2589 | unsigned count, i, j; |
| 2590 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2591 | radeon_ring_free_size(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2592 | rdp = RREG32(RADEON_CP_RB_RPTR); |
| 2593 | wdp = RREG32(RADEON_CP_RB_WPTR); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2594 | count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2595 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
| 2596 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
| 2597 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2598 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2599 | seq_printf(m, "%u dwords in ring\n", count); |
| 2600 | for (j = 0; j <= count; j++) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2601 | i = (rdp + j) & ring->ptr_mask; |
| 2602 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2603 | } |
| 2604 | return 0; |
| 2605 | } |
| 2606 | |
| 2607 | |
| 2608 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
| 2609 | { |
| 2610 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2611 | struct drm_device *dev = node->minor->dev; |
| 2612 | struct radeon_device *rdev = dev->dev_private; |
| 2613 | uint32_t csq_stat, csq2_stat, tmp; |
| 2614 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; |
| 2615 | unsigned i; |
| 2616 | |
| 2617 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
| 2618 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); |
| 2619 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); |
| 2620 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); |
| 2621 | r_rptr = (csq_stat >> 0) & 0x3ff; |
| 2622 | r_wptr = (csq_stat >> 10) & 0x3ff; |
| 2623 | ib1_rptr = (csq_stat >> 20) & 0x3ff; |
| 2624 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; |
| 2625 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; |
| 2626 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; |
| 2627 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); |
| 2628 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); |
| 2629 | seq_printf(m, "Ring rptr %u\n", r_rptr); |
| 2630 | seq_printf(m, "Ring wptr %u\n", r_wptr); |
| 2631 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); |
| 2632 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); |
| 2633 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); |
| 2634 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); |
| 2635 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms |
| 2636 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ |
| 2637 | seq_printf(m, "Ring fifo:\n"); |
| 2638 | for (i = 0; i < 256; i++) { |
| 2639 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
| 2640 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
| 2641 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); |
| 2642 | } |
| 2643 | seq_printf(m, "Indirect1 fifo:\n"); |
| 2644 | for (i = 256; i <= 512; i++) { |
| 2645 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
| 2646 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
| 2647 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); |
| 2648 | } |
| 2649 | seq_printf(m, "Indirect2 fifo:\n"); |
| 2650 | for (i = 640; i < ib1_wptr; i++) { |
| 2651 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
| 2652 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
| 2653 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); |
| 2654 | } |
| 2655 | return 0; |
| 2656 | } |
| 2657 | |
| 2658 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) |
| 2659 | { |
| 2660 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2661 | struct drm_device *dev = node->minor->dev; |
| 2662 | struct radeon_device *rdev = dev->dev_private; |
| 2663 | uint32_t tmp; |
| 2664 | |
| 2665 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
| 2666 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); |
| 2667 | tmp = RREG32(RADEON_MC_FB_LOCATION); |
| 2668 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); |
| 2669 | tmp = RREG32(RADEON_BUS_CNTL); |
| 2670 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
| 2671 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
| 2672 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
| 2673 | tmp = RREG32(RADEON_AGP_BASE); |
| 2674 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
| 2675 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
| 2676 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
| 2677 | tmp = RREG32(0x01D0); |
| 2678 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); |
| 2679 | tmp = RREG32(RADEON_AIC_LO_ADDR); |
| 2680 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); |
| 2681 | tmp = RREG32(RADEON_AIC_HI_ADDR); |
| 2682 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); |
| 2683 | tmp = RREG32(0x01E4); |
| 2684 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); |
| 2685 | return 0; |
| 2686 | } |
| 2687 | |
| 2688 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
| 2689 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, |
| 2690 | }; |
| 2691 | |
| 2692 | static struct drm_info_list r100_debugfs_cp_list[] = { |
| 2693 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, |
| 2694 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, |
| 2695 | }; |
| 2696 | |
| 2697 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
| 2698 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, |
| 2699 | }; |
| 2700 | #endif |
| 2701 | |
| 2702 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
| 2703 | { |
| 2704 | #if defined(CONFIG_DEBUG_FS) |
| 2705 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); |
| 2706 | #else |
| 2707 | return 0; |
| 2708 | #endif |
| 2709 | } |
| 2710 | |
| 2711 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
| 2712 | { |
| 2713 | #if defined(CONFIG_DEBUG_FS) |
| 2714 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); |
| 2715 | #else |
| 2716 | return 0; |
| 2717 | #endif |
| 2718 | } |
| 2719 | |
| 2720 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
| 2721 | { |
| 2722 | #if defined(CONFIG_DEBUG_FS) |
| 2723 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); |
| 2724 | #else |
| 2725 | return 0; |
| 2726 | #endif |
| 2727 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2728 | |
| 2729 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 2730 | uint32_t tiling_flags, uint32_t pitch, |
| 2731 | uint32_t offset, uint32_t obj_size) |
| 2732 | { |
| 2733 | int surf_index = reg * 16; |
| 2734 | int flags = 0; |
| 2735 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2736 | if (rdev->family <= CHIP_RS200) { |
| 2737 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
| 2738 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
| 2739 | flags |= RADEON_SURF_TILE_COLOR_BOTH; |
| 2740 | if (tiling_flags & RADEON_TILING_MACRO) |
| 2741 | flags |= RADEON_SURF_TILE_COLOR_MACRO; |
| 2742 | } else if (rdev->family <= CHIP_RV280) { |
| 2743 | if (tiling_flags & (RADEON_TILING_MACRO)) |
| 2744 | flags |= R200_SURF_TILE_COLOR_MACRO; |
| 2745 | if (tiling_flags & RADEON_TILING_MICRO) |
| 2746 | flags |= R200_SURF_TILE_COLOR_MICRO; |
| 2747 | } else { |
| 2748 | if (tiling_flags & RADEON_TILING_MACRO) |
| 2749 | flags |= R300_SURF_TILE_MACRO; |
| 2750 | if (tiling_flags & RADEON_TILING_MICRO) |
| 2751 | flags |= R300_SURF_TILE_MICRO; |
| 2752 | } |
| 2753 | |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 2754 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
| 2755 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; |
| 2756 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) |
| 2757 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; |
| 2758 | |
Dave Airlie | f5c5f04 | 2010-06-11 14:40:16 +1000 | [diff] [blame] | 2759 | /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ |
| 2760 | if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { |
| 2761 | if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) |
| 2762 | if (ASIC_IS_RN50(rdev)) |
| 2763 | pitch /= 16; |
| 2764 | } |
| 2765 | |
| 2766 | /* r100/r200 divide by 16 */ |
| 2767 | if (rdev->family < CHIP_R300) |
| 2768 | flags |= pitch / 16; |
| 2769 | else |
| 2770 | flags |= pitch / 8; |
| 2771 | |
| 2772 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2773 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2774 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
| 2775 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
| 2776 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
| 2777 | return 0; |
| 2778 | } |
| 2779 | |
| 2780 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
| 2781 | { |
| 2782 | int surf_index = reg * 16; |
| 2783 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); |
| 2784 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2785 | |
| 2786 | void r100_bandwidth_update(struct radeon_device *rdev) |
| 2787 | { |
| 2788 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
| 2789 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
| 2790 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
| 2791 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
| 2792 | fixed20_12 memtcas_ff[8] = { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2793 | dfixed_init(1), |
| 2794 | dfixed_init(2), |
| 2795 | dfixed_init(3), |
| 2796 | dfixed_init(0), |
| 2797 | dfixed_init_half(1), |
| 2798 | dfixed_init_half(2), |
| 2799 | dfixed_init(0), |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2800 | }; |
| 2801 | fixed20_12 memtcas_rs480_ff[8] = { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2802 | dfixed_init(0), |
| 2803 | dfixed_init(1), |
| 2804 | dfixed_init(2), |
| 2805 | dfixed_init(3), |
| 2806 | dfixed_init(0), |
| 2807 | dfixed_init_half(1), |
| 2808 | dfixed_init_half(2), |
| 2809 | dfixed_init_half(3), |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2810 | }; |
| 2811 | fixed20_12 memtcas2_ff[8] = { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2812 | dfixed_init(0), |
| 2813 | dfixed_init(1), |
| 2814 | dfixed_init(2), |
| 2815 | dfixed_init(3), |
| 2816 | dfixed_init(4), |
| 2817 | dfixed_init(5), |
| 2818 | dfixed_init(6), |
| 2819 | dfixed_init(7), |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2820 | }; |
| 2821 | fixed20_12 memtrbs[8] = { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2822 | dfixed_init(1), |
| 2823 | dfixed_init_half(1), |
| 2824 | dfixed_init(2), |
| 2825 | dfixed_init_half(2), |
| 2826 | dfixed_init(3), |
| 2827 | dfixed_init_half(3), |
| 2828 | dfixed_init(4), |
| 2829 | dfixed_init_half(4) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2830 | }; |
| 2831 | fixed20_12 memtrbs_r4xx[8] = { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2832 | dfixed_init(4), |
| 2833 | dfixed_init(5), |
| 2834 | dfixed_init(6), |
| 2835 | dfixed_init(7), |
| 2836 | dfixed_init(8), |
| 2837 | dfixed_init(9), |
| 2838 | dfixed_init(10), |
| 2839 | dfixed_init(11) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2840 | }; |
| 2841 | fixed20_12 min_mem_eff; |
| 2842 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
| 2843 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
| 2844 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
| 2845 | disp_drain_rate2, read_return_rate; |
| 2846 | fixed20_12 time_disp1_drop_priority; |
| 2847 | int c; |
| 2848 | int cur_size = 16; /* in octawords */ |
| 2849 | int critical_point = 0, critical_point2; |
| 2850 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
| 2851 | int stop_req, max_stop_req; |
| 2852 | struct drm_display_mode *mode1 = NULL; |
| 2853 | struct drm_display_mode *mode2 = NULL; |
| 2854 | uint32_t pixel_bytes1 = 0; |
| 2855 | uint32_t pixel_bytes2 = 0; |
| 2856 | |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 2857 | radeon_update_display_priority(rdev); |
| 2858 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2859 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
| 2860 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
| 2861 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; |
| 2862 | } |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 2863 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 2864 | if (rdev->mode_info.crtcs[1]->base.enabled) { |
| 2865 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
| 2866 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; |
| 2867 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2868 | } |
| 2869 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2870 | min_mem_eff.full = dfixed_const_8(0); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2871 | /* get modes */ |
| 2872 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
| 2873 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
| 2874 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
| 2875 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
| 2876 | /* check crtc enables */ |
| 2877 | if (mode2) |
| 2878 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
| 2879 | if (mode1) |
| 2880 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
| 2881 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
| 2882 | } |
| 2883 | |
| 2884 | /* |
| 2885 | * determine is there is enough bw for current mode |
| 2886 | */ |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 2887 | sclk_ff = rdev->pm.sclk; |
| 2888 | mclk_ff = rdev->pm.mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2889 | |
| 2890 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2891 | temp_ff.full = dfixed_const(temp); |
| 2892 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2893 | |
| 2894 | pix_clk.full = 0; |
| 2895 | pix_clk2.full = 0; |
| 2896 | peak_disp_bw.full = 0; |
| 2897 | if (mode1) { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2898 | temp_ff.full = dfixed_const(1000); |
| 2899 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ |
| 2900 | pix_clk.full = dfixed_div(pix_clk, temp_ff); |
| 2901 | temp_ff.full = dfixed_const(pixel_bytes1); |
| 2902 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2903 | } |
| 2904 | if (mode2) { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2905 | temp_ff.full = dfixed_const(1000); |
| 2906 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ |
| 2907 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); |
| 2908 | temp_ff.full = dfixed_const(pixel_bytes2); |
| 2909 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2910 | } |
| 2911 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2912 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2913 | if (peak_disp_bw.full >= mem_bw.full) { |
| 2914 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
| 2915 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
| 2916 | } |
| 2917 | |
| 2918 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
| 2919 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
| 2920 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
| 2921 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
| 2922 | mem_trp = ((temp & 0x3)) + 1; |
| 2923 | mem_tras = ((temp & 0x70) >> 4) + 1; |
| 2924 | } else if (rdev->family == CHIP_R300 || |
| 2925 | rdev->family == CHIP_R350) { /* r300, r350 */ |
| 2926 | mem_trcd = (temp & 0x7) + 1; |
| 2927 | mem_trp = ((temp >> 8) & 0x7) + 1; |
| 2928 | mem_tras = ((temp >> 11) & 0xf) + 4; |
| 2929 | } else if (rdev->family == CHIP_RV350 || |
| 2930 | rdev->family <= CHIP_RV380) { |
| 2931 | /* rv3x0 */ |
| 2932 | mem_trcd = (temp & 0x7) + 3; |
| 2933 | mem_trp = ((temp >> 8) & 0x7) + 3; |
| 2934 | mem_tras = ((temp >> 11) & 0xf) + 6; |
| 2935 | } else if (rdev->family == CHIP_R420 || |
| 2936 | rdev->family == CHIP_R423 || |
| 2937 | rdev->family == CHIP_RV410) { |
| 2938 | /* r4xx */ |
| 2939 | mem_trcd = (temp & 0xf) + 3; |
| 2940 | if (mem_trcd > 15) |
| 2941 | mem_trcd = 15; |
| 2942 | mem_trp = ((temp >> 8) & 0xf) + 3; |
| 2943 | if (mem_trp > 15) |
| 2944 | mem_trp = 15; |
| 2945 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
| 2946 | if (mem_tras > 31) |
| 2947 | mem_tras = 31; |
| 2948 | } else { /* RV200, R200 */ |
| 2949 | mem_trcd = (temp & 0x7) + 1; |
| 2950 | mem_trp = ((temp >> 8) & 0x7) + 1; |
| 2951 | mem_tras = ((temp >> 12) & 0xf) + 4; |
| 2952 | } |
| 2953 | /* convert to FF */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2954 | trcd_ff.full = dfixed_const(mem_trcd); |
| 2955 | trp_ff.full = dfixed_const(mem_trp); |
| 2956 | tras_ff.full = dfixed_const(mem_tras); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2957 | |
| 2958 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
| 2959 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
| 2960 | data = (temp & (7 << 20)) >> 20; |
| 2961 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
| 2962 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
| 2963 | tcas_ff = memtcas_rs480_ff[data]; |
| 2964 | else |
| 2965 | tcas_ff = memtcas_ff[data]; |
| 2966 | } else |
| 2967 | tcas_ff = memtcas2_ff[data]; |
| 2968 | |
| 2969 | if (rdev->family == CHIP_RS400 || |
| 2970 | rdev->family == CHIP_RS480) { |
| 2971 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
| 2972 | data = (temp >> 23) & 0x7; |
| 2973 | if (data < 5) |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 2974 | tcas_ff.full += dfixed_const(data); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2975 | } |
| 2976 | |
| 2977 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
| 2978 | /* on the R300, Tcas is included in Trbs. |
| 2979 | */ |
| 2980 | temp = RREG32(RADEON_MEM_CNTL); |
| 2981 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
| 2982 | if (data == 1) { |
| 2983 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
| 2984 | temp = RREG32(R300_MC_IND_INDEX); |
| 2985 | temp &= ~R300_MC_IND_ADDR_MASK; |
| 2986 | temp |= R300_MC_READ_CNTL_CD_mcind; |
| 2987 | WREG32(R300_MC_IND_INDEX, temp); |
| 2988 | temp = RREG32(R300_MC_IND_DATA); |
| 2989 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
| 2990 | } else { |
| 2991 | temp = RREG32(R300_MC_READ_CNTL_AB); |
| 2992 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
| 2993 | } |
| 2994 | } else { |
| 2995 | temp = RREG32(R300_MC_READ_CNTL_AB); |
| 2996 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
| 2997 | } |
| 2998 | if (rdev->family == CHIP_RV410 || |
| 2999 | rdev->family == CHIP_R420 || |
| 3000 | rdev->family == CHIP_R423) |
| 3001 | trbs_ff = memtrbs_r4xx[data]; |
| 3002 | else |
| 3003 | trbs_ff = memtrbs[data]; |
| 3004 | tcas_ff.full += trbs_ff.full; |
| 3005 | } |
| 3006 | |
| 3007 | sclk_eff_ff.full = sclk_ff.full; |
| 3008 | |
| 3009 | if (rdev->flags & RADEON_IS_AGP) { |
| 3010 | fixed20_12 agpmode_ff; |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3011 | agpmode_ff.full = dfixed_const(radeon_agpmode); |
| 3012 | temp_ff.full = dfixed_const_666(16); |
| 3013 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3014 | } |
| 3015 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
| 3016 | |
| 3017 | if (ASIC_IS_R300(rdev)) { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3018 | sclk_delay_ff.full = dfixed_const(250); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3019 | } else { |
| 3020 | if ((rdev->family == CHIP_RV100) || |
| 3021 | rdev->flags & RADEON_IS_IGP) { |
| 3022 | if (rdev->mc.vram_is_ddr) |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3023 | sclk_delay_ff.full = dfixed_const(41); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3024 | else |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3025 | sclk_delay_ff.full = dfixed_const(33); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3026 | } else { |
| 3027 | if (rdev->mc.vram_width == 128) |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3028 | sclk_delay_ff.full = dfixed_const(57); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3029 | else |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3030 | sclk_delay_ff.full = dfixed_const(41); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3031 | } |
| 3032 | } |
| 3033 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3034 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3035 | |
| 3036 | if (rdev->mc.vram_is_ddr) { |
| 3037 | if (rdev->mc.vram_width == 32) { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3038 | k1.full = dfixed_const(40); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3039 | c = 3; |
| 3040 | } else { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3041 | k1.full = dfixed_const(20); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3042 | c = 1; |
| 3043 | } |
| 3044 | } else { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3045 | k1.full = dfixed_const(40); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3046 | c = 3; |
| 3047 | } |
| 3048 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3049 | temp_ff.full = dfixed_const(2); |
| 3050 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); |
| 3051 | temp_ff.full = dfixed_const(c); |
| 3052 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); |
| 3053 | temp_ff.full = dfixed_const(4); |
| 3054 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); |
| 3055 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3056 | mc_latency_mclk.full += k1.full; |
| 3057 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3058 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
| 3059 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3060 | |
| 3061 | /* |
| 3062 | HW cursor time assuming worst case of full size colour cursor. |
| 3063 | */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3064 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3065 | temp_ff.full += trcd_ff.full; |
| 3066 | if (temp_ff.full < tras_ff.full) |
| 3067 | temp_ff.full = tras_ff.full; |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3068 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3069 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3070 | temp_ff.full = dfixed_const(cur_size); |
| 3071 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3072 | /* |
| 3073 | Find the total latency for the display data. |
| 3074 | */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3075 | disp_latency_overhead.full = dfixed_const(8); |
| 3076 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3077 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
| 3078 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
| 3079 | |
| 3080 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
| 3081 | disp_latency.full = mc_latency_mclk.full; |
| 3082 | else |
| 3083 | disp_latency.full = mc_latency_sclk.full; |
| 3084 | |
| 3085 | /* setup Max GRPH_STOP_REQ default value */ |
| 3086 | if (ASIC_IS_RV100(rdev)) |
| 3087 | max_stop_req = 0x5c; |
| 3088 | else |
| 3089 | max_stop_req = 0x7c; |
| 3090 | |
| 3091 | if (mode1) { |
| 3092 | /* CRTC1 |
| 3093 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
| 3094 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
| 3095 | */ |
| 3096 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
| 3097 | |
| 3098 | if (stop_req > max_stop_req) |
| 3099 | stop_req = max_stop_req; |
| 3100 | |
| 3101 | /* |
| 3102 | Find the drain rate of the display buffer. |
| 3103 | */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3104 | temp_ff.full = dfixed_const((16/pixel_bytes1)); |
| 3105 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3106 | |
| 3107 | /* |
| 3108 | Find the critical point of the display buffer. |
| 3109 | */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3110 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); |
| 3111 | crit_point_ff.full += dfixed_const_half(0); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3112 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3113 | critical_point = dfixed_trunc(crit_point_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3114 | |
| 3115 | if (rdev->disp_priority == 2) { |
| 3116 | critical_point = 0; |
| 3117 | } |
| 3118 | |
| 3119 | /* |
| 3120 | The critical point should never be above max_stop_req-4. Setting |
| 3121 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
| 3122 | */ |
| 3123 | if (max_stop_req - critical_point < 4) |
| 3124 | critical_point = 0; |
| 3125 | |
| 3126 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
| 3127 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
| 3128 | critical_point = 0x10; |
| 3129 | } |
| 3130 | |
| 3131 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
| 3132 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
| 3133 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
| 3134 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
| 3135 | if ((rdev->family == CHIP_R350) && |
| 3136 | (stop_req > 0x15)) { |
| 3137 | stop_req -= 0x10; |
| 3138 | } |
| 3139 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
| 3140 | temp |= RADEON_GRPH_BUFFER_SIZE; |
| 3141 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
| 3142 | RADEON_GRPH_CRITICAL_AT_SOF | |
| 3143 | RADEON_GRPH_STOP_CNTL); |
| 3144 | /* |
| 3145 | Write the result into the register. |
| 3146 | */ |
| 3147 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
| 3148 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
| 3149 | |
| 3150 | #if 0 |
| 3151 | if ((rdev->family == CHIP_RS400) || |
| 3152 | (rdev->family == CHIP_RS480)) { |
| 3153 | /* attempt to program RS400 disp regs correctly ??? */ |
| 3154 | temp = RREG32(RS400_DISP1_REG_CNTL); |
| 3155 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
| 3156 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
| 3157 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
| 3158 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
| 3159 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
| 3160 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
| 3161 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
| 3162 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
| 3163 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
| 3164 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
| 3165 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
| 3166 | } |
| 3167 | #endif |
| 3168 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3169 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3170 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
| 3171 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
| 3172 | } |
| 3173 | |
| 3174 | if (mode2) { |
| 3175 | u32 grph2_cntl; |
| 3176 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
| 3177 | |
| 3178 | if (stop_req > max_stop_req) |
| 3179 | stop_req = max_stop_req; |
| 3180 | |
| 3181 | /* |
| 3182 | Find the drain rate of the display buffer. |
| 3183 | */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3184 | temp_ff.full = dfixed_const((16/pixel_bytes2)); |
| 3185 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3186 | |
| 3187 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
| 3188 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
| 3189 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
| 3190 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
| 3191 | if ((rdev->family == CHIP_R350) && |
| 3192 | (stop_req > 0x15)) { |
| 3193 | stop_req -= 0x10; |
| 3194 | } |
| 3195 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
| 3196 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
| 3197 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
| 3198 | RADEON_GRPH_CRITICAL_AT_SOF | |
| 3199 | RADEON_GRPH_STOP_CNTL); |
| 3200 | |
| 3201 | if ((rdev->family == CHIP_RS100) || |
| 3202 | (rdev->family == CHIP_RS200)) |
| 3203 | critical_point2 = 0; |
| 3204 | else { |
| 3205 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3206 | temp_ff.full = dfixed_const(temp); |
| 3207 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3208 | if (sclk_ff.full < temp_ff.full) |
| 3209 | temp_ff.full = sclk_ff.full; |
| 3210 | |
| 3211 | read_return_rate.full = temp_ff.full; |
| 3212 | |
| 3213 | if (mode1) { |
| 3214 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3215 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3216 | } else { |
| 3217 | time_disp1_drop_priority.full = 0; |
| 3218 | } |
| 3219 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3220 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); |
| 3221 | crit_point_ff.full += dfixed_const_half(0); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3222 | |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 3223 | critical_point2 = dfixed_trunc(crit_point_ff); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3224 | |
| 3225 | if (rdev->disp_priority == 2) { |
| 3226 | critical_point2 = 0; |
| 3227 | } |
| 3228 | |
| 3229 | if (max_stop_req - critical_point2 < 4) |
| 3230 | critical_point2 = 0; |
| 3231 | |
| 3232 | } |
| 3233 | |
| 3234 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
| 3235 | /* some R300 cards have problem with this set to 0 */ |
| 3236 | critical_point2 = 0x10; |
| 3237 | } |
| 3238 | |
| 3239 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
| 3240 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
| 3241 | |
| 3242 | if ((rdev->family == CHIP_RS400) || |
| 3243 | (rdev->family == CHIP_RS480)) { |
| 3244 | #if 0 |
| 3245 | /* attempt to program RS400 disp2 regs correctly ??? */ |
| 3246 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
| 3247 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
| 3248 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
| 3249 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
| 3250 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
| 3251 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
| 3252 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
| 3253 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
| 3254 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
| 3255 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
| 3256 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
| 3257 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
| 3258 | #endif |
| 3259 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
| 3260 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
| 3261 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
| 3262 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
| 3263 | } |
| 3264 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3265 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 3266 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
| 3267 | } |
| 3268 | } |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3269 | |
Andi Kleen | cbdd450 | 2011-10-13 16:08:46 -0700 | [diff] [blame] | 3270 | static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3271 | { |
| 3272 | DRM_ERROR("pitch %d\n", t->pitch); |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3273 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3274 | DRM_ERROR("width %d\n", t->width); |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3275 | DRM_ERROR("width_11 %d\n", t->width_11); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3276 | DRM_ERROR("height %d\n", t->height); |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3277 | DRM_ERROR("height_11 %d\n", t->height_11); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3278 | DRM_ERROR("num levels %d\n", t->num_levels); |
| 3279 | DRM_ERROR("depth %d\n", t->txdepth); |
| 3280 | DRM_ERROR("bpp %d\n", t->cpp); |
| 3281 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
| 3282 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
| 3283 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3284 | DRM_ERROR("compress format %d\n", t->compress_format); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3285 | } |
| 3286 | |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3287 | static int r100_track_compress_size(int compress_format, int w, int h) |
| 3288 | { |
| 3289 | int block_width, block_height, block_bytes; |
| 3290 | int wblocks, hblocks; |
| 3291 | int min_wblocks; |
| 3292 | int sz; |
| 3293 | |
| 3294 | block_width = 4; |
| 3295 | block_height = 4; |
| 3296 | |
| 3297 | switch (compress_format) { |
| 3298 | case R100_TRACK_COMP_DXT1: |
| 3299 | block_bytes = 8; |
| 3300 | min_wblocks = 4; |
| 3301 | break; |
| 3302 | default: |
| 3303 | case R100_TRACK_COMP_DXT35: |
| 3304 | block_bytes = 16; |
| 3305 | min_wblocks = 2; |
| 3306 | break; |
| 3307 | } |
| 3308 | |
| 3309 | hblocks = (h + block_height - 1) / block_height; |
| 3310 | wblocks = (w + block_width - 1) / block_width; |
| 3311 | if (wblocks < min_wblocks) |
| 3312 | wblocks = min_wblocks; |
| 3313 | sz = wblocks * hblocks * block_bytes; |
| 3314 | return sz; |
| 3315 | } |
| 3316 | |
Roland Scheidegger | 37cf6b0 | 2010-06-12 13:31:11 -0400 | [diff] [blame] | 3317 | static int r100_cs_track_cube(struct radeon_device *rdev, |
| 3318 | struct r100_cs_track *track, unsigned idx) |
| 3319 | { |
| 3320 | unsigned face, w, h; |
| 3321 | struct radeon_bo *cube_robj; |
| 3322 | unsigned long size; |
| 3323 | unsigned compress_format = track->textures[idx].compress_format; |
| 3324 | |
| 3325 | for (face = 0; face < 5; face++) { |
| 3326 | cube_robj = track->textures[idx].cube_info[face].robj; |
| 3327 | w = track->textures[idx].cube_info[face].width; |
| 3328 | h = track->textures[idx].cube_info[face].height; |
| 3329 | |
| 3330 | if (compress_format) { |
| 3331 | size = r100_track_compress_size(compress_format, w, h); |
| 3332 | } else |
| 3333 | size = w * h; |
| 3334 | size *= track->textures[idx].cpp; |
| 3335 | |
| 3336 | size += track->textures[idx].cube_info[face].offset; |
| 3337 | |
| 3338 | if (size > radeon_bo_size(cube_robj)) { |
| 3339 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
| 3340 | size, radeon_bo_size(cube_robj)); |
| 3341 | r100_cs_track_texture_print(&track->textures[idx]); |
| 3342 | return -1; |
| 3343 | } |
| 3344 | } |
| 3345 | return 0; |
| 3346 | } |
| 3347 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3348 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
| 3349 | struct r100_cs_track *track) |
| 3350 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3351 | struct radeon_bo *robj; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3352 | unsigned long size; |
Marek Olšák | b73c5f8 | 2010-04-11 03:18:52 +0200 | [diff] [blame] | 3353 | unsigned u, i, w, h, d; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3354 | int ret; |
| 3355 | |
| 3356 | for (u = 0; u < track->num_texture; u++) { |
| 3357 | if (!track->textures[u].enabled) |
| 3358 | continue; |
Alex Deucher | 43b93fb | 2010-10-27 01:02:35 -0400 | [diff] [blame] | 3359 | if (track->textures[u].lookup_disable) |
| 3360 | continue; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3361 | robj = track->textures[u].robj; |
| 3362 | if (robj == NULL) { |
| 3363 | DRM_ERROR("No texture bound to unit %u\n", u); |
| 3364 | return -EINVAL; |
| 3365 | } |
| 3366 | size = 0; |
| 3367 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
| 3368 | if (track->textures[u].use_pitch) { |
| 3369 | if (rdev->family < CHIP_R300) |
| 3370 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); |
| 3371 | else |
| 3372 | w = track->textures[u].pitch / (1 << i); |
| 3373 | } else { |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3374 | w = track->textures[u].width; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3375 | if (rdev->family >= CHIP_RV515) |
| 3376 | w |= track->textures[u].width_11; |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3377 | w = w / (1 << i); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3378 | if (track->textures[u].roundup_w) |
| 3379 | w = roundup_pow_of_two(w); |
| 3380 | } |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3381 | h = track->textures[u].height; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3382 | if (rdev->family >= CHIP_RV515) |
| 3383 | h |= track->textures[u].height_11; |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3384 | h = h / (1 << i); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3385 | if (track->textures[u].roundup_h) |
| 3386 | h = roundup_pow_of_two(h); |
Marek Olšák | b73c5f8 | 2010-04-11 03:18:52 +0200 | [diff] [blame] | 3387 | if (track->textures[u].tex_coord_type == 1) { |
| 3388 | d = (1 << track->textures[u].txdepth) / (1 << i); |
| 3389 | if (!d) |
| 3390 | d = 1; |
| 3391 | } else { |
| 3392 | d = 1; |
| 3393 | } |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3394 | if (track->textures[u].compress_format) { |
| 3395 | |
Marek Olšák | b73c5f8 | 2010-04-11 03:18:52 +0200 | [diff] [blame] | 3396 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3397 | /* compressed textures are block based */ |
| 3398 | } else |
Marek Olšák | b73c5f8 | 2010-04-11 03:18:52 +0200 | [diff] [blame] | 3399 | size += w * h * d; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3400 | } |
| 3401 | size *= track->textures[u].cpp; |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3402 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3403 | switch (track->textures[u].tex_coord_type) { |
| 3404 | case 0: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3405 | case 1: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3406 | break; |
| 3407 | case 2: |
| 3408 | if (track->separate_cube) { |
| 3409 | ret = r100_cs_track_cube(rdev, track, u); |
| 3410 | if (ret) |
| 3411 | return ret; |
| 3412 | } else |
| 3413 | size *= 6; |
| 3414 | break; |
| 3415 | default: |
| 3416 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
| 3417 | "%u\n", track->textures[u].tex_coord_type, u); |
| 3418 | return -EINVAL; |
| 3419 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3420 | if (size > radeon_bo_size(robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3421 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3422 | "%lu\n", u, size, radeon_bo_size(robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3423 | r100_cs_track_texture_print(&track->textures[u]); |
| 3424 | return -EINVAL; |
| 3425 | } |
| 3426 | } |
| 3427 | return 0; |
| 3428 | } |
| 3429 | |
| 3430 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
| 3431 | { |
| 3432 | unsigned i; |
| 3433 | unsigned long size; |
| 3434 | unsigned prim_walk; |
| 3435 | unsigned nverts; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3436 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3437 | |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3438 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
Marek Olšák | a41ceb1 | 2010-09-12 05:09:13 +0200 | [diff] [blame] | 3439 | !track->blend_read_enable) |
| 3440 | num_cb = 0; |
| 3441 | |
| 3442 | for (i = 0; i < num_cb; i++) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3443 | if (track->cb[i].robj == NULL) { |
| 3444 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
| 3445 | return -EINVAL; |
| 3446 | } |
| 3447 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
| 3448 | size += track->cb[i].offset; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3449 | if (size > radeon_bo_size(track->cb[i].robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3450 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
| 3451 | "(need %lu have %lu) !\n", i, size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3452 | radeon_bo_size(track->cb[i].robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3453 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
| 3454 | i, track->cb[i].pitch, track->cb[i].cpp, |
| 3455 | track->cb[i].offset, track->maxy); |
| 3456 | return -EINVAL; |
| 3457 | } |
| 3458 | } |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3459 | track->cb_dirty = false; |
| 3460 | |
| 3461 | if (track->zb_dirty && track->z_enabled) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3462 | if (track->zb.robj == NULL) { |
| 3463 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
| 3464 | return -EINVAL; |
| 3465 | } |
| 3466 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
| 3467 | size += track->zb.offset; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3468 | if (size > radeon_bo_size(track->zb.robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3469 | DRM_ERROR("[drm] Buffer too small for z buffer " |
| 3470 | "(need %lu have %lu) !\n", size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3471 | radeon_bo_size(track->zb.robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3472 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
| 3473 | track->zb.pitch, track->zb.cpp, |
| 3474 | track->zb.offset, track->maxy); |
| 3475 | return -EINVAL; |
| 3476 | } |
| 3477 | } |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3478 | track->zb_dirty = false; |
| 3479 | |
Marek Olšák | fff1ce4 | 2011-02-14 01:01:10 +0100 | [diff] [blame] | 3480 | if (track->aa_dirty && track->aaresolve) { |
| 3481 | if (track->aa.robj == NULL) { |
| 3482 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); |
| 3483 | return -EINVAL; |
| 3484 | } |
| 3485 | /* I believe the format comes from colorbuffer0. */ |
| 3486 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; |
| 3487 | size += track->aa.offset; |
| 3488 | if (size > radeon_bo_size(track->aa.robj)) { |
| 3489 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " |
| 3490 | "(need %lu have %lu) !\n", i, size, |
| 3491 | radeon_bo_size(track->aa.robj)); |
| 3492 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", |
| 3493 | i, track->aa.pitch, track->cb[0].cpp, |
| 3494 | track->aa.offset, track->maxy); |
| 3495 | return -EINVAL; |
| 3496 | } |
| 3497 | } |
| 3498 | track->aa_dirty = false; |
| 3499 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3500 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
Marek Olšák | cae94b0 | 2010-02-21 21:24:15 +0100 | [diff] [blame] | 3501 | if (track->vap_vf_cntl & (1 << 14)) { |
| 3502 | nverts = track->vap_alt_nverts; |
| 3503 | } else { |
| 3504 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
| 3505 | } |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3506 | switch (prim_walk) { |
| 3507 | case 1: |
| 3508 | for (i = 0; i < track->num_arrays; i++) { |
| 3509 | size = track->arrays[i].esize * track->max_indx * 4; |
| 3510 | if (track->arrays[i].robj == NULL) { |
| 3511 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
| 3512 | "bound\n", prim_walk, i); |
| 3513 | return -EINVAL; |
| 3514 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3515 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
| 3516 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
| 3517 | "need %lu dwords have %lu dwords\n", |
| 3518 | prim_walk, i, size >> 2, |
| 3519 | radeon_bo_size(track->arrays[i].robj) |
| 3520 | >> 2); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3521 | DRM_ERROR("Max indices %u\n", track->max_indx); |
| 3522 | return -EINVAL; |
| 3523 | } |
| 3524 | } |
| 3525 | break; |
| 3526 | case 2: |
| 3527 | for (i = 0; i < track->num_arrays; i++) { |
| 3528 | size = track->arrays[i].esize * (nverts - 1) * 4; |
| 3529 | if (track->arrays[i].robj == NULL) { |
| 3530 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
| 3531 | "bound\n", prim_walk, i); |
| 3532 | return -EINVAL; |
| 3533 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3534 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
| 3535 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
| 3536 | "need %lu dwords have %lu dwords\n", |
| 3537 | prim_walk, i, size >> 2, |
| 3538 | radeon_bo_size(track->arrays[i].robj) |
| 3539 | >> 2); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3540 | return -EINVAL; |
| 3541 | } |
| 3542 | } |
| 3543 | break; |
| 3544 | case 3: |
| 3545 | size = track->vtx_size * nverts; |
| 3546 | if (size != track->immd_dwords) { |
| 3547 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
| 3548 | track->immd_dwords, size); |
| 3549 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
| 3550 | nverts, track->vtx_size); |
| 3551 | return -EINVAL; |
| 3552 | } |
| 3553 | break; |
| 3554 | default: |
| 3555 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
| 3556 | prim_walk); |
| 3557 | return -EINVAL; |
| 3558 | } |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3559 | |
| 3560 | if (track->tex_dirty) { |
| 3561 | track->tex_dirty = false; |
| 3562 | return r100_cs_track_texture_check(rdev, track); |
| 3563 | } |
| 3564 | return 0; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3565 | } |
| 3566 | |
| 3567 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
| 3568 | { |
| 3569 | unsigned i, face; |
| 3570 | |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3571 | track->cb_dirty = true; |
| 3572 | track->zb_dirty = true; |
| 3573 | track->tex_dirty = true; |
Marek Olšák | fff1ce4 | 2011-02-14 01:01:10 +0100 | [diff] [blame] | 3574 | track->aa_dirty = true; |
Marek Olšák | 40b4a75 | 2011-02-12 19:21:35 +0100 | [diff] [blame] | 3575 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3576 | if (rdev->family < CHIP_R300) { |
| 3577 | track->num_cb = 1; |
| 3578 | if (rdev->family <= CHIP_RS200) |
| 3579 | track->num_texture = 3; |
| 3580 | else |
| 3581 | track->num_texture = 6; |
| 3582 | track->maxy = 2048; |
| 3583 | track->separate_cube = 1; |
| 3584 | } else { |
| 3585 | track->num_cb = 4; |
| 3586 | track->num_texture = 16; |
| 3587 | track->maxy = 4096; |
| 3588 | track->separate_cube = 0; |
Dave Airlie | 45e4039 | 2011-02-20 21:57:32 +0000 | [diff] [blame] | 3589 | track->aaresolve = false; |
Marek Olšák | fff1ce4 | 2011-02-14 01:01:10 +0100 | [diff] [blame] | 3590 | track->aa.robj = NULL; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3591 | } |
| 3592 | |
| 3593 | for (i = 0; i < track->num_cb; i++) { |
| 3594 | track->cb[i].robj = NULL; |
| 3595 | track->cb[i].pitch = 8192; |
| 3596 | track->cb[i].cpp = 16; |
| 3597 | track->cb[i].offset = 0; |
| 3598 | } |
| 3599 | track->z_enabled = true; |
| 3600 | track->zb.robj = NULL; |
| 3601 | track->zb.pitch = 8192; |
| 3602 | track->zb.cpp = 4; |
| 3603 | track->zb.offset = 0; |
| 3604 | track->vtx_size = 0x7F; |
| 3605 | track->immd_dwords = 0xFFFFFFFFUL; |
| 3606 | track->num_arrays = 11; |
| 3607 | track->max_indx = 0x00FFFFFFUL; |
| 3608 | for (i = 0; i < track->num_arrays; i++) { |
| 3609 | track->arrays[i].robj = NULL; |
| 3610 | track->arrays[i].esize = 0x7F; |
| 3611 | } |
| 3612 | for (i = 0; i < track->num_texture; i++) { |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3613 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3614 | track->textures[i].pitch = 16536; |
| 3615 | track->textures[i].width = 16536; |
| 3616 | track->textures[i].height = 16536; |
| 3617 | track->textures[i].width_11 = 1 << 11; |
| 3618 | track->textures[i].height_11 = 1 << 11; |
| 3619 | track->textures[i].num_levels = 12; |
| 3620 | if (rdev->family <= CHIP_RS200) { |
| 3621 | track->textures[i].tex_coord_type = 0; |
| 3622 | track->textures[i].txdepth = 0; |
| 3623 | } else { |
| 3624 | track->textures[i].txdepth = 16; |
| 3625 | track->textures[i].tex_coord_type = 1; |
| 3626 | } |
| 3627 | track->textures[i].cpp = 64; |
| 3628 | track->textures[i].robj = NULL; |
| 3629 | /* CS IB emission code makes sure texture unit are disabled */ |
| 3630 | track->textures[i].enabled = false; |
Alex Deucher | 43b93fb | 2010-10-27 01:02:35 -0400 | [diff] [blame] | 3631 | track->textures[i].lookup_disable = false; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3632 | track->textures[i].roundup_w = true; |
| 3633 | track->textures[i].roundup_h = true; |
| 3634 | if (track->separate_cube) |
| 3635 | for (face = 0; face < 5; face++) { |
| 3636 | track->textures[i].cube_info[face].robj = NULL; |
| 3637 | track->textures[i].cube_info[face].width = 16536; |
| 3638 | track->textures[i].cube_info[face].height = 16536; |
| 3639 | track->textures[i].cube_info[face].offset = 0; |
| 3640 | } |
| 3641 | } |
| 3642 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3643 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3644 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3645 | { |
| 3646 | uint32_t scratch; |
| 3647 | uint32_t tmp = 0; |
| 3648 | unsigned i; |
| 3649 | int r; |
| 3650 | |
| 3651 | r = radeon_scratch_get(rdev, &scratch); |
| 3652 | if (r) { |
| 3653 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
| 3654 | return r; |
| 3655 | } |
| 3656 | WREG32(scratch, 0xCAFEDEAD); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3657 | r = radeon_ring_lock(rdev, ring, 2); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3658 | if (r) { |
| 3659 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| 3660 | radeon_scratch_free(rdev, scratch); |
| 3661 | return r; |
| 3662 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3663 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
| 3664 | radeon_ring_write(ring, 0xDEADBEEF); |
| 3665 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3666 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3667 | tmp = RREG32(scratch); |
| 3668 | if (tmp == 0xDEADBEEF) { |
| 3669 | break; |
| 3670 | } |
| 3671 | DRM_UDELAY(1); |
| 3672 | } |
| 3673 | if (i < rdev->usec_timeout) { |
| 3674 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
| 3675 | } else { |
Alex Deucher | 369d7ec | 2011-01-17 18:08:58 +0000 | [diff] [blame] | 3676 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3677 | scratch, tmp); |
| 3678 | r = -EINVAL; |
| 3679 | } |
| 3680 | radeon_scratch_free(rdev, scratch); |
| 3681 | return r; |
| 3682 | } |
| 3683 | |
| 3684 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| 3685 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3686 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 3687 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3688 | radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); |
| 3689 | radeon_ring_write(ring, ib->gpu_addr); |
| 3690 | radeon_ring_write(ring, ib->length_dw); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3691 | } |
| 3692 | |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 3693 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3694 | { |
| 3695 | struct radeon_ib *ib; |
| 3696 | uint32_t scratch; |
| 3697 | uint32_t tmp = 0; |
| 3698 | unsigned i; |
| 3699 | int r; |
| 3700 | |
| 3701 | r = radeon_scratch_get(rdev, &scratch); |
| 3702 | if (r) { |
| 3703 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
| 3704 | return r; |
| 3705 | } |
| 3706 | WREG32(scratch, 0xCAFEDEAD); |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 3707 | r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3708 | if (r) { |
| 3709 | return r; |
| 3710 | } |
| 3711 | ib->ptr[0] = PACKET0(scratch, 0); |
| 3712 | ib->ptr[1] = 0xDEADBEEF; |
| 3713 | ib->ptr[2] = PACKET2(0); |
| 3714 | ib->ptr[3] = PACKET2(0); |
| 3715 | ib->ptr[4] = PACKET2(0); |
| 3716 | ib->ptr[5] = PACKET2(0); |
| 3717 | ib->ptr[6] = PACKET2(0); |
| 3718 | ib->ptr[7] = PACKET2(0); |
| 3719 | ib->length_dw = 8; |
| 3720 | r = radeon_ib_schedule(rdev, ib); |
| 3721 | if (r) { |
| 3722 | radeon_scratch_free(rdev, scratch); |
| 3723 | radeon_ib_free(rdev, &ib); |
| 3724 | return r; |
| 3725 | } |
| 3726 | r = radeon_fence_wait(ib->fence, false); |
| 3727 | if (r) { |
| 3728 | return r; |
| 3729 | } |
| 3730 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3731 | tmp = RREG32(scratch); |
| 3732 | if (tmp == 0xDEADBEEF) { |
| 3733 | break; |
| 3734 | } |
| 3735 | DRM_UDELAY(1); |
| 3736 | } |
| 3737 | if (i < rdev->usec_timeout) { |
| 3738 | DRM_INFO("ib test succeeded in %u usecs\n", i); |
| 3739 | } else { |
Paul Bolle | 62f288c | 2011-02-19 22:34:00 +0100 | [diff] [blame] | 3740 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3741 | scratch, tmp); |
| 3742 | r = -EINVAL; |
| 3743 | } |
| 3744 | radeon_scratch_free(rdev, scratch); |
| 3745 | radeon_ib_free(rdev, &ib); |
| 3746 | return r; |
| 3747 | } |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3748 | |
| 3749 | void r100_ib_fini(struct radeon_device *rdev) |
| 3750 | { |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 3751 | radeon_ib_pool_suspend(rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3752 | radeon_ib_pool_fini(rdev); |
| 3753 | } |
| 3754 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3755 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
| 3756 | { |
| 3757 | /* Shutdown CP we shouldn't need to do that but better be safe than |
| 3758 | * sorry |
| 3759 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3760 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3761 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
| 3762 | |
| 3763 | /* Save few CRTC registers */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3764 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3765 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
| 3766 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
| 3767 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
| 3768 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 3769 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); |
| 3770 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); |
| 3771 | } |
| 3772 | |
| 3773 | /* Disable VGA aperture access */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3774 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3775 | /* Disable cursor, overlay, crtc */ |
| 3776 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
| 3777 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
| 3778 | S_000054_CRTC_DISPLAY_DIS(1)); |
| 3779 | WREG32(R_000050_CRTC_GEN_CNTL, |
| 3780 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | |
| 3781 | S_000050_CRTC_DISP_REQ_EN_B(1)); |
| 3782 | WREG32(R_000420_OV0_SCALE_CNTL, |
| 3783 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); |
| 3784 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); |
| 3785 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 3786 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | |
| 3787 | S_000360_CUR2_LOCK(1)); |
| 3788 | WREG32(R_0003F8_CRTC2_GEN_CNTL, |
| 3789 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | |
| 3790 | S_0003F8_CRTC2_DISPLAY_DIS(1) | |
| 3791 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); |
| 3792 | WREG32(R_000360_CUR2_OFFSET, |
| 3793 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); |
| 3794 | } |
| 3795 | } |
| 3796 | |
| 3797 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) |
| 3798 | { |
| 3799 | /* Update base address for crtc */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 3800 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3801 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 3802 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3803 | } |
| 3804 | /* Restore CRTC registers */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3805 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3806 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
| 3807 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
| 3808 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 3809 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); |
| 3810 | } |
| 3811 | } |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3812 | |
| 3813 | void r100_vga_render_disable(struct radeon_device *rdev) |
| 3814 | { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3815 | u32 tmp; |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3816 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3817 | tmp = RREG8(R_0003C2_GENMO_WT); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3818 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
| 3819 | } |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3820 | |
| 3821 | static void r100_debugfs(struct radeon_device *rdev) |
| 3822 | { |
| 3823 | int r; |
| 3824 | |
| 3825 | r = r100_debugfs_mc_info_init(rdev); |
| 3826 | if (r) |
| 3827 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
| 3828 | } |
| 3829 | |
| 3830 | static void r100_mc_program(struct radeon_device *rdev) |
| 3831 | { |
| 3832 | struct r100_mc_save save; |
| 3833 | |
| 3834 | /* Stops all mc clients */ |
| 3835 | r100_mc_stop(rdev, &save); |
| 3836 | if (rdev->flags & RADEON_IS_AGP) { |
| 3837 | WREG32(R_00014C_MC_AGP_LOCATION, |
| 3838 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
| 3839 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
| 3840 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
| 3841 | if (rdev->family > CHIP_RV200) |
| 3842 | WREG32(R_00015C_AGP_BASE_2, |
| 3843 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
| 3844 | } else { |
| 3845 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
| 3846 | WREG32(R_000170_AGP_BASE, 0); |
| 3847 | if (rdev->family > CHIP_RV200) |
| 3848 | WREG32(R_00015C_AGP_BASE_2, 0); |
| 3849 | } |
| 3850 | /* Wait for mc idle */ |
| 3851 | if (r100_mc_wait_for_idle(rdev)) |
| 3852 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
| 3853 | /* Program MC, should be a 32bits limited address space */ |
| 3854 | WREG32(R_000148_MC_FB_LOCATION, |
| 3855 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| 3856 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| 3857 | r100_mc_resume(rdev, &save); |
| 3858 | } |
| 3859 | |
| 3860 | void r100_clock_startup(struct radeon_device *rdev) |
| 3861 | { |
| 3862 | u32 tmp; |
| 3863 | |
| 3864 | if (radeon_dynclks != -1 && radeon_dynclks) |
| 3865 | radeon_legacy_set_clock_gating(rdev, 1); |
| 3866 | /* We need to force on some of the block */ |
| 3867 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
| 3868 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
| 3869 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
| 3870 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
| 3871 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
| 3872 | } |
| 3873 | |
| 3874 | static int r100_startup(struct radeon_device *rdev) |
| 3875 | { |
| 3876 | int r; |
| 3877 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 3878 | /* set common regs */ |
| 3879 | r100_set_common_regs(rdev); |
| 3880 | /* program mc */ |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3881 | r100_mc_program(rdev); |
| 3882 | /* Resume clock */ |
| 3883 | r100_clock_startup(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3884 | /* Initialize GART (initialize after TTM so we can allocate |
| 3885 | * memory through TTM but finalize after TTM) */ |
Dave Airlie | 17e15b0 | 2009-11-05 15:36:53 +1000 | [diff] [blame] | 3886 | r100_enable_bm(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3887 | if (rdev->flags & RADEON_IS_PCI) { |
| 3888 | r = r100_pci_gart_enable(rdev); |
| 3889 | if (r) |
| 3890 | return r; |
| 3891 | } |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3892 | |
| 3893 | /* allocate wb buffer */ |
| 3894 | r = radeon_wb_init(rdev); |
| 3895 | if (r) |
| 3896 | return r; |
| 3897 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 3898 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 3899 | if (r) { |
| 3900 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 3901 | return r; |
| 3902 | } |
| 3903 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3904 | /* Enable IRQ */ |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3905 | r100_irq_set(rdev); |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 3906 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3907 | /* 1M ring buffer */ |
| 3908 | r = r100_cp_init(rdev, 1024 * 1024); |
| 3909 | if (r) { |
Paul Bolle | ec4f2ac | 2011-01-28 23:32:04 +0100 | [diff] [blame] | 3910 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3911 | return r; |
| 3912 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 3913 | |
| 3914 | r = radeon_ib_pool_start(rdev); |
| 3915 | if (r) |
| 3916 | return r; |
| 3917 | |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 3918 | r = radeon_ib_ring_tests(rdev); |
| 3919 | if (r) |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3920 | return r; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 3921 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3922 | return 0; |
| 3923 | } |
| 3924 | |
| 3925 | int r100_resume(struct radeon_device *rdev) |
| 3926 | { |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 3927 | int r; |
| 3928 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3929 | /* Make sur GART are not working */ |
| 3930 | if (rdev->flags & RADEON_IS_PCI) |
| 3931 | r100_pci_gart_disable(rdev); |
| 3932 | /* Resume clock before doing reset */ |
| 3933 | r100_clock_startup(rdev); |
| 3934 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 3935 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3936 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 3937 | RREG32(R_000E40_RBBM_STATUS), |
| 3938 | RREG32(R_0007C0_CP_STAT)); |
| 3939 | } |
| 3940 | /* post */ |
| 3941 | radeon_combios_asic_init(rdev->ddev); |
| 3942 | /* Resume clock after posting */ |
| 3943 | r100_clock_startup(rdev); |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 3944 | /* Initialize surface registers */ |
| 3945 | radeon_surface_init(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 3946 | |
| 3947 | rdev->accel_working = true; |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 3948 | r = r100_startup(rdev); |
| 3949 | if (r) { |
| 3950 | rdev->accel_working = false; |
| 3951 | } |
| 3952 | return r; |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3953 | } |
| 3954 | |
| 3955 | int r100_suspend(struct radeon_device *rdev) |
| 3956 | { |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 3957 | radeon_ib_pool_suspend(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3958 | r100_cp_disable(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3959 | radeon_wb_disable(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3960 | r100_irq_disable(rdev); |
| 3961 | if (rdev->flags & RADEON_IS_PCI) |
| 3962 | r100_pci_gart_disable(rdev); |
| 3963 | return 0; |
| 3964 | } |
| 3965 | |
| 3966 | void r100_fini(struct radeon_device *rdev) |
| 3967 | { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3968 | r100_cp_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3969 | radeon_wb_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3970 | r100_ib_fini(rdev); |
| 3971 | radeon_gem_fini(rdev); |
| 3972 | if (rdev->flags & RADEON_IS_PCI) |
| 3973 | r100_pci_gart_fini(rdev); |
Jerome Glisse | d0269ed | 2010-01-07 16:08:32 +0100 | [diff] [blame] | 3974 | radeon_agp_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3975 | radeon_irq_kms_fini(rdev); |
| 3976 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3977 | radeon_bo_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3978 | radeon_atombios_fini(rdev); |
| 3979 | kfree(rdev->bios); |
| 3980 | rdev->bios = NULL; |
| 3981 | } |
| 3982 | |
Dave Airlie | 4c712e6 | 2010-07-15 12:13:50 +1000 | [diff] [blame] | 3983 | /* |
| 3984 | * Due to how kexec works, it can leave the hw fully initialised when it |
| 3985 | * boots the new kernel. However doing our init sequence with the CP and |
| 3986 | * WB stuff setup causes GPU hangs on the RN50 at least. So at startup |
| 3987 | * do some quick sanity checks and restore sane values to avoid this |
| 3988 | * problem. |
| 3989 | */ |
| 3990 | void r100_restore_sanity(struct radeon_device *rdev) |
| 3991 | { |
| 3992 | u32 tmp; |
| 3993 | |
| 3994 | tmp = RREG32(RADEON_CP_CSQ_CNTL); |
| 3995 | if (tmp) { |
| 3996 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 3997 | } |
| 3998 | tmp = RREG32(RADEON_CP_RB_CNTL); |
| 3999 | if (tmp) { |
| 4000 | WREG32(RADEON_CP_RB_CNTL, 0); |
| 4001 | } |
| 4002 | tmp = RREG32(RADEON_SCRATCH_UMSK); |
| 4003 | if (tmp) { |
| 4004 | WREG32(RADEON_SCRATCH_UMSK, 0); |
| 4005 | } |
| 4006 | } |
| 4007 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4008 | int r100_init(struct radeon_device *rdev) |
| 4009 | { |
| 4010 | int r; |
| 4011 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4012 | /* Register debugfs file specific to this group of asics */ |
| 4013 | r100_debugfs(rdev); |
| 4014 | /* Disable VGA */ |
| 4015 | r100_vga_render_disable(rdev); |
| 4016 | /* Initialize scratch registers */ |
| 4017 | radeon_scratch_init(rdev); |
| 4018 | /* Initialize surface registers */ |
| 4019 | radeon_surface_init(rdev); |
Dave Airlie | 4c712e6 | 2010-07-15 12:13:50 +1000 | [diff] [blame] | 4020 | /* sanity check some register to avoid hangs like after kexec */ |
| 4021 | r100_restore_sanity(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4022 | /* TODO: disable VGA need to use VGA request */ |
| 4023 | /* BIOS*/ |
| 4024 | if (!radeon_get_bios(rdev)) { |
| 4025 | if (ASIC_IS_AVIVO(rdev)) |
| 4026 | return -EINVAL; |
| 4027 | } |
| 4028 | if (rdev->is_atom_bios) { |
| 4029 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| 4030 | return -EINVAL; |
| 4031 | } else { |
| 4032 | r = radeon_combios_init(rdev); |
| 4033 | if (r) |
| 4034 | return r; |
| 4035 | } |
| 4036 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 4037 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4038 | dev_warn(rdev->dev, |
| 4039 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 4040 | RREG32(R_000E40_RBBM_STATUS), |
| 4041 | RREG32(R_0007C0_CP_STAT)); |
| 4042 | } |
| 4043 | /* check if cards are posted or not */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 4044 | if (radeon_boot_test_post_card(rdev) == false) |
| 4045 | return -EINVAL; |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4046 | /* Set asic errata */ |
| 4047 | r100_errata(rdev); |
| 4048 | /* Initialize clocks */ |
| 4049 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 4050 | /* initialize AGP */ |
| 4051 | if (rdev->flags & RADEON_IS_AGP) { |
| 4052 | r = radeon_agp_init(rdev); |
| 4053 | if (r) { |
| 4054 | radeon_agp_disable(rdev); |
| 4055 | } |
| 4056 | } |
| 4057 | /* initialize VRAM */ |
| 4058 | r100_mc_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4059 | /* Fence driver */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 4060 | r = radeon_fence_driver_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4061 | if (r) |
| 4062 | return r; |
| 4063 | r = radeon_irq_kms_init(rdev); |
| 4064 | if (r) |
| 4065 | return r; |
| 4066 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 4067 | r = radeon_bo_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4068 | if (r) |
| 4069 | return r; |
| 4070 | if (rdev->flags & RADEON_IS_PCI) { |
| 4071 | r = r100_pci_gart_init(rdev); |
| 4072 | if (r) |
| 4073 | return r; |
| 4074 | } |
| 4075 | r100_set_safe_registers(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 4076 | |
| 4077 | r = radeon_ib_pool_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4078 | rdev->accel_working = true; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 4079 | if (r) { |
| 4080 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 4081 | rdev->accel_working = false; |
| 4082 | } |
| 4083 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4084 | r = r100_startup(rdev); |
| 4085 | if (r) { |
| 4086 | /* Somethings want wront with the accel init stop accel */ |
| 4087 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4088 | r100_cp_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 4089 | radeon_wb_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4090 | r100_ib_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 4091 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4092 | if (rdev->flags & RADEON_IS_PCI) |
| 4093 | r100_pci_gart_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 4094 | rdev->accel_working = false; |
| 4095 | } |
| 4096 | return 0; |
| 4097 | } |
Andi Kleen | 6fcbef7 | 2011-10-13 16:08:42 -0700 | [diff] [blame] | 4098 | |
| 4099 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
| 4100 | { |
| 4101 | if (reg < rdev->rmmio_size) |
| 4102 | return readl(((void __iomem *)rdev->rmmio) + reg); |
| 4103 | else { |
| 4104 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 4105 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 4106 | } |
| 4107 | } |
| 4108 | |
| 4109 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 4110 | { |
| 4111 | if (reg < rdev->rmmio_size) |
| 4112 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| 4113 | else { |
| 4114 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 4115 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 4116 | } |
| 4117 | } |
| 4118 | |
| 4119 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
| 4120 | { |
| 4121 | if (reg < rdev->rio_mem_size) |
| 4122 | return ioread32(rdev->rio_mem + reg); |
| 4123 | else { |
| 4124 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
| 4125 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
| 4126 | } |
| 4127 | } |
| 4128 | |
| 4129 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 4130 | { |
| 4131 | if (reg < rdev->rio_mem_size) |
| 4132 | iowrite32(v, rdev->rio_mem + reg); |
| 4133 | else { |
| 4134 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
| 4135 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
| 4136 | } |
| 4137 | } |