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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2001 Ralf Baechle
Ralf Baechle70342282013-01-22 12:59:30 +01006 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This file define the irq handler for MIPS CPU interrupts.
10 *
Ralf Baechle70342282013-01-22 12:59:30 +010011 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 *
25 * Don't even think about using this on SMP. You have been warned.
26 *
27 * This file exports one global function:
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090028 * void mips_cpu_irq_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 */
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/kernel.h>
David Howellsca4d3e672010-10-07 14:08:54 +010033#include <linux/irq.h>
Gabor Juhos0916b462013-01-31 12:20:43 +000034#include <linux/irqdomain.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
Ralf Baechled03d0a52005-08-17 13:44:26 +000038#include <asm/mipsmtregs.h>
Andrew Brestickerf64e55d2014-09-18 14:47:10 -070039#include <asm/setup.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
Paul Burton892b8cf2015-05-24 16:11:16 +010041#include "irqchip.h"
42
Thomas Gleixnera93951c2011-03-23 21:09:02 +000043static inline void unmask_mips_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070044{
Thomas Gleixnera93951c2011-03-23 21:09:02 +000045 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechle569f75b2005-07-13 18:20:33 +000046 irq_enable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070047}
48
Thomas Gleixnera93951c2011-03-23 21:09:02 +000049static inline void mask_mips_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070050{
Thomas Gleixnera93951c2011-03-23 21:09:02 +000051 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechle569f75b2005-07-13 18:20:33 +000052 irq_disable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070053}
54
Ralf Baechle94dee172006-07-02 14:41:42 +010055static struct irq_chip mips_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090056 .name = "MIPS",
Thomas Gleixnera93951c2011-03-23 21:09:02 +000057 .irq_ack = mask_mips_irq,
58 .irq_mask = mask_mips_irq,
59 .irq_mask_ack = mask_mips_irq,
60 .irq_unmask = unmask_mips_irq,
61 .irq_eoi = unmask_mips_irq,
Felix Fietkaua3e6c1e2015-01-15 19:05:28 +010062 .irq_disable = mask_mips_irq,
63 .irq_enable = unmask_mips_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070064};
65
Ralf Baechled03d0a52005-08-17 13:44:26 +000066/*
67 * Basically the same as above but taking care of all the MT stuff
68 */
69
Thomas Gleixnera93951c2011-03-23 21:09:02 +000070static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
Ralf Baechled03d0a52005-08-17 13:44:26 +000071{
72 unsigned int vpflags = dvpe();
73
Thomas Gleixnera93951c2011-03-23 21:09:02 +000074 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechled03d0a52005-08-17 13:44:26 +000075 evpe(vpflags);
Thomas Gleixnera93951c2011-03-23 21:09:02 +000076 unmask_mips_irq(d);
Ralf Baechled03d0a52005-08-17 13:44:26 +000077 return 0;
78}
79
Ralf Baechled03d0a52005-08-17 13:44:26 +000080/*
81 * While we ack the interrupt interrupts are disabled and thus we don't need
82 * to deal with concurrency issues. Same for mips_cpu_irq_end.
83 */
Thomas Gleixnera93951c2011-03-23 21:09:02 +000084static void mips_mt_cpu_irq_ack(struct irq_data *d)
Ralf Baechled03d0a52005-08-17 13:44:26 +000085{
86 unsigned int vpflags = dvpe();
Thomas Gleixnera93951c2011-03-23 21:09:02 +000087 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechled03d0a52005-08-17 13:44:26 +000088 evpe(vpflags);
Thomas Gleixnera93951c2011-03-23 21:09:02 +000089 mask_mips_irq(d);
Ralf Baechled03d0a52005-08-17 13:44:26 +000090}
91
Ralf Baechle94dee172006-07-02 14:41:42 +010092static struct irq_chip mips_mt_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090093 .name = "MIPS",
Thomas Gleixnera93951c2011-03-23 21:09:02 +000094 .irq_startup = mips_mt_cpu_irq_startup,
95 .irq_ack = mips_mt_cpu_irq_ack,
96 .irq_mask = mask_mips_irq,
97 .irq_mask_ack = mips_mt_cpu_irq_ack,
98 .irq_unmask = unmask_mips_irq,
99 .irq_eoi = unmask_mips_irq,
Felix Fietkaua3e6c1e2015-01-15 19:05:28 +0100100 .irq_disable = mask_mips_irq,
101 .irq_enable = unmask_mips_irq,
Ralf Baechled03d0a52005-08-17 13:44:26 +0000102};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103
Andrew Bresticker85f7cda2014-09-18 14:47:09 -0700104asmlinkage void __weak plat_irq_dispatch(void)
105{
106 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
107 int irq;
108
109 if (!pending) {
110 spurious_interrupt();
111 return;
112 }
113
114 pending >>= CAUSEB_IP;
115 while (pending) {
116 irq = fls(pending) - 1;
117 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
118 pending &= ~BIT(irq);
119 }
120}
121
Gabor Juhos0916b462013-01-31 12:20:43 +0000122static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
123 irq_hw_number_t hw)
124{
125 static struct irq_chip *chip;
126
127 if (hw < 2 && cpu_has_mipsmt) {
128 /* Software interrupts are used for MT/CMT IPI */
129 chip = &mips_mt_cpu_irq_controller;
130 } else {
131 chip = &mips_cpu_irq_controller;
132 }
133
Andrew Brestickerf64e55d2014-09-18 14:47:10 -0700134 if (cpu_has_vint)
135 set_vi_handler(hw, plat_irq_dispatch);
136
Gabor Juhos0916b462013-01-31 12:20:43 +0000137 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
138
139 return 0;
140}
141
142static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
143 .map = mips_cpu_intc_map,
144 .xlate = irq_domain_xlate_onecell,
145};
146
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700147static void __init __mips_cpu_irq_init(struct device_node *of_node)
Gabor Juhos0916b462013-01-31 12:20:43 +0000148{
149 struct irq_domain *domain;
150
151 /* Mask interrupts. */
152 clear_c0_status(ST0_IM);
153 clear_c0_cause(CAUSEF_IP);
154
155 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
156 &mips_cpu_intc_irq_domain_ops, NULL);
157 if (!domain)
Ralf Baechlef7777dc2013-09-18 16:05:26 +0200158 panic("Failed to add irqdomain for MIPS CPU");
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700159}
Gabor Juhos0916b462013-01-31 12:20:43 +0000160
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700161void __init mips_cpu_irq_init(void)
162{
163 __mips_cpu_irq_init(NULL);
164}
165
Andrew Brestickerafe8dc22014-09-18 14:47:08 -0700166int __init mips_cpu_irq_of_init(struct device_node *of_node,
167 struct device_node *parent)
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700168{
169 __mips_cpu_irq_init(of_node);
Gabor Juhos0916b462013-01-31 12:20:43 +0000170 return 0;
171}
Paul Burton892b8cf2015-05-24 16:11:16 +0100172IRQCHIP_DECLARE(cpu_intc, "mti,cpu-interrupt-controller", mips_cpu_irq_of_init);