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Dinh Nguyen475dc862014-09-04 16:45:56 -05001/*
Dinh Nguyen88c8e4c2015-03-09 22:57:04 -05002 * Copyright (C) 2015 Altera Corporation <www.altera.com>
Dinh Nguyen475dc862014-09-04 16:45:56 -05003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
Dinh Nguyen475dc862014-09-04 16:45:56 -050017#include "socfpga_arria10.dtsi"
18
19/ {
20 model = "Altera SOCFPGA Arria 10";
21 compatible = "altr,socfpga-arria10", "altr,socfpga";
22
Dinh Nguyenefb66722016-05-03 08:59:01 -050023 aliases {
24 ethernet0 = &gmac0;
Matthew Gerlachb65c0ef2016-05-12 10:24:42 -070025 serial0 = &uart1;
Dinh Nguyenefb66722016-05-03 08:59:01 -050026 };
27
Dinh Nguyen475dc862014-09-04 16:45:56 -050028 chosen {
Dinh Nguyenefc19852015-07-14 17:19:02 -050029 bootargs = "earlyprintk";
Matthew Gerlachb65c0ef2016-05-12 10:24:42 -070030 stdout-path = "serial0:115200n8";
Dinh Nguyen475dc862014-09-04 16:45:56 -050031 };
32
33 memory {
34 name = "memory";
35 device_type = "memory";
36 reg = <0x0 0x40000000>; /* 1GB */
37 };
38
39 soc {
40 clkmgr@ffd04000 {
41 clocks {
42 osc1 {
43 clock-frequency = <25000000>;
44 };
45 };
46 };
Dinh Nguyen475dc862014-09-04 16:45:56 -050047 };
48};
Dinh Nguyen74568da2015-04-02 13:26:35 -050049
Dinh Nguyen112cadf2015-06-02 21:31:00 -050050&gmac0 {
51 phy-mode = "rgmii";
52 phy-addr = <0xffffffff>; /* probe for phy addr */
53
54 /*
55 * These skews assume the user's FPGA design is adding 600ps of delay
56 * for TX_CLK on Arria 10.
57 *
58 * All skews are offset since hardware skew values for the ksz9031
59 * range from a negative skew to a positive skew.
60 * See the micrel-ksz90x1.txt Documentation file for details.
61 */
62 txd0-skew-ps = <0>; /* -420ps */
63 txd1-skew-ps = <0>; /* -420ps */
64 txd2-skew-ps = <0>; /* -420ps */
65 txd3-skew-ps = <0>; /* -420ps */
66 rxd0-skew-ps = <420>; /* 0ps */
67 rxd1-skew-ps = <420>; /* 0ps */
68 rxd2-skew-ps = <420>; /* 0ps */
69 rxd3-skew-ps = <420>; /* 0ps */
70 txen-skew-ps = <0>; /* -420ps */
71 txc-skew-ps = <1860>; /* 960ps */
72 rxdv-skew-ps = <420>; /* 0ps */
73 rxc-skew-ps = <1680>; /* 780ps */
74 max-frame-size = <3800>;
75 status = "okay";
76};
77
Thor Thayer5984be02016-06-02 17:52:26 +000078&spi1 {
79 status = "okay";
80
81 resource-manager@0 {
82 compatible = "altr,a10sr";
83 reg = <0>;
84 spi-max-frequency = <100000>;
85 /* low-level active IRQ at GPIO1_5 */
86 interrupt-parent = <&portb>;
87 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
88 interrupt-controller;
89 #interrupt-cells = <2>;
90
91 a10sr_gpio: gpio-controller {
92 compatible = "altr,a10sr-gpio";
93 gpio-controller;
94 #gpio-cells = <2>;
95 };
96 };
97};
98
Dinh Nguyen19c21382015-09-22 14:50:37 -050099&i2c1 {
100 speed-mode = <0>;
101 status = "okay";
102
103 /*
104 * adjust the falling times to decrease the i2c frequency to 50Khz
105 * because the LCD module does not work at the standard 100Khz
106 */
107 i2c-sda-falling-time-ns = <6000>;
108 i2c-scl-falling-time-ns = <6000>;
109
110 eeprom@51 {
111 compatible = "atmel,24c32";
112 reg = <0x51>;
113 pagesize = <32>;
114 };
115
116 rtc@68 {
117 compatible = "dallas,ds1339";
118 reg = <0x68>;
119 };
120};
121
Dinh Nguyen74568da2015-04-02 13:26:35 -0500122&uart1 {
123 status = "okay";
124};
Dinh Nguyen19c21382015-09-22 14:50:37 -0500125
126&usb0 {
127 status = "okay";
128};