Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This is i.MX low power i2c controller driver. |
| 3 | * |
| 4 | * Copyright 2016 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/completion.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/errno.h> |
| 23 | #include <linux/i2c.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/kernel.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/of.h> |
| 30 | #include <linux/of_device.h> |
Gao Pan | e13fe92 | 2017-01-17 18:20:55 +0800 | [diff] [blame] | 31 | #include <linux/pinctrl/consumer.h> |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/sched.h> |
| 34 | #include <linux/slab.h> |
| 35 | |
| 36 | #define DRIVER_NAME "imx-lpi2c" |
| 37 | |
| 38 | #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */ |
| 39 | #define LPI2C_MCR 0x10 /* i2c contrl register */ |
| 40 | #define LPI2C_MSR 0x14 /* i2c status register */ |
| 41 | #define LPI2C_MIER 0x18 /* i2c interrupt enable */ |
| 42 | #define LPI2C_MCFGR0 0x20 /* i2c master configuration */ |
| 43 | #define LPI2C_MCFGR1 0x24 /* i2c master configuration */ |
| 44 | #define LPI2C_MCFGR2 0x28 /* i2c master configuration */ |
| 45 | #define LPI2C_MCFGR3 0x2C /* i2c master configuration */ |
| 46 | #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */ |
| 47 | #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */ |
| 48 | #define LPI2C_MFCR 0x58 /* i2c master FIFO control */ |
| 49 | #define LPI2C_MFSR 0x5C /* i2c master FIFO status */ |
| 50 | #define LPI2C_MTDR 0x60 /* i2c master TX data register */ |
| 51 | #define LPI2C_MRDR 0x70 /* i2c master RX data register */ |
| 52 | |
| 53 | /* i2c command */ |
| 54 | #define TRAN_DATA 0X00 |
| 55 | #define RECV_DATA 0X01 |
| 56 | #define GEN_STOP 0X02 |
| 57 | #define RECV_DISCARD 0X03 |
| 58 | #define GEN_START 0X04 |
| 59 | #define START_NACK 0X05 |
| 60 | #define START_HIGH 0X06 |
| 61 | #define START_HIGH_NACK 0X07 |
| 62 | |
| 63 | #define MCR_MEN BIT(0) |
| 64 | #define MCR_RST BIT(1) |
| 65 | #define MCR_DOZEN BIT(2) |
| 66 | #define MCR_DBGEN BIT(3) |
| 67 | #define MCR_RTF BIT(8) |
| 68 | #define MCR_RRF BIT(9) |
| 69 | #define MSR_TDF BIT(0) |
| 70 | #define MSR_RDF BIT(1) |
| 71 | #define MSR_SDF BIT(9) |
| 72 | #define MSR_NDF BIT(10) |
| 73 | #define MSR_ALF BIT(11) |
| 74 | #define MSR_MBF BIT(24) |
| 75 | #define MSR_BBF BIT(25) |
| 76 | #define MIER_TDIE BIT(0) |
| 77 | #define MIER_RDIE BIT(1) |
| 78 | #define MIER_SDIE BIT(9) |
| 79 | #define MIER_NDIE BIT(10) |
| 80 | #define MCFGR1_AUTOSTOP BIT(8) |
| 81 | #define MCFGR1_IGNACK BIT(9) |
| 82 | #define MRDR_RXEMPTY BIT(14) |
| 83 | |
| 84 | #define I2C_CLK_RATIO 2 |
| 85 | #define CHUNK_DATA 256 |
| 86 | |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 87 | #define LPI2C_DEFAULT_RATE 100000 |
| 88 | #define STARDARD_MAX_BITRATE 400000 |
| 89 | #define FAST_MAX_BITRATE 1000000 |
| 90 | #define FAST_PLUS_MAX_BITRATE 3400000 |
| 91 | #define HIGHSPEED_MAX_BITRATE 5000000 |
| 92 | |
| 93 | enum lpi2c_imx_mode { |
| 94 | STANDARD, /* 100+Kbps */ |
| 95 | FAST, /* 400+Kbps */ |
| 96 | FAST_PLUS, /* 1.0+Mbps */ |
| 97 | HS, /* 3.4+Mbps */ |
| 98 | ULTRA_FAST, /* 5.0+Mbps */ |
| 99 | }; |
| 100 | |
| 101 | enum lpi2c_imx_pincfg { |
| 102 | TWO_PIN_OD, |
| 103 | TWO_PIN_OO, |
| 104 | TWO_PIN_PP, |
| 105 | FOUR_PIN_PP, |
| 106 | }; |
| 107 | |
| 108 | struct lpi2c_imx_struct { |
| 109 | struct i2c_adapter adapter; |
| 110 | struct clk *clk; |
| 111 | void __iomem *base; |
| 112 | __u8 *rx_buf; |
| 113 | __u8 *tx_buf; |
| 114 | struct completion complete; |
| 115 | unsigned int msglen; |
| 116 | unsigned int delivered; |
| 117 | unsigned int block_data; |
| 118 | unsigned int bitrate; |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 119 | unsigned int txfifosize; |
| 120 | unsigned int rxfifosize; |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 121 | enum lpi2c_imx_mode mode; |
| 122 | }; |
| 123 | |
| 124 | static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx, |
| 125 | unsigned int enable) |
| 126 | { |
| 127 | writel(enable, lpi2c_imx->base + LPI2C_MIER); |
| 128 | } |
| 129 | |
| 130 | static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx) |
| 131 | { |
| 132 | unsigned long orig_jiffies = jiffies; |
| 133 | unsigned int temp; |
| 134 | |
| 135 | while (1) { |
| 136 | temp = readl(lpi2c_imx->base + LPI2C_MSR); |
| 137 | |
| 138 | /* check for arbitration lost, clear if set */ |
| 139 | if (temp & MSR_ALF) { |
| 140 | writel(temp, lpi2c_imx->base + LPI2C_MSR); |
| 141 | return -EAGAIN; |
| 142 | } |
| 143 | |
| 144 | if (temp & (MSR_BBF | MSR_MBF)) |
| 145 | break; |
| 146 | |
| 147 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
| 148 | dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n"); |
| 149 | return -ETIMEDOUT; |
| 150 | } |
| 151 | schedule(); |
| 152 | } |
| 153 | |
| 154 | return 0; |
| 155 | } |
| 156 | |
| 157 | static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx) |
| 158 | { |
| 159 | unsigned int bitrate = lpi2c_imx->bitrate; |
| 160 | enum lpi2c_imx_mode mode; |
| 161 | |
| 162 | if (bitrate < STARDARD_MAX_BITRATE) |
| 163 | mode = STANDARD; |
| 164 | else if (bitrate < FAST_MAX_BITRATE) |
| 165 | mode = FAST; |
| 166 | else if (bitrate < FAST_PLUS_MAX_BITRATE) |
| 167 | mode = FAST_PLUS; |
| 168 | else if (bitrate < HIGHSPEED_MAX_BITRATE) |
| 169 | mode = HS; |
| 170 | else |
| 171 | mode = ULTRA_FAST; |
| 172 | |
| 173 | lpi2c_imx->mode = mode; |
| 174 | } |
| 175 | |
| 176 | static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx, |
| 177 | struct i2c_msg *msgs) |
| 178 | { |
| 179 | unsigned int temp; |
| 180 | u8 read; |
| 181 | |
| 182 | temp = readl(lpi2c_imx->base + LPI2C_MCR); |
| 183 | temp |= MCR_RRF | MCR_RTF; |
| 184 | writel(temp, lpi2c_imx->base + LPI2C_MCR); |
| 185 | writel(0x7f00, lpi2c_imx->base + LPI2C_MSR); |
| 186 | |
| 187 | read = msgs->flags & I2C_M_RD; |
| 188 | temp = (msgs->addr << 1 | read) | (GEN_START << 8); |
| 189 | writel(temp, lpi2c_imx->base + LPI2C_MTDR); |
| 190 | |
| 191 | return lpi2c_imx_bus_busy(lpi2c_imx); |
| 192 | } |
| 193 | |
| 194 | static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) |
| 195 | { |
| 196 | unsigned long orig_jiffies = jiffies; |
| 197 | unsigned int temp; |
| 198 | |
| 199 | writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); |
| 200 | |
| 201 | do { |
| 202 | temp = readl(lpi2c_imx->base + LPI2C_MSR); |
| 203 | if (temp & MSR_SDF) |
| 204 | break; |
| 205 | |
| 206 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
| 207 | dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n"); |
| 208 | break; |
| 209 | } |
| 210 | schedule(); |
| 211 | |
| 212 | } while (1); |
| 213 | } |
| 214 | |
| 215 | /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ |
| 216 | static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) |
| 217 | { |
| 218 | u8 prescale, filt, sethold, clkhi, clklo, datavd; |
| 219 | unsigned int clk_rate, clk_cycle; |
| 220 | enum lpi2c_imx_pincfg pincfg; |
| 221 | unsigned int temp; |
| 222 | |
| 223 | lpi2c_imx_set_mode(lpi2c_imx); |
| 224 | |
| 225 | clk_rate = clk_get_rate(lpi2c_imx->clk); |
| 226 | if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST) |
| 227 | filt = 0; |
| 228 | else |
| 229 | filt = 2; |
| 230 | |
| 231 | for (prescale = 0; prescale <= 7; prescale++) { |
| 232 | clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate) |
| 233 | - 3 - (filt >> 1); |
| 234 | clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1); |
| 235 | clklo = clk_cycle - clkhi; |
| 236 | if (clklo < 64) |
| 237 | break; |
| 238 | } |
| 239 | |
| 240 | if (prescale > 7) |
| 241 | return -EINVAL; |
| 242 | |
| 243 | /* set MCFGR1: PINCFG, PRESCALE, IGNACK */ |
| 244 | if (lpi2c_imx->mode == ULTRA_FAST) |
| 245 | pincfg = TWO_PIN_OO; |
| 246 | else |
| 247 | pincfg = TWO_PIN_OD; |
| 248 | temp = prescale | pincfg << 24; |
| 249 | |
| 250 | if (lpi2c_imx->mode == ULTRA_FAST) |
| 251 | temp |= MCFGR1_IGNACK; |
| 252 | |
| 253 | writel(temp, lpi2c_imx->base + LPI2C_MCFGR1); |
| 254 | |
| 255 | /* set MCFGR2: FILTSDA, FILTSCL */ |
| 256 | temp = (filt << 16) | (filt << 24); |
| 257 | writel(temp, lpi2c_imx->base + LPI2C_MCFGR2); |
| 258 | |
| 259 | /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */ |
| 260 | sethold = clkhi; |
| 261 | datavd = clkhi >> 1; |
| 262 | temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo; |
| 263 | |
| 264 | if (lpi2c_imx->mode == HS) |
| 265 | writel(temp, lpi2c_imx->base + LPI2C_MCCR1); |
| 266 | else |
| 267 | writel(temp, lpi2c_imx->base + LPI2C_MCCR0); |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx) |
| 273 | { |
| 274 | unsigned int temp; |
| 275 | int ret; |
| 276 | |
| 277 | ret = clk_enable(lpi2c_imx->clk); |
| 278 | if (ret) |
| 279 | return ret; |
| 280 | |
| 281 | temp = MCR_RST; |
| 282 | writel(temp, lpi2c_imx->base + LPI2C_MCR); |
| 283 | writel(0, lpi2c_imx->base + LPI2C_MCR); |
| 284 | |
| 285 | ret = lpi2c_imx_config(lpi2c_imx); |
| 286 | if (ret) |
| 287 | goto clk_disable; |
| 288 | |
| 289 | temp = readl(lpi2c_imx->base + LPI2C_MCR); |
| 290 | temp |= MCR_MEN; |
| 291 | writel(temp, lpi2c_imx->base + LPI2C_MCR); |
| 292 | |
| 293 | return 0; |
| 294 | |
| 295 | clk_disable: |
| 296 | clk_disable(lpi2c_imx->clk); |
| 297 | |
| 298 | return ret; |
| 299 | } |
| 300 | |
| 301 | static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx) |
| 302 | { |
| 303 | u32 temp; |
| 304 | |
| 305 | temp = readl(lpi2c_imx->base + LPI2C_MCR); |
| 306 | temp &= ~MCR_MEN; |
| 307 | writel(temp, lpi2c_imx->base + LPI2C_MCR); |
| 308 | |
| 309 | clk_disable(lpi2c_imx->clk); |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) |
| 315 | { |
| 316 | unsigned long timeout; |
| 317 | |
| 318 | timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ); |
| 319 | |
| 320 | return timeout ? 0 : -ETIMEDOUT; |
| 321 | } |
| 322 | |
| 323 | static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx) |
| 324 | { |
| 325 | unsigned long orig_jiffies = jiffies; |
| 326 | u32 txcnt; |
| 327 | |
| 328 | do { |
| 329 | txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; |
| 330 | |
| 331 | if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) { |
| 332 | dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n"); |
| 333 | return -EIO; |
| 334 | } |
| 335 | |
| 336 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
| 337 | dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n"); |
| 338 | return -ETIMEDOUT; |
| 339 | } |
| 340 | schedule(); |
| 341 | |
| 342 | } while (txcnt); |
| 343 | |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx) |
| 348 | { |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 349 | writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR); |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx) |
| 353 | { |
| 354 | unsigned int temp, remaining; |
| 355 | |
| 356 | remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; |
| 357 | |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 358 | if (remaining > (lpi2c_imx->rxfifosize >> 1)) |
| 359 | temp = lpi2c_imx->rxfifosize >> 1; |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 360 | else |
| 361 | temp = 0; |
| 362 | |
| 363 | writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR); |
| 364 | } |
| 365 | |
| 366 | static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx) |
| 367 | { |
| 368 | unsigned int data, txcnt; |
| 369 | |
| 370 | txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; |
| 371 | |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 372 | while (txcnt < lpi2c_imx->txfifosize) { |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 373 | if (lpi2c_imx->delivered == lpi2c_imx->msglen) |
| 374 | break; |
| 375 | |
| 376 | data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++]; |
| 377 | writel(data, lpi2c_imx->base + LPI2C_MTDR); |
| 378 | txcnt++; |
| 379 | } |
| 380 | |
| 381 | if (lpi2c_imx->delivered < lpi2c_imx->msglen) |
| 382 | lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE); |
| 383 | else |
| 384 | complete(&lpi2c_imx->complete); |
| 385 | } |
| 386 | |
| 387 | static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx) |
| 388 | { |
| 389 | unsigned int blocklen, remaining; |
| 390 | unsigned int temp, data; |
| 391 | |
| 392 | do { |
| 393 | data = readl(lpi2c_imx->base + LPI2C_MRDR); |
| 394 | if (data & MRDR_RXEMPTY) |
| 395 | break; |
| 396 | |
| 397 | lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff; |
| 398 | } while (1); |
| 399 | |
| 400 | /* |
| 401 | * First byte is the length of remaining packet in the SMBus block |
| 402 | * data read. Add it to msgs->len. |
| 403 | */ |
| 404 | if (lpi2c_imx->block_data) { |
| 405 | blocklen = lpi2c_imx->rx_buf[0]; |
| 406 | lpi2c_imx->msglen += blocklen; |
| 407 | } |
| 408 | |
| 409 | remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; |
| 410 | |
| 411 | if (!remaining) { |
| 412 | complete(&lpi2c_imx->complete); |
| 413 | return; |
| 414 | } |
| 415 | |
| 416 | /* not finished, still waiting for rx data */ |
| 417 | lpi2c_imx_set_rx_watermark(lpi2c_imx); |
| 418 | |
| 419 | /* multiple receive commands */ |
| 420 | if (lpi2c_imx->block_data) { |
| 421 | lpi2c_imx->block_data = 0; |
| 422 | temp = remaining; |
| 423 | temp |= (RECV_DATA << 8); |
| 424 | writel(temp, lpi2c_imx->base + LPI2C_MTDR); |
| 425 | } else if (!(lpi2c_imx->delivered & 0xff)) { |
| 426 | temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1; |
| 427 | temp |= (RECV_DATA << 8); |
| 428 | writel(temp, lpi2c_imx->base + LPI2C_MTDR); |
| 429 | } |
| 430 | |
| 431 | lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE); |
| 432 | } |
| 433 | |
| 434 | static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx, |
| 435 | struct i2c_msg *msgs) |
| 436 | { |
| 437 | lpi2c_imx->tx_buf = msgs->buf; |
| 438 | lpi2c_imx_set_tx_watermark(lpi2c_imx); |
| 439 | lpi2c_imx_write_txfifo(lpi2c_imx); |
| 440 | } |
| 441 | |
| 442 | static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx, |
| 443 | struct i2c_msg *msgs) |
| 444 | { |
| 445 | unsigned int temp; |
| 446 | |
| 447 | lpi2c_imx->rx_buf = msgs->buf; |
| 448 | lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN; |
| 449 | |
| 450 | lpi2c_imx_set_rx_watermark(lpi2c_imx); |
| 451 | temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1; |
| 452 | temp |= (RECV_DATA << 8); |
| 453 | writel(temp, lpi2c_imx->base + LPI2C_MTDR); |
| 454 | |
| 455 | lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); |
| 456 | } |
| 457 | |
| 458 | static int lpi2c_imx_xfer(struct i2c_adapter *adapter, |
| 459 | struct i2c_msg *msgs, int num) |
| 460 | { |
| 461 | struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter); |
| 462 | unsigned int temp; |
| 463 | int i, result; |
| 464 | |
| 465 | result = lpi2c_imx_master_enable(lpi2c_imx); |
| 466 | if (result) |
| 467 | return result; |
| 468 | |
| 469 | for (i = 0; i < num; i++) { |
| 470 | result = lpi2c_imx_start(lpi2c_imx, &msgs[i]); |
| 471 | if (result) |
| 472 | goto disable; |
| 473 | |
| 474 | /* quick smbus */ |
| 475 | if (num == 1 && msgs[0].len == 0) |
| 476 | goto stop; |
| 477 | |
| 478 | lpi2c_imx->delivered = 0; |
| 479 | lpi2c_imx->msglen = msgs[i].len; |
| 480 | init_completion(&lpi2c_imx->complete); |
| 481 | |
| 482 | if (msgs[i].flags & I2C_M_RD) |
| 483 | lpi2c_imx_read(lpi2c_imx, &msgs[i]); |
| 484 | else |
| 485 | lpi2c_imx_write(lpi2c_imx, &msgs[i]); |
| 486 | |
| 487 | result = lpi2c_imx_msg_complete(lpi2c_imx); |
| 488 | if (result) |
| 489 | goto stop; |
| 490 | |
| 491 | if (!(msgs[i].flags & I2C_M_RD)) { |
| 492 | result = lpi2c_imx_txfifo_empty(lpi2c_imx); |
| 493 | if (result) |
| 494 | goto stop; |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | stop: |
| 499 | lpi2c_imx_stop(lpi2c_imx); |
| 500 | |
| 501 | temp = readl(lpi2c_imx->base + LPI2C_MSR); |
| 502 | if ((temp & MSR_NDF) && !result) |
| 503 | result = -EIO; |
| 504 | |
| 505 | disable: |
| 506 | lpi2c_imx_master_disable(lpi2c_imx); |
| 507 | |
| 508 | dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, |
| 509 | (result < 0) ? "error" : "success msg", |
| 510 | (result < 0) ? result : num); |
| 511 | |
| 512 | return (result < 0) ? result : num; |
| 513 | } |
| 514 | |
| 515 | static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) |
| 516 | { |
| 517 | struct lpi2c_imx_struct *lpi2c_imx = dev_id; |
| 518 | unsigned int temp; |
| 519 | |
| 520 | lpi2c_imx_intctrl(lpi2c_imx, 0); |
| 521 | temp = readl(lpi2c_imx->base + LPI2C_MSR); |
| 522 | |
| 523 | if (temp & MSR_RDF) |
| 524 | lpi2c_imx_read_rxfifo(lpi2c_imx); |
| 525 | |
| 526 | if (temp & MSR_TDF) |
| 527 | lpi2c_imx_write_txfifo(lpi2c_imx); |
| 528 | |
| 529 | if (temp & MSR_NDF) |
| 530 | complete(&lpi2c_imx->complete); |
| 531 | |
| 532 | return IRQ_HANDLED; |
| 533 | } |
| 534 | |
| 535 | static u32 lpi2c_imx_func(struct i2c_adapter *adapter) |
| 536 | { |
| 537 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
| 538 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; |
| 539 | } |
| 540 | |
Bhumika Goyal | 92d9d0d | 2017-01-27 23:36:17 +0530 | [diff] [blame] | 541 | static const struct i2c_algorithm lpi2c_imx_algo = { |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 542 | .master_xfer = lpi2c_imx_xfer, |
| 543 | .functionality = lpi2c_imx_func, |
| 544 | }; |
| 545 | |
| 546 | static const struct of_device_id lpi2c_imx_of_match[] = { |
| 547 | { .compatible = "fsl,imx7ulp-lpi2c" }, |
| 548 | { .compatible = "fsl,imx8dv-lpi2c" }, |
| 549 | { }, |
| 550 | }; |
| 551 | MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); |
| 552 | |
| 553 | static int lpi2c_imx_probe(struct platform_device *pdev) |
| 554 | { |
| 555 | struct lpi2c_imx_struct *lpi2c_imx; |
| 556 | struct resource *res; |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 557 | unsigned int temp; |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 558 | int irq, ret; |
| 559 | |
| 560 | lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL); |
| 561 | if (!lpi2c_imx) |
| 562 | return -ENOMEM; |
| 563 | |
| 564 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 565 | lpi2c_imx->base = devm_ioremap_resource(&pdev->dev, res); |
| 566 | if (IS_ERR(lpi2c_imx->base)) |
| 567 | return PTR_ERR(lpi2c_imx->base); |
| 568 | |
| 569 | irq = platform_get_irq(pdev, 0); |
| 570 | if (irq < 0) { |
| 571 | dev_err(&pdev->dev, "can't get irq number\n"); |
| 572 | return irq; |
| 573 | } |
| 574 | |
| 575 | lpi2c_imx->adapter.owner = THIS_MODULE; |
| 576 | lpi2c_imx->adapter.algo = &lpi2c_imx_algo; |
| 577 | lpi2c_imx->adapter.dev.parent = &pdev->dev; |
| 578 | lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; |
| 579 | strlcpy(lpi2c_imx->adapter.name, pdev->name, |
| 580 | sizeof(lpi2c_imx->adapter.name)); |
| 581 | |
| 582 | lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); |
| 583 | if (IS_ERR(lpi2c_imx->clk)) { |
| 584 | dev_err(&pdev->dev, "can't get I2C peripheral clock\n"); |
| 585 | return PTR_ERR(lpi2c_imx->clk); |
| 586 | } |
| 587 | |
| 588 | ret = of_property_read_u32(pdev->dev.of_node, |
| 589 | "clock-frequency", &lpi2c_imx->bitrate); |
| 590 | if (ret) |
| 591 | lpi2c_imx->bitrate = LPI2C_DEFAULT_RATE; |
| 592 | |
| 593 | ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0, |
| 594 | pdev->name, lpi2c_imx); |
| 595 | if (ret) { |
| 596 | dev_err(&pdev->dev, "can't claim irq %d\n", irq); |
| 597 | return ret; |
| 598 | } |
| 599 | |
| 600 | i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx); |
| 601 | platform_set_drvdata(pdev, lpi2c_imx); |
| 602 | |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 603 | ret = clk_prepare_enable(lpi2c_imx->clk); |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 604 | if (ret) { |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 605 | dev_err(&pdev->dev, "clk enable failed %d\n", ret); |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 606 | return ret; |
| 607 | } |
| 608 | |
Gao Pan | 6eb89ef | 2016-12-02 11:38:16 +0800 | [diff] [blame] | 609 | temp = readl(lpi2c_imx->base + LPI2C_PARAM); |
| 610 | lpi2c_imx->txfifosize = 1 << (temp & 0x0f); |
| 611 | lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f); |
| 612 | |
| 613 | clk_disable(lpi2c_imx->clk); |
| 614 | |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 615 | ret = i2c_add_adapter(&lpi2c_imx->adapter); |
| 616 | if (ret) |
| 617 | goto clk_unprepare; |
| 618 | |
| 619 | dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n"); |
| 620 | |
| 621 | return 0; |
| 622 | |
| 623 | clk_unprepare: |
| 624 | clk_unprepare(lpi2c_imx->clk); |
| 625 | |
| 626 | return ret; |
| 627 | } |
| 628 | |
| 629 | static int lpi2c_imx_remove(struct platform_device *pdev) |
| 630 | { |
| 631 | struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev); |
| 632 | |
| 633 | i2c_del_adapter(&lpi2c_imx->adapter); |
| 634 | |
| 635 | clk_unprepare(lpi2c_imx->clk); |
| 636 | |
| 637 | return 0; |
| 638 | } |
| 639 | |
Gao Pan | e13fe92 | 2017-01-17 18:20:55 +0800 | [diff] [blame] | 640 | #ifdef CONFIG_PM_SLEEP |
| 641 | static int lpi2c_imx_suspend(struct device *dev) |
| 642 | { |
| 643 | pinctrl_pm_select_sleep_state(dev); |
| 644 | |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | static int lpi2c_imx_resume(struct device *dev) |
| 649 | { |
| 650 | pinctrl_pm_select_default_state(dev); |
| 651 | |
| 652 | return 0; |
| 653 | } |
| 654 | #endif |
| 655 | |
| 656 | static SIMPLE_DEV_PM_OPS(imx_lpi2c_pm, lpi2c_imx_suspend, lpi2c_imx_resume); |
| 657 | |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 658 | static struct platform_driver lpi2c_imx_driver = { |
| 659 | .probe = lpi2c_imx_probe, |
| 660 | .remove = lpi2c_imx_remove, |
| 661 | .driver = { |
| 662 | .name = DRIVER_NAME, |
| 663 | .of_match_table = lpi2c_imx_of_match, |
Gao Pan | e13fe92 | 2017-01-17 18:20:55 +0800 | [diff] [blame] | 664 | .pm = &imx_lpi2c_pm, |
Gao Pan | a55fa9d | 2016-11-30 10:40:47 +0800 | [diff] [blame] | 665 | }, |
| 666 | }; |
| 667 | |
| 668 | module_platform_driver(lpi2c_imx_driver); |
| 669 | |
| 670 | MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); |
| 671 | MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus"); |
| 672 | MODULE_LICENSE("GPL"); |