blob: 761613f9fd5a0d208788ac1e6ee16635eb830ae3 [file] [log] [blame]
Ralph Metzler43dd07f2011-07-03 13:42:18 -03001#define AUD_COMM_EXEC__A 0x1000000
Ralph Metzler43dd07f2011-07-03 13:42:18 -03002#define AUD_COMM_EXEC_STOP 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -03003#define FEC_COMM_EXEC__A 0x1C00000
Ralph Metzler43dd07f2011-07-03 13:42:18 -03004#define FEC_COMM_EXEC_STOP 0x0
5#define FEC_COMM_EXEC_ACTIVE 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -03006#define FEC_DI_COMM_EXEC__A 0x1C20000
Ralph Metzler43dd07f2011-07-03 13:42:18 -03007#define FEC_DI_COMM_EXEC_STOP 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -03008#define FEC_DI_INPUT_CTL__A 0x1C20016
Ralph Metzler43dd07f2011-07-03 13:42:18 -03009#define FEC_RS_COMM_EXEC__A 0x1C30000
Ralph Metzler43dd07f2011-07-03 13:42:18 -030010#define FEC_RS_COMM_EXEC_STOP 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -030011#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
Ralph Metzler43dd07f2011-07-03 13:42:18 -030012#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
Mauro Carvalho Chehab8f3741e2013-03-20 06:15:45 -030013#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014
Ralph Metzler43dd07f2011-07-03 13:42:18 -030014#define FEC_OC_MODE__A 0x1C40011
Ralph Metzler43dd07f2011-07-03 13:42:18 -030015#define FEC_OC_MODE_PARITY__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030016#define FEC_OC_DTO_MODE__A 0x1C40014
Ralph Metzler43dd07f2011-07-03 13:42:18 -030017#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030018#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -030019#define FEC_OC_DTO_PERIOD__A 0x1C40015
Ralph Metzler43dd07f2011-07-03 13:42:18 -030020#define FEC_OC_DTO_BURST_LEN__A 0x1C40018
Ralph Metzler43dd07f2011-07-03 13:42:18 -030021#define FEC_OC_FCT_MODE__A 0x1C4001A
Ralph Metzler43dd07f2011-07-03 13:42:18 -030022#define FEC_OC_FCT_MODE__PRE 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -030023#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030024#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -030025#define FEC_OC_TMD_MODE__A 0x1C4001E
Ralph Metzler43dd07f2011-07-03 13:42:18 -030026#define FEC_OC_TMD_COUNT__A 0x1C4001F
Ralph Metzler43dd07f2011-07-03 13:42:18 -030027#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
Ralph Metzler43dd07f2011-07-03 13:42:18 -030028#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
Ralph Metzler43dd07f2011-07-03 13:42:18 -030029#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
Ralph Metzler43dd07f2011-07-03 13:42:18 -030030#define FEC_OC_AVR_PARM_A__A 0x1C40026
Ralph Metzler43dd07f2011-07-03 13:42:18 -030031#define FEC_OC_AVR_PARM_B__A 0x1C40027
Ralph Metzler43dd07f2011-07-03 13:42:18 -030032#define FEC_OC_RCN_GAIN__A 0x1C4002E
Ralph Metzler43dd07f2011-07-03 13:42:18 -030033#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
Ralph Metzler43dd07f2011-07-03 13:42:18 -030034#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
Ralph Metzler43dd07f2011-07-03 13:42:18 -030035#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
Ralph Metzler43dd07f2011-07-03 13:42:18 -030036#define FEC_OC_SNC_MODE__A 0x1C40040
Ralph Metzler43dd07f2011-07-03 13:42:18 -030037#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
Ralph Metzler43dd07f2011-07-03 13:42:18 -030038#define FEC_OC_SNC_LWM__A 0x1C40041
Ralph Metzler43dd07f2011-07-03 13:42:18 -030039#define FEC_OC_SNC_HWM__A 0x1C40042
Ralph Metzler43dd07f2011-07-03 13:42:18 -030040#define FEC_OC_SNC_UNLOCK__A 0x1C40043
Ralph Metzler43dd07f2011-07-03 13:42:18 -030041#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
Ralph Metzler43dd07f2011-07-03 13:42:18 -030042#define FEC_OC_IPR_MODE__A 0x1C40048
Ralph Metzler43dd07f2011-07-03 13:42:18 -030043#define FEC_OC_IPR_MODE_SERIAL__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030044#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -030045#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
Ralph Metzler43dd07f2011-07-03 13:42:18 -030046#define FEC_OC_IPR_INVERT__A 0x1C40049
Ralph Metzler43dd07f2011-07-03 13:42:18 -030047#define FEC_OC_IPR_INVERT_MD0__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030048#define FEC_OC_IPR_INVERT_MD1__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -030049#define FEC_OC_IPR_INVERT_MD2__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -030050#define FEC_OC_IPR_INVERT_MD3__M 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -030051#define FEC_OC_IPR_INVERT_MD4__M 0x10
Ralph Metzler43dd07f2011-07-03 13:42:18 -030052#define FEC_OC_IPR_INVERT_MD5__M 0x20
Ralph Metzler43dd07f2011-07-03 13:42:18 -030053#define FEC_OC_IPR_INVERT_MD6__M 0x40
Ralph Metzler43dd07f2011-07-03 13:42:18 -030054#define FEC_OC_IPR_INVERT_MD7__M 0x80
Ralph Metzler43dd07f2011-07-03 13:42:18 -030055#define FEC_OC_IPR_INVERT_MERR__M 0x100
Ralph Metzler43dd07f2011-07-03 13:42:18 -030056#define FEC_OC_IPR_INVERT_MSTRT__M 0x200
Ralph Metzler43dd07f2011-07-03 13:42:18 -030057#define FEC_OC_IPR_INVERT_MVAL__M 0x400
Ralph Metzler43dd07f2011-07-03 13:42:18 -030058#define FEC_OC_IPR_INVERT_MCLK__M 0x800
Ralph Metzler43dd07f2011-07-03 13:42:18 -030059#define FEC_OC_OCR_INVERT__A 0x1C40052
Ralph Metzler43dd07f2011-07-03 13:42:18 -030060#define IQM_COMM_EXEC__A 0x1800000
Ralph Metzler43dd07f2011-07-03 13:42:18 -030061#define IQM_COMM_EXEC_B_STOP 0x0
62#define IQM_COMM_EXEC_B_ACTIVE 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030063#define IQM_FS_RATE_OFS_LO__A 0x1820010
Ralph Metzler43dd07f2011-07-03 13:42:18 -030064#define IQM_FS_ADJ_SEL__A 0x1820014
Ralph Metzler43dd07f2011-07-03 13:42:18 -030065#define IQM_FS_ADJ_SEL_B_OFF 0x0
66#define IQM_FS_ADJ_SEL_B_QAM 0x1
67#define IQM_FS_ADJ_SEL_B_VSB 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -030068#define IQM_FD_RATESEL__A 0x1830010
Ralph Metzler43dd07f2011-07-03 13:42:18 -030069#define IQM_RC_RATE_OFS_LO__A 0x1840010
70#define IQM_RC_RATE_OFS_LO__W 16
71#define IQM_RC_RATE_OFS_LO__M 0xFFFF
Ralph Metzler43dd07f2011-07-03 13:42:18 -030072#define IQM_RC_RATE_OFS_HI__M 0xFF
Ralph Metzler43dd07f2011-07-03 13:42:18 -030073#define IQM_RC_ADJ_SEL__A 0x1840014
Ralph Metzler43dd07f2011-07-03 13:42:18 -030074#define IQM_RC_ADJ_SEL_B_OFF 0x0
75#define IQM_RC_ADJ_SEL_B_QAM 0x1
76#define IQM_RC_ADJ_SEL_B_VSB 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -030077#define IQM_RC_STRETCH__A 0x1840016
Ralph Metzler43dd07f2011-07-03 13:42:18 -030078#define IQM_CF_COMM_INT_MSK__A 0x1860006
Ralph Metzler43dd07f2011-07-03 13:42:18 -030079#define IQM_CF_SYMMETRIC__A 0x1860010
Ralph Metzler43dd07f2011-07-03 13:42:18 -030080#define IQM_CF_MIDTAP__A 0x1860011
Ralph Metzler43dd07f2011-07-03 13:42:18 -030081#define IQM_CF_MIDTAP_RE__B 0
Ralph Metzler43dd07f2011-07-03 13:42:18 -030082#define IQM_CF_MIDTAP_IM__B 1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030083#define IQM_CF_OUT_ENA__A 0x1860012
Ralph Metzler43dd07f2011-07-03 13:42:18 -030084#define IQM_CF_OUT_ENA_QAM__B 1
Ralph Metzler43dd07f2011-07-03 13:42:18 -030085#define IQM_CF_OUT_ENA_OFDM__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -030086#define IQM_CF_ADJ_SEL__A 0x1860013
Ralph Metzler43dd07f2011-07-03 13:42:18 -030087#define IQM_CF_SCALE__A 0x1860014
Ralph Metzler43dd07f2011-07-03 13:42:18 -030088#define IQM_CF_SCALE_SH__A 0x1860015
Ralph Metzler43dd07f2011-07-03 13:42:18 -030089#define IQM_CF_SCALE_SH__PRE 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -030090#define IQM_CF_POW_MEAS_LEN__A 0x1860017
Ralph Metzler43dd07f2011-07-03 13:42:18 -030091#define IQM_CF_DS_ENA__A 0x1860019
Ralph Metzler43dd07f2011-07-03 13:42:18 -030092#define IQM_CF_TAP_RE0__A 0x1860020
Ralph Metzler43dd07f2011-07-03 13:42:18 -030093#define IQM_CF_TAP_IM0__A 0x1860040
Ralph Metzler43dd07f2011-07-03 13:42:18 -030094#define IQM_CF_CLP_VAL__A 0x1860060
Ralph Metzler43dd07f2011-07-03 13:42:18 -030095#define IQM_CF_DATATH__A 0x1860061
Ralph Metzler43dd07f2011-07-03 13:42:18 -030096#define IQM_CF_PKDTH__A 0x1860062
Ralph Metzler43dd07f2011-07-03 13:42:18 -030097#define IQM_CF_WND_LEN__A 0x1860063
Ralph Metzler43dd07f2011-07-03 13:42:18 -030098#define IQM_CF_DET_LCT__A 0x1860064
Ralph Metzler43dd07f2011-07-03 13:42:18 -030099#define IQM_CF_BYPASSDET__A 0x1860067
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300100#define IQM_AF_COMM_EXEC__A 0x1870000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300101#define IQM_AF_COMM_EXEC_ACTIVE 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300102#define IQM_AF_CLKNEG__A 0x1870012
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300103#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300104#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
105#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300106#define IQM_AF_START_LOCK__A 0x187001B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300107#define IQM_AF_PHASE0__A 0x187001C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300108#define IQM_AF_PHASE1__A 0x187001D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300109#define IQM_AF_PHASE2__A 0x187001E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300110#define IQM_AF_CLP_LEN__A 0x1870023
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300111#define IQM_AF_CLP_TH__A 0x1870024
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300112#define IQM_AF_SNS_LEN__A 0x1870026
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300113#define IQM_AF_AGC_IF__A 0x1870028
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300114#define IQM_AF_AGC_RF__A 0x1870029
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300115#define IQM_AF_PDREF__A 0x187002B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300116#define IQM_AF_PDREF__M 0x1F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300117#define IQM_AF_STDBY__A 0x187002C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300118#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300119#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300120#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300121#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300122#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300123#define IQM_AF_AMUX__A 0x187002D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300124#define IQM_AF_AMUX_SIGNAL2ADC 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300125#define IQM_AF_UPD_SEL__A 0x187002F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300126#define IQM_AF_INC_LCT__A 0x1870034
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300127#define IQM_AF_INC_BYPASS__A 0x1870036
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300128#define OFDM_CP_COMM_EXEC__A 0x2800000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300129#define OFDM_CP_COMM_EXEC_STOP 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300130#define OFDM_EC_SB_PRIOR__A 0x3410013
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300131#define OFDM_EC_SB_PRIOR_HI 0x0
132#define OFDM_EC_SB_PRIOR_LO 0x1
Mauro Carvalho Chehab8f3741e2013-03-20 06:15:45 -0300133#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017
134#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300135#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300136#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300137#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300138#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300139#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300140#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300141#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300142#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300143#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300144#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300145#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300146#define OFDM_LC_COMM_EXEC__A 0x3800000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300147#define OFDM_LC_COMM_EXEC_STOP 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300148#define OFDM_SC_COMM_EXEC__A 0x3C00000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300149#define OFDM_SC_COMM_EXEC_STOP 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300150#define OFDM_SC_COMM_STATE__A 0x3C00001
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300151#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300152#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300153#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300154#define OFDM_SC_RA_RAM_CMD__A 0x3C20043
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300155#define OFDM_SC_RA_RAM_CMD_NULL 0x0
156#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300157#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
158#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
159#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
160#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6
161#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7
162#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300163#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300164#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300165#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300166#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300167#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
168#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300169#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
170#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
171#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
172#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300173#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
174#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
175#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300176#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
177#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
178#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
179#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300180#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
181#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
182#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
183#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
184#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300185#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
186#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300187#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300188#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300189#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300190#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300191#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300192#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300193#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300194#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300195#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300196#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300197#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300198#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300199#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300200#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300201#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300202#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300203#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300204#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300205#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300206#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300207#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300208#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300209#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300210#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300211#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300212#define QAM_COMM_EXEC__A 0x1400000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300213#define QAM_COMM_EXEC_STOP 0x0
214#define QAM_COMM_EXEC_ACTIVE 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300215#define QAM_TOP_ANNEX_A 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300216#define QAM_TOP_ANNEX_C 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300217#define QAM_SL_ERR_POWER__A 0x1430017
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300218#define QAM_DQ_QUAL_FUN0__A 0x1440018
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300219#define QAM_DQ_QUAL_FUN1__A 0x1440019
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300220#define QAM_DQ_QUAL_FUN2__A 0x144001A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300221#define QAM_DQ_QUAL_FUN3__A 0x144001B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300222#define QAM_DQ_QUAL_FUN4__A 0x144001C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300223#define QAM_DQ_QUAL_FUN5__A 0x144001D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300224#define QAM_LC_MODE__A 0x1450010
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300225#define QAM_LC_QUAL_TAB0__A 0x1450018
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300226#define QAM_LC_QUAL_TAB1__A 0x1450019
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300227#define QAM_LC_QUAL_TAB2__A 0x145001A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300228#define QAM_LC_QUAL_TAB3__A 0x145001B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300229#define QAM_LC_QUAL_TAB4__A 0x145001C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300230#define QAM_LC_QUAL_TAB5__A 0x145001D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300231#define QAM_LC_QUAL_TAB6__A 0x145001E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300232#define QAM_LC_QUAL_TAB8__A 0x145001F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300233#define QAM_LC_QUAL_TAB9__A 0x1450020
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300234#define QAM_LC_QUAL_TAB10__A 0x1450021
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300235#define QAM_LC_QUAL_TAB12__A 0x1450022
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300236#define QAM_LC_QUAL_TAB15__A 0x1450023
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300237#define QAM_LC_QUAL_TAB16__A 0x1450024
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300238#define QAM_LC_QUAL_TAB20__A 0x1450025
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300239#define QAM_LC_QUAL_TAB25__A 0x1450026
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300240#define QAM_LC_LPF_FACTORP__A 0x1450028
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300241#define QAM_LC_LPF_FACTORI__A 0x1450029
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300242#define QAM_LC_RATE_LIMIT__A 0x145002A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300243#define QAM_LC_SYMBOL_FREQ__A 0x145002B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300244#define QAM_SY_TIMEOUT__A 0x1470011
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300245#define QAM_SY_TIMEOUT__PRE 0x3A98
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300246#define QAM_SY_SYNC_LWM__A 0x1470012
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300247#define QAM_SY_SYNC_AWM__A 0x1470013
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300248#define QAM_SY_SYNC_HWM__A 0x1470014
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300249#define QAM_SY_SP_INV__A 0x1470017
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300250#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300251#define SCU_COMM_EXEC__A 0x800000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300252#define SCU_COMM_EXEC_STOP 0x0
253#define SCU_COMM_EXEC_ACTIVE 0x1
254#define SCU_COMM_EXEC_HOLD 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300255#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300256#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300257#define SCU_RAM_GPIO__A 0x831EC7
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300258#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300259#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300260#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300261#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300262#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300263#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300264#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300265#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300266#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300267#define SCU_RAM_AGC_RF_MAX__A 0x831F1B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300268#define SCU_RAM_AGC_CONFIG__A 0x831F24
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300269#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300270#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300271#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300272#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300273#define SCU_RAM_AGC_KI__A 0x831F25
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300274#define SCU_RAM_AGC_KI_RF__B 4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300275#define SCU_RAM_AGC_KI_RF__M 0xF0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300276#define SCU_RAM_AGC_KI_IF__B 8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300277#define SCU_RAM_AGC_KI_IF__M 0xF00
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300278#define SCU_RAM_AGC_KI_RED__A 0x831F26
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300279#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300280#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300281#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300282#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300283#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300284#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300285#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300286#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300287#define SCU_RAM_AGC_KI_MIN__A 0x831F2B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300288#define SCU_RAM_AGC_KI_MAX__A 0x831F2C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300289#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300290#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300291#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300292#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300293#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300294#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300295#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300296#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300297#define SCU_RAM_AGC_SNS_SUM__A 0x831F35
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300298#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300299#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300300#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300301#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300302#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300303#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300304#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300305#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300306#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300307#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300308#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300309#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300310#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300311#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300312#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300313#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300314#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300315#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300316#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300317#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300318#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300319#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300320#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300321#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300322#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300323#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300324#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300325#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300326#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300327#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300328#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300329#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300330#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300331#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300332#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300333#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300334#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300335#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300336#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300337#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300338#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300339#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300340#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300341#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300342#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300343#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300344#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300345#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300346#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300347#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300348#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300349#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300350#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300351#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300352#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300353#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300354#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300355#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300356#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300357#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300358#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000
359#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000
360#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300361#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300362#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300363#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300364#define SCU_RAM_PARAM_15__A 0x831FED
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300365#define SCU_RAM_PARAM_0__A 0x831FFC
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300366#define SCU_RAM_COMMAND__A 0x831FFD
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300367#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
368#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
369#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3
370#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
371#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300372#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300373#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300374#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300375#define SIO_TOP_COMM_KEY__A 0x41000F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300376#define SIO_TOP_COMM_KEY_KEY 0xFABA
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300377#define SIO_TOP_JTAGID_LO__A 0x410012
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300378#define SIO_HI_RA_RAM_RES__A 0x420031
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300379#define SIO_HI_RA_RAM_CMD__A 0x420032
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300380#define SIO_HI_RA_RAM_CMD_RESET 0x2
381#define SIO_HI_RA_RAM_CMD_CONFIG 0x3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300382#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300383#define SIO_HI_RA_RAM_PAR_1__A 0x420033
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300384#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300385#define SIO_HI_RA_RAM_PAR_2__A 0x420034
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300386#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300387#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
388#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300389#define SIO_HI_RA_RAM_PAR_3__A 0x420035
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300390#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300391#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300392#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
393#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300394#define SIO_HI_RA_RAM_PAR_4__A 0x420036
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300395#define SIO_HI_RA_RAM_PAR_5__A 0x420037
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300396#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300397#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300398#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300399#define SIO_HI_RA_RAM_PAR_6__A 0x420038
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300400#define SIO_CC_PLL_LOCK__A 0x450012
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300401#define SIO_CC_PWD_MODE__A 0x450015
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300402#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
403#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1
404#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
405#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3
406#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300407#define SIO_CC_SOFT_RST__A 0x450016
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300408#define SIO_CC_SOFT_RST_OFDM__M 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300409#define SIO_CC_SOFT_RST_SYS__M 0x2
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300410#define SIO_CC_SOFT_RST_OSC__M 0x4
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300411#define SIO_CC_UPDATE__A 0x450017
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300412#define SIO_CC_UPDATE_KEY 0xFABA
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300413#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300414#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
415#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300416#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300417#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0
418#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300419#define SIO_BL_COMM_EXEC__A 0x480000
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300420#define SIO_BL_COMM_EXEC_ACTIVE 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300421#define SIO_BL_STATUS__A 0x480010
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300422#define SIO_BL_MODE__A 0x480011
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300423#define SIO_BL_MODE_DIRECT 0x0
424#define SIO_BL_MODE_CHAIN 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300425#define SIO_BL_ENABLE__A 0x480012
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300426#define SIO_BL_ENABLE_ON 0x1
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300427#define SIO_BL_TGT_HDR__A 0x480014
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300428#define SIO_BL_TGT_ADDR__A 0x480015
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300429#define SIO_BL_SRC_ADDR__A 0x480016
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300430#define SIO_BL_SRC_LEN__A 0x480017
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300431#define SIO_BL_CHAIN_ADDR__A 0x480018
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300432#define SIO_BL_CHAIN_LEN__A 0x480019
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300433#define SIO_PDR_MON_CFG__A 0x7F0010
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300434#define SIO_PDR_UIO_IN_HI__A 0x7F0015
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300435#define SIO_PDR_UIO_OUT_LO__A 0x7F0016
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300436#define SIO_PDR_OHW_CFG__A 0x7F001F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300437#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3
Antti Palosaari14053442012-05-17 18:26:50 -0300438#define SIO_PDR_GPIO_CFG__A 0x7F0021
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300439#define SIO_PDR_MSTRT_CFG__A 0x7F0025
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300440#define SIO_PDR_MERR_CFG__A 0x7F0026
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300441#define SIO_PDR_MCLK_CFG__A 0x7F0028
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300442#define SIO_PDR_MCLK_CFG_DRIVE__B 3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300443#define SIO_PDR_MVAL_CFG__A 0x7F0029
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300444#define SIO_PDR_MD0_CFG__A 0x7F002A
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300445#define SIO_PDR_MD0_CFG_DRIVE__B 3
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300446#define SIO_PDR_MD1_CFG__A 0x7F002B
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300447#define SIO_PDR_MD2_CFG__A 0x7F002C
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300448#define SIO_PDR_MD3_CFG__A 0x7F002D
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300449#define SIO_PDR_MD4_CFG__A 0x7F002F
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300450#define SIO_PDR_MD5_CFG__A 0x7F0030
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300451#define SIO_PDR_MD6_CFG__A 0x7F0031
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300452#define SIO_PDR_MD7_CFG__A 0x7F0032
Antti Palosaari14053442012-05-17 18:26:50 -0300453#define SIO_PDR_SMA_RX_CFG__A 0x7F0037
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300454#define SIO_PDR_SMA_TX_CFG__A 0x7F0038