| Stephen Warren | be944d4 | 2012-04-10 16:31:59 -0600 | [diff] [blame] | 1 | /* |
| 2 | * tegra30_ahub.h - Definitions for Tegra30 AHUB driver |
| 3 | * |
| 4 | * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __TEGRA30_AHUB_H__ |
| 20 | #define __TEGRA30_AHUB_H__ |
| 21 | |
| 22 | /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ |
| 23 | |
| 24 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 |
| 25 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf |
| 26 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
| 27 | |
| 28 | /* Channel count minus 1 */ |
| 29 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 |
| 30 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 |
| 31 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
| 32 | |
| 33 | /* Channel count minus 1 */ |
| 34 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 |
| 35 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 |
| 36 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
| 37 | |
| 38 | #define TEGRA30_AUDIOCIF_BITS_4 0 |
| 39 | #define TEGRA30_AUDIOCIF_BITS_8 1 |
| 40 | #define TEGRA30_AUDIOCIF_BITS_12 2 |
| 41 | #define TEGRA30_AUDIOCIF_BITS_16 3 |
| 42 | #define TEGRA30_AUDIOCIF_BITS_20 4 |
| 43 | #define TEGRA30_AUDIOCIF_BITS_24 5 |
| 44 | #define TEGRA30_AUDIOCIF_BITS_28 6 |
| 45 | #define TEGRA30_AUDIOCIF_BITS_32 7 |
| 46 | |
| 47 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 |
| 48 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 49 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 50 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 51 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 52 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 53 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 54 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 55 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 56 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
| 57 | |
| 58 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 |
| 59 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 60 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 61 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 62 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 63 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 64 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 65 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 66 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 67 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
| 68 | |
| 69 | #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 |
| 70 | #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 |
| 71 | #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2 |
| 72 | |
| 73 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6 |
| 74 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
| 75 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
| 76 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
| 77 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
| 78 | |
| 79 | #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0 |
| 80 | #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1 |
| 81 | #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2 |
| 82 | |
| 83 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 |
| 84 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
| 85 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
| 86 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
| 87 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
| 88 | |
| 89 | #define TEGRA30_AUDIOCIF_CTRL_REPLICATE 3 |
| 90 | |
| 91 | #define TEGRA30_AUDIOCIF_DIRECTION_TX 0 |
| 92 | #define TEGRA30_AUDIOCIF_DIRECTION_RX 1 |
| 93 | |
| 94 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2 |
| 95 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
| 96 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
| 97 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
| 98 | |
| 99 | #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0 |
| 100 | #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1 |
| 101 | |
| 102 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 |
| 103 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
| 104 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
| 105 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
| 106 | |
| 107 | #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0 |
| 108 | #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1 |
| 109 | |
| 110 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 |
| 111 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) |
| 112 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) |
| 113 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) |
| 114 | |
| 115 | /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ |
| 116 | |
| 117 | /* TEGRA30_AHUB_CHANNEL_CTRL */ |
| 118 | |
| 119 | #define TEGRA30_AHUB_CHANNEL_CTRL 0x0 |
| 120 | #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20 |
| 121 | #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4 |
| 122 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31) |
| 123 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30) |
| 124 | #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29) |
| 125 | |
| 126 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16 |
| 127 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff |
| 128 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) |
| 129 | |
| 130 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8 |
| 131 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff |
| 132 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) |
| 133 | |
| 134 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6) |
| 135 | |
| 136 | #define TEGRA30_PACK_8_4 2 |
| 137 | #define TEGRA30_PACK_16 3 |
| 138 | |
| 139 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4 |
| 140 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3 |
| 141 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) |
| 142 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) |
| 143 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) |
| 144 | |
| 145 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2) |
| 146 | |
| 147 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0 |
| 148 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3 |
| 149 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) |
| 150 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) |
| 151 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) |
| 152 | |
| 153 | /* TEGRA30_AHUB_CHANNEL_CLEAR */ |
| 154 | |
| 155 | #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4 |
| 156 | #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20 |
| 157 | #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4 |
| 158 | #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31) |
| 159 | #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30) |
| 160 | |
| 161 | /* TEGRA30_AHUB_CHANNEL_STATUS */ |
| 162 | |
| 163 | #define TEGRA30_AHUB_CHANNEL_STATUS 0x8 |
| 164 | #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20 |
| 165 | #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4 |
| 166 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24 |
| 167 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff |
| 168 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT) |
| 169 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16 |
| 170 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff |
| 171 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT) |
| 172 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1) |
| 173 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0) |
| 174 | |
| 175 | /* TEGRA30_AHUB_CHANNEL_TXFIFO */ |
| 176 | |
| 177 | #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc |
| 178 | #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20 |
| 179 | #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4 |
| 180 | |
| 181 | /* TEGRA30_AHUB_CHANNEL_RXFIFO */ |
| 182 | |
| 183 | #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10 |
| 184 | #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20 |
| 185 | #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4 |
| 186 | |
| 187 | /* TEGRA30_AHUB_CIF_TX_CTRL */ |
| 188 | |
| 189 | #define TEGRA30_AHUB_CIF_TX_CTRL 0x14 |
| 190 | #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20 |
| 191 | #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4 |
| 192 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ |
| 193 | |
| 194 | /* TEGRA30_AHUB_CIF_RX_CTRL */ |
| 195 | |
| 196 | #define TEGRA30_AHUB_CIF_RX_CTRL 0x18 |
| 197 | #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20 |
| 198 | #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4 |
| 199 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ |
| 200 | |
| 201 | /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ |
| 202 | |
| 203 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80 |
| 204 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28 |
| 205 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf |
| 206 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT) |
| 207 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16 |
| 208 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff |
| 209 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT) |
| 210 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4 |
| 211 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff |
| 212 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT) |
| 213 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2) |
| 214 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1) |
| 215 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0) |
| 216 | |
| 217 | /* TEGRA30_AHUB_MISC_CTRL */ |
| 218 | |
| 219 | #define TEGRA30_AHUB_MISC_CTRL 0x84 |
| 220 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31) |
| 221 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8) |
| 222 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0 |
| 223 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT) |
| 224 | |
| 225 | /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ |
| 226 | |
| 227 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88 |
| 228 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31) |
| 229 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30) |
| 230 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29) |
| 231 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28) |
| 232 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27) |
| 233 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26) |
| 234 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25) |
| 235 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24) |
| 236 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23) |
| 237 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22) |
| 238 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21) |
| 239 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20) |
| 240 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19) |
| 241 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18) |
| 242 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17) |
| 243 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16) |
| 244 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15) |
| 245 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14) |
| 246 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13) |
| 247 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12) |
| 248 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11) |
| 249 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10) |
| 250 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9) |
| 251 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8) |
| 252 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7) |
| 253 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6) |
| 254 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5) |
| 255 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4) |
| 256 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3) |
| 257 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2) |
| 258 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1) |
| 259 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0) |
| 260 | |
| 261 | /* TEGRA30_AHUB_I2S_LIVE_STATUS */ |
| 262 | |
| 263 | #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c |
| 264 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29) |
| 265 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28) |
| 266 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27) |
| 267 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26) |
| 268 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25) |
| 269 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24) |
| 270 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23) |
| 271 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22) |
| 272 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21) |
| 273 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20) |
| 274 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19) |
| 275 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18) |
| 276 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17) |
| 277 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16) |
| 278 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15) |
| 279 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14) |
| 280 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13) |
| 281 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12) |
| 282 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11) |
| 283 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10) |
| 284 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9) |
| 285 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8) |
| 286 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7) |
| 287 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6) |
| 288 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5) |
| 289 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4) |
| 290 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3) |
| 291 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2) |
| 292 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1) |
| 293 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0) |
| 294 | |
| 295 | /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ |
| 296 | |
| 297 | #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90 |
| 298 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8 |
| 299 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3 |
| 300 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26) |
| 301 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25) |
| 302 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24) |
| 303 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15) |
| 304 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9) |
| 305 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8) |
| 306 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7) |
| 307 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1) |
| 308 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0) |
| 309 | |
| 310 | /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ |
| 311 | |
| 312 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8 |
| 313 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11) |
| 314 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) |
| 315 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) |
| 316 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) |
| 317 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) |
| 318 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) |
| 319 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) |
| 320 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) |
| 321 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) |
| 322 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) |
| 323 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) |
| 324 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) |
| 325 | |
| 326 | /* TEGRA30_AHUB_I2S_INT_MASK */ |
| 327 | |
| 328 | #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 |
| 329 | |
| 330 | /* TEGRA30_AHUB_DAM_INT_MASK */ |
| 331 | |
| 332 | #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 |
| 333 | |
| 334 | /* TEGRA30_AHUB_SPDIF_INT_MASK */ |
| 335 | |
| 336 | #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc |
| 337 | |
| 338 | /* TEGRA30_AHUB_APBIF_INT_MASK */ |
| 339 | |
| 340 | #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 |
| 341 | |
| 342 | /* TEGRA30_AHUB_I2S_INT_STATUS */ |
| 343 | |
| 344 | #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 |
| 345 | |
| 346 | /* TEGRA30_AHUB_DAM_INT_STATUS */ |
| 347 | |
| 348 | #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc |
| 349 | |
| 350 | /* TEGRA30_AHUB_SPDIF_INT_STATUS */ |
| 351 | |
| 352 | #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 |
| 353 | |
| 354 | /* TEGRA30_AHUB_APBIF_INT_STATUS */ |
| 355 | |
| 356 | #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 |
| 357 | |
| 358 | /* TEGRA30_AHUB_I2S_INT_SOURCE */ |
| 359 | |
| 360 | #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 |
| 361 | |
| 362 | /* TEGRA30_AHUB_DAM_INT_SOURCE */ |
| 363 | |
| 364 | #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 |
| 365 | |
| 366 | /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ |
| 367 | |
| 368 | #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec |
| 369 | |
| 370 | /* TEGRA30_AHUB_APBIF_INT_SOURCE */ |
| 371 | |
| 372 | #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 |
| 373 | |
| 374 | /* TEGRA30_AHUB_I2S_INT_SET */ |
| 375 | |
| 376 | #define TEGRA30_AHUB_I2S_INT_SET 0xf8 |
| 377 | |
| 378 | /* TEGRA30_AHUB_DAM_INT_SET */ |
| 379 | |
| 380 | #define TEGRA30_AHUB_DAM_INT_SET 0xfc |
| 381 | |
| 382 | /* TEGRA30_AHUB_SPDIF_INT_SET */ |
| 383 | |
| 384 | #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 |
| 385 | |
| 386 | /* TEGRA30_AHUB_APBIF_INT_SET */ |
| 387 | |
| 388 | #define TEGRA30_AHUB_APBIF_INT_SET 0x104 |
| 389 | |
| 390 | /* Registers within TEGRA30_AHUB_BASE */ |
| 391 | |
| 392 | #define TEGRA30_AHUB_AUDIO_RX 0x0 |
| 393 | #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 |
| 394 | #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 |
| 395 | /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ |
| 396 | /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ |
| 397 | |
| 398 | /* |
| 399 | * Terminology: |
| 400 | * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, |
| 401 | * I2S controllers, SPDIF controllers, and DAMs. |
| 402 | * XBAR: The core cross-bar component of the AHUB. |
| 403 | * CIF: Client Interface; the HW module connecting an audio device to the |
| 404 | * XBAR. |
| 405 | * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, |
| 406 | * possibly including sample-rate conversion. |
| 407 | * |
| 408 | * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio |
| 409 | * transmitted by a particular TX CIF. |
| 410 | * |
| 411 | * This driver is currently very simplistic; many HW features are not |
| 412 | * exposed; DAMs are not supported, only 16-bit stereo audio is supported, |
| 413 | * etc. |
| 414 | */ |
| 415 | |
| 416 | enum tegra30_ahub_txcif { |
| 417 | TEGRA30_AHUB_TXCIF_APBIF_TX0, |
| 418 | TEGRA30_AHUB_TXCIF_APBIF_TX1, |
| 419 | TEGRA30_AHUB_TXCIF_APBIF_TX2, |
| 420 | TEGRA30_AHUB_TXCIF_APBIF_TX3, |
| 421 | TEGRA30_AHUB_TXCIF_I2S0_TX0, |
| 422 | TEGRA30_AHUB_TXCIF_I2S1_TX0, |
| 423 | TEGRA30_AHUB_TXCIF_I2S2_TX0, |
| 424 | TEGRA30_AHUB_TXCIF_I2S3_TX0, |
| 425 | TEGRA30_AHUB_TXCIF_I2S4_TX0, |
| 426 | TEGRA30_AHUB_TXCIF_DAM0_TX0, |
| 427 | TEGRA30_AHUB_TXCIF_DAM1_TX0, |
| 428 | TEGRA30_AHUB_TXCIF_DAM2_TX0, |
| 429 | TEGRA30_AHUB_TXCIF_SPDIF_TX0, |
| 430 | TEGRA30_AHUB_TXCIF_SPDIF_TX1, |
| 431 | }; |
| 432 | |
| 433 | enum tegra30_ahub_rxcif { |
| 434 | TEGRA30_AHUB_RXCIF_APBIF_RX0, |
| 435 | TEGRA30_AHUB_RXCIF_APBIF_RX1, |
| 436 | TEGRA30_AHUB_RXcIF_APBIF_RX2, |
| 437 | TEGRA30_AHUB_RXCIF_APBIF_RX3, |
| 438 | TEGRA30_AHUB_RXCIF_I2S0_RX0, |
| 439 | TEGRA30_AHUB_RXCIF_I2S1_RX0, |
| 440 | TEGRA30_AHUB_RXCIF_I2S2_RX0, |
| 441 | TEGRA30_AHUB_RXCIF_I2S3_RX0, |
| 442 | TEGRA30_AHUB_RXCIF_I2S4_RX0, |
| 443 | TEGRA30_AHUB_RXCIF_DAM0_RX0, |
| 444 | TEGRA30_AHUB_RXCIF_DAM0_RX1, |
| 445 | TEGRA30_AHUB_RXCIF_DAM1_RX0, |
| 446 | TEGRA30_AHUB_RXCIF_DAM2_RX1, |
| 447 | TEGRA30_AHUB_RXCIF_DAM3_RX0, |
| 448 | TEGRA30_AHUB_RXCIF_DAM3_RX1, |
| 449 | TEGRA30_AHUB_RXCIF_SPDIF_RX0, |
| 450 | TEGRA30_AHUB_RXCIF_SPDIF_RX1, |
| 451 | }; |
| 452 | |
| 453 | extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, |
| 454 | unsigned long *fiforeg, |
| 455 | unsigned long *reqsel); |
| 456 | extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
| 457 | extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
| 458 | extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
| 459 | |
| 460 | extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, |
| 461 | unsigned long *fiforeg, |
| 462 | unsigned long *reqsel); |
| 463 | extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); |
| 464 | extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); |
| 465 | extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); |
| 466 | |
| 467 | extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, |
| 468 | enum tegra30_ahub_txcif txcif); |
| 469 | extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); |
| 470 | |
| 471 | struct tegra30_ahub { |
| 472 | struct device *dev; |
| 473 | struct clk *clk_d_audio; |
| 474 | struct clk *clk_apbif; |
| 475 | int dma_sel; |
| 476 | resource_size_t apbif_addr; |
| 477 | struct regmap *regmap_apbif; |
| 478 | struct regmap *regmap_ahub; |
| 479 | DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); |
| 480 | DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); |
| 481 | }; |
| 482 | |
| 483 | #endif |