blob: bbce47dc79e648d1e6b06f697193297436b1982f [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
29
Thierry Reding08943e62013-09-26 16:08:18 +020030struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010031 struct idr contexts;
32 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020033};
34
Thierry Reding1503ca42014-11-24 17:41:23 +010035static void tegra_atomic_schedule(struct tegra_drm *tegra,
36 struct drm_atomic_state *state)
37{
38 tegra->commit.state = state;
39 schedule_work(&tegra->commit.work);
40}
41
42static void tegra_atomic_complete(struct tegra_drm *tegra,
43 struct drm_atomic_state *state)
44{
45 struct drm_device *drm = tegra->drm;
46
47 /*
48 * Everything below can be run asynchronously without the need to grab
49 * any modeset locks at all under one condition: It must be guaranteed
50 * that the asynchronous work has either been cancelled (if the driver
51 * supports it, which at least requires that the framebuffers get
52 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
53 * before the new state gets committed on the software side with
54 * drm_atomic_helper_swap_state().
55 *
56 * This scheme allows new atomic state updates to be prepared and
57 * checked in parallel to the asynchronous completion of the previous
58 * update. Which is important since compositors need to figure out the
59 * composition of the next frame right after having submitted the
60 * current layout.
61 */
62
Daniel Vetter1af434a2015-02-22 12:24:19 +010063 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010064 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080065 drm_atomic_helper_commit_planes(drm, state,
66 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010067
68 drm_atomic_helper_wait_for_vblanks(drm, state);
69
70 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010071 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010072}
73
74static void tegra_atomic_work(struct work_struct *work)
75{
76 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
77 commit.work);
78
79 tegra_atomic_complete(tegra, tegra->commit.state);
80}
81
82static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020083 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010084{
85 struct tegra_drm *tegra = drm->dev_private;
86 int err;
87
88 err = drm_atomic_helper_prepare_planes(drm, state);
89 if (err)
90 return err;
91
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020092 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010093 mutex_lock(&tegra->commit.lock);
94 flush_work(&tegra->commit.work);
95
96 /*
97 * This is the point of no return - everything below never fails except
98 * when the hw goes bonghits. Which means we can commit the new state on
99 * the software side now.
100 */
101
Daniel Vetter5e84c262016-06-10 00:06:32 +0200102 drm_atomic_helper_swap_state(state, true);
Thierry Reding1503ca42014-11-24 17:41:23 +0100103
Chris Wilson08536952016-10-14 13:18:18 +0100104 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200105 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100106 tegra_atomic_schedule(tegra, state);
107 else
108 tegra_atomic_complete(tegra, state);
109
110 mutex_unlock(&tegra->commit.lock);
111 return 0;
112}
113
Thierry Redingf9914212014-11-26 13:03:57 +0100114static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
115 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530116#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100117 .output_poll_changed = tegra_fb_output_poll_changed,
118#endif
Thierry Reding07866962014-11-24 17:08:06 +0100119 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100120 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100121};
122
Thierry Reding776dc382013-10-14 14:43:22 +0200123static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000124{
Thierry Reding776dc382013-10-14 14:43:22 +0200125 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200126 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000127 int err;
128
Thierry Reding776dc382013-10-14 14:43:22 +0200129 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200130 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200131 return -ENOMEM;
132
Thierry Redingdf06b752014-06-26 21:41:53 +0200133 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200134 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100135 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200136 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100137
Thierry Redingdf06b752014-06-26 21:41:53 +0200138 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300139 if (!tegra->domain) {
140 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200141 goto free;
142 }
143
Thierry Reding4553f732015-01-19 16:15:04 +0100144 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200145 gem_start = geometry->aperture_start;
146 gem_end = geometry->aperture_end - CARVEOUT_SZ;
147 carveout_start = gem_end + 1;
148 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100149
Mikko Perttunenad926012016-12-14 13:16:11 +0200150 order = __ffs(tegra->domain->pgsize_bitmap);
151 init_iova_domain(&tegra->carveout.domain, 1UL << order,
152 carveout_start >> order,
153 carveout_end >> order);
154
155 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
156 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
157
158 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100159 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200160
161 DRM_DEBUG("IOMMU apertures:\n");
162 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
163 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
164 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200165 }
166
Thierry Reding386a2a72013-09-24 13:22:17 +0200167 mutex_init(&tegra->clients_lock);
168 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100169
170 mutex_init(&tegra->commit.lock);
171 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
172
Thierry Reding386a2a72013-09-24 13:22:17 +0200173 drm->dev_private = tegra;
174 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000175
176 drm_mode_config_init(drm);
177
Thierry Redingf9914212014-11-26 13:03:57 +0100178 drm->mode_config.min_width = 0;
179 drm->mode_config.min_height = 0;
180
181 drm->mode_config.max_width = 4096;
182 drm->mode_config.max_height = 4096;
183
Alexandre Courbot5e911442016-11-08 16:50:42 +0900184 drm->mode_config.allow_fb_modifiers = true;
185
Thierry Redingf9914212014-11-26 13:03:57 +0100186 drm->mode_config.funcs = &tegra_drm_mode_funcs;
187
Thierry Redinge2215322014-06-27 17:19:25 +0200188 err = tegra_drm_fb_prepare(drm);
189 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100190 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200191
192 drm_kms_helper_poll_init(drm);
193
Thierry Reding776dc382013-10-14 14:43:22 +0200194 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000195 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100196 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197
Thierry Reding603f0cc2013-04-22 21:22:14 +0200198 /*
199 * We don't use the drm_irq_install() helpers provided by the DRM
200 * core, so we need to set this manually in order to allow the
201 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
202 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300203 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200204
Thierry Reding42e9ce02015-01-28 14:43:05 +0100205 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100206 drm->max_vblank_count = 0xffffffff;
207
Thierry Reding6e5ff992012-11-28 11:45:47 +0100208 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
209 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100210 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100211
Thierry Reding31930d42015-07-02 17:04:06 +0200212 drm_mode_config_reset(drm);
213
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000214 err = tegra_drm_fb_init(drm);
215 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100216 goto vblank;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100219
220vblank:
221 drm_vblank_cleanup(drm);
222device:
223 host1x_device_exit(device);
224fbdev:
225 drm_kms_helper_poll_fini(drm);
226 tegra_drm_fb_free(drm);
227config:
228 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200229
230 if (tegra->domain) {
231 iommu_domain_free(tegra->domain);
232 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100233 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200234 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200235 }
236free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100237 kfree(tegra);
238 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000239}
240
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200241static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000242{
Thierry Reding776dc382013-10-14 14:43:22 +0200243 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200244 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200245 int err;
246
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000247 drm_kms_helper_poll_fini(drm);
248 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200249 drm_mode_config_cleanup(drm);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100250 drm_vblank_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000251
Thierry Reding776dc382013-10-14 14:43:22 +0200252 err = host1x_device_exit(device);
253 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200254 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200255
Thierry Redingdf06b752014-06-26 21:41:53 +0200256 if (tegra->domain) {
257 iommu_domain_free(tegra->domain);
258 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100259 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200260 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200261 }
262
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100263 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000264}
265
266static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
267{
Thierry Reding08943e62013-09-26 16:08:18 +0200268 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200269
270 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
271 if (!fpriv)
272 return -ENOMEM;
273
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100274 idr_init(&fpriv->contexts);
275 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200276 filp->driver_priv = fpriv;
277
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000278 return 0;
279}
280
Thierry Redingc88c3632013-09-26 16:08:22 +0200281static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200282{
283 context->client->ops->close_channel(context);
284 kfree(context);
285}
286
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000287static void tegra_drm_lastclose(struct drm_device *drm)
288{
Archit Tanejab110ef32015-10-27 13:40:59 +0530289#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200290 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000291
Thierry Reding386a2a72013-09-24 13:22:17 +0200292 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100293#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000294}
295
Thierry Redingc40f0f12013-10-10 11:00:33 +0200296static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100297host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200298{
299 struct drm_gem_object *gem;
300 struct tegra_bo *bo;
301
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100302 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200303 if (!gem)
304 return NULL;
305
Daniel Vettera07cdfe2015-11-23 10:32:48 +0100306 drm_gem_object_unreference_unlocked(gem);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200307
308 bo = to_tegra_bo(gem);
309 return &bo->base;
310}
311
Thierry Reding961e3be2014-06-10 10:25:00 +0200312static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
313 struct drm_tegra_reloc __user *src,
314 struct drm_device *drm,
315 struct drm_file *file)
316{
317 u32 cmdbuf, target;
318 int err;
319
320 err = get_user(cmdbuf, &src->cmdbuf.handle);
321 if (err < 0)
322 return err;
323
324 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
325 if (err < 0)
326 return err;
327
328 err = get_user(target, &src->target.handle);
329 if (err < 0)
330 return err;
331
David Ung31f40f82015-01-20 18:37:35 -0800332 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200333 if (err < 0)
334 return err;
335
336 err = get_user(dest->shift, &src->shift);
337 if (err < 0)
338 return err;
339
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100340 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200341 if (!dest->cmdbuf.bo)
342 return -ENOENT;
343
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100344 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200345 if (!dest->target.bo)
346 return -ENOENT;
347
348 return 0;
349}
350
Thierry Redingc40f0f12013-10-10 11:00:33 +0200351int tegra_drm_submit(struct tegra_drm_context *context,
352 struct drm_tegra_submit *args, struct drm_device *drm,
353 struct drm_file *file)
354{
355 unsigned int num_cmdbufs = args->num_cmdbufs;
356 unsigned int num_relocs = args->num_relocs;
357 unsigned int num_waitchks = args->num_waitchks;
358 struct drm_tegra_cmdbuf __user *cmdbufs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100359 (void __user *)(uintptr_t)args->cmdbufs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200360 struct drm_tegra_reloc __user *relocs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100361 (void __user *)(uintptr_t)args->relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200362 struct drm_tegra_waitchk __user *waitchks =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100363 (void __user *)(uintptr_t)args->waitchks;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200364 struct drm_tegra_syncpt syncpt;
365 struct host1x_job *job;
366 int err;
367
368 /* We don't yet support other than one syncpt_incr struct per submit */
369 if (args->num_syncpts != 1)
370 return -EINVAL;
371
372 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
373 args->num_relocs, args->num_waitchks);
374 if (!job)
375 return -ENOMEM;
376
377 job->num_relocs = args->num_relocs;
378 job->num_waitchk = args->num_waitchks;
379 job->client = (u32)args->context;
380 job->class = context->client->base.class;
381 job->serialize = true;
382
383 while (num_cmdbufs) {
384 struct drm_tegra_cmdbuf cmdbuf;
385 struct host1x_bo *bo;
386
Dan Carpenter9a991602013-11-08 13:07:37 +0300387 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
388 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200389 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300390 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200391
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100392 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200393 if (!bo) {
394 err = -ENOENT;
395 goto fail;
396 }
397
398 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
399 num_cmdbufs--;
400 cmdbufs++;
401 }
402
Thierry Reding961e3be2014-06-10 10:25:00 +0200403 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200404 while (num_relocs--) {
Thierry Reding961e3be2014-06-10 10:25:00 +0200405 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
406 &relocs[num_relocs], drm,
407 file);
408 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200409 goto fail;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200410 }
411
Dan Carpenter9a991602013-11-08 13:07:37 +0300412 if (copy_from_user(job->waitchk, waitchks,
413 sizeof(*waitchks) * num_waitchks)) {
414 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200415 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300416 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200417
Dan Carpenter9a991602013-11-08 13:07:37 +0300418 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
419 sizeof(syncpt))) {
420 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200421 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300422 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200423
424 job->is_addr_reg = context->client->ops->is_addr_reg;
425 job->syncpt_incrs = syncpt.incrs;
426 job->syncpt_id = syncpt.id;
427 job->timeout = 10000;
428
429 if (args->timeout && args->timeout < 10000)
430 job->timeout = args->timeout;
431
432 err = host1x_job_pin(job, context->client->base.dev);
433 if (err)
434 goto fail;
435
436 err = host1x_job_submit(job);
437 if (err)
438 goto fail_submit;
439
440 args->fence = job->syncpt_end;
441
442 host1x_job_put(job);
443 return 0;
444
445fail_submit:
446 host1x_job_unpin(job);
447fail:
448 host1x_job_put(job);
449 return err;
450}
451
452
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200453#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100454static struct tegra_drm_context *
455tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200456{
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100457 struct tegra_drm_context *context;
Thierry Redingc88c3632013-09-26 16:08:22 +0200458
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100459 mutex_lock(&file->lock);
460 context = idr_find(&file->contexts, id);
461 mutex_unlock(&file->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200462
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100463 return context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200464}
465
466static int tegra_gem_create(struct drm_device *drm, void *data,
467 struct drm_file *file)
468{
469 struct drm_tegra_gem_create *args = data;
470 struct tegra_bo *bo;
471
Thierry Reding773af772013-10-04 22:34:01 +0200472 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200473 &args->handle);
474 if (IS_ERR(bo))
475 return PTR_ERR(bo);
476
477 return 0;
478}
479
480static int tegra_gem_mmap(struct drm_device *drm, void *data,
481 struct drm_file *file)
482{
483 struct drm_tegra_gem_mmap *args = data;
484 struct drm_gem_object *gem;
485 struct tegra_bo *bo;
486
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100487 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200488 if (!gem)
489 return -EINVAL;
490
491 bo = to_tegra_bo(gem);
492
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200493 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200494
Daniel Vetter11533302015-11-23 10:32:40 +0100495 drm_gem_object_unreference_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200496
497 return 0;
498}
499
500static int tegra_syncpt_read(struct drm_device *drm, void *data,
501 struct drm_file *file)
502{
Thierry Reding776dc382013-10-14 14:43:22 +0200503 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200504 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200505 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200506
Thierry Reding776dc382013-10-14 14:43:22 +0200507 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200508 if (!sp)
509 return -EINVAL;
510
511 args->value = host1x_syncpt_read_min(sp);
512 return 0;
513}
514
515static int tegra_syncpt_incr(struct drm_device *drm, void *data,
516 struct drm_file *file)
517{
Thierry Reding776dc382013-10-14 14:43:22 +0200518 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200519 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200520 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200521
Thierry Reding776dc382013-10-14 14:43:22 +0200522 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200523 if (!sp)
524 return -EINVAL;
525
Arto Merilainenebae30b2013-05-29 13:26:08 +0300526 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200527}
528
529static int tegra_syncpt_wait(struct drm_device *drm, void *data,
530 struct drm_file *file)
531{
Thierry Reding776dc382013-10-14 14:43:22 +0200532 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200533 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200534 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200535
Thierry Reding776dc382013-10-14 14:43:22 +0200536 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200537 if (!sp)
538 return -EINVAL;
539
540 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
541 &args->value);
542}
543
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100544static int tegra_client_open(struct tegra_drm_file *fpriv,
545 struct tegra_drm_client *client,
546 struct tegra_drm_context *context)
547{
548 int err;
549
550 err = client->ops->open_channel(client, context);
551 if (err < 0)
552 return err;
553
554 err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
555 if (err < 0) {
556 client->ops->close_channel(context);
557 return err;
558 }
559
560 context->client = client;
561 context->id = err;
562
563 return 0;
564}
565
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200566static int tegra_open_channel(struct drm_device *drm, void *data,
567 struct drm_file *file)
568{
Thierry Reding08943e62013-09-26 16:08:18 +0200569 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200570 struct tegra_drm *tegra = drm->dev_private;
571 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200572 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200573 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200574 int err = -ENODEV;
575
576 context = kzalloc(sizeof(*context), GFP_KERNEL);
577 if (!context)
578 return -ENOMEM;
579
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100580 mutex_lock(&fpriv->lock);
581
Thierry Reding776dc382013-10-14 14:43:22 +0200582 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200583 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100584 err = tegra_client_open(fpriv, client, context);
585 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200586 break;
587
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100588 args->context = context->id;
589 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200590 }
591
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100592 if (err < 0)
593 kfree(context);
594
595 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200596 return err;
597}
598
599static int tegra_close_channel(struct drm_device *drm, void *data,
600 struct drm_file *file)
601{
Thierry Reding08943e62013-09-26 16:08:18 +0200602 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200603 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200604 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100605 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200606
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100607 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200608
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100609 context = tegra_drm_file_get_context(fpriv, args->context);
610 if (!context) {
611 err = -EINVAL;
612 goto unlock;
613 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200614
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100615 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200616 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200617
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100618unlock:
619 mutex_unlock(&fpriv->lock);
620 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200621}
622
623static int tegra_get_syncpt(struct drm_device *drm, void *data,
624 struct drm_file *file)
625{
Thierry Reding08943e62013-09-26 16:08:18 +0200626 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200627 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200628 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100630 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100632 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200633
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100634 context = tegra_drm_file_get_context(fpriv, args->context);
635 if (!context) {
636 err = -ENODEV;
637 goto unlock;
638 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200639
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100640 if (args->index >= context->client->base.num_syncpts) {
641 err = -EINVAL;
642 goto unlock;
643 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200644
Thierry Reding53fa7f72013-09-24 15:35:40 +0200645 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200646 args->id = host1x_syncpt_id(syncpt);
647
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100648unlock:
649 mutex_unlock(&fpriv->lock);
650 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200651}
652
653static int tegra_submit(struct drm_device *drm, void *data,
654 struct drm_file *file)
655{
Thierry Reding08943e62013-09-26 16:08:18 +0200656 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200657 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200658 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100659 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200660
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100661 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200662
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100663 context = tegra_drm_file_get_context(fpriv, args->context);
664 if (!context) {
665 err = -ENODEV;
666 goto unlock;
667 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200668
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100669 err = context->client->ops->submit(context, args, drm, file);
670
671unlock:
672 mutex_unlock(&fpriv->lock);
673 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200674}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300675
676static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
677 struct drm_file *file)
678{
679 struct tegra_drm_file *fpriv = file->driver_priv;
680 struct drm_tegra_get_syncpt_base *args = data;
681 struct tegra_drm_context *context;
682 struct host1x_syncpt_base *base;
683 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100684 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300685
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100686 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300687
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100688 context = tegra_drm_file_get_context(fpriv, args->context);
689 if (!context) {
690 err = -ENODEV;
691 goto unlock;
692 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300693
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100694 if (args->syncpt >= context->client->base.num_syncpts) {
695 err = -EINVAL;
696 goto unlock;
697 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300698
699 syncpt = context->client->base.syncpts[args->syncpt];
700
701 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100702 if (!base) {
703 err = -ENXIO;
704 goto unlock;
705 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300706
707 args->id = host1x_syncpt_base_id(base);
708
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100709unlock:
710 mutex_unlock(&fpriv->lock);
711 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300712}
Thierry Reding7678d712014-06-03 14:56:57 +0200713
714static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
715 struct drm_file *file)
716{
717 struct drm_tegra_gem_set_tiling *args = data;
718 enum tegra_bo_tiling_mode mode;
719 struct drm_gem_object *gem;
720 unsigned long value = 0;
721 struct tegra_bo *bo;
722
723 switch (args->mode) {
724 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
725 mode = TEGRA_BO_TILING_MODE_PITCH;
726
727 if (args->value != 0)
728 return -EINVAL;
729
730 break;
731
732 case DRM_TEGRA_GEM_TILING_MODE_TILED:
733 mode = TEGRA_BO_TILING_MODE_TILED;
734
735 if (args->value != 0)
736 return -EINVAL;
737
738 break;
739
740 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
741 mode = TEGRA_BO_TILING_MODE_BLOCK;
742
743 if (args->value > 5)
744 return -EINVAL;
745
746 value = args->value;
747 break;
748
749 default:
750 return -EINVAL;
751 }
752
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100753 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200754 if (!gem)
755 return -ENOENT;
756
757 bo = to_tegra_bo(gem);
758
759 bo->tiling.mode = mode;
760 bo->tiling.value = value;
761
Daniel Vetter11533302015-11-23 10:32:40 +0100762 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200763
764 return 0;
765}
766
767static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
768 struct drm_file *file)
769{
770 struct drm_tegra_gem_get_tiling *args = data;
771 struct drm_gem_object *gem;
772 struct tegra_bo *bo;
773 int err = 0;
774
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100775 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200776 if (!gem)
777 return -ENOENT;
778
779 bo = to_tegra_bo(gem);
780
781 switch (bo->tiling.mode) {
782 case TEGRA_BO_TILING_MODE_PITCH:
783 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
784 args->value = 0;
785 break;
786
787 case TEGRA_BO_TILING_MODE_TILED:
788 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
789 args->value = 0;
790 break;
791
792 case TEGRA_BO_TILING_MODE_BLOCK:
793 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
794 args->value = bo->tiling.value;
795 break;
796
797 default:
798 err = -EINVAL;
799 break;
800 }
801
Daniel Vetter11533302015-11-23 10:32:40 +0100802 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200803
804 return err;
805}
Thierry Reding7b129082014-06-10 12:04:03 +0200806
807static int tegra_gem_set_flags(struct drm_device *drm, void *data,
808 struct drm_file *file)
809{
810 struct drm_tegra_gem_set_flags *args = data;
811 struct drm_gem_object *gem;
812 struct tegra_bo *bo;
813
814 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
815 return -EINVAL;
816
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100817 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200818 if (!gem)
819 return -ENOENT;
820
821 bo = to_tegra_bo(gem);
822 bo->flags = 0;
823
824 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
825 bo->flags |= TEGRA_BO_BOTTOM_UP;
826
Daniel Vetter11533302015-11-23 10:32:40 +0100827 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200828
829 return 0;
830}
831
832static int tegra_gem_get_flags(struct drm_device *drm, void *data,
833 struct drm_file *file)
834{
835 struct drm_tegra_gem_get_flags *args = data;
836 struct drm_gem_object *gem;
837 struct tegra_bo *bo;
838
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100839 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200840 if (!gem)
841 return -ENOENT;
842
843 bo = to_tegra_bo(gem);
844 args->flags = 0;
845
846 if (bo->flags & TEGRA_BO_BOTTOM_UP)
847 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
848
Daniel Vetter11533302015-11-23 10:32:40 +0100849 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200850
851 return 0;
852}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200853#endif
854
Rob Clarkbaa70942013-08-02 13:27:49 -0400855static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200856#ifdef CONFIG_DRM_TEGRA_STAGING
Daniel Vetterf8c47142015-09-08 13:56:30 +0200857 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
858 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
859 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
860 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
861 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
862 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
863 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
864 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
865 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
866 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
867 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
868 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
869 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
870 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200871#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000872};
873
874static const struct file_operations tegra_drm_fops = {
875 .owner = THIS_MODULE,
876 .open = drm_open,
877 .release = drm_release,
878 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200879 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000880 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000881 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000882 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000883 .llseek = noop_llseek,
884};
885
Thierry Reding88e72712015-09-24 18:35:31 +0200886static u32 tegra_drm_get_vblank_counter(struct drm_device *drm,
887 unsigned int pipe)
Thierry Reding6e5ff992012-11-28 11:45:47 +0100888{
Shawn Guo75bcb052017-01-09 19:25:44 +0800889 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
Thierry Reding42e9ce02015-01-28 14:43:05 +0100890 struct tegra_dc *dc = to_tegra_dc(crtc);
Thierry Redinged7dae52014-12-16 16:03:13 +0100891
892 if (!crtc)
893 return 0;
894
Thierry Reding42e9ce02015-01-28 14:43:05 +0100895 return tegra_dc_get_vblank_counter(dc);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100896}
897
Thierry Reding88e72712015-09-24 18:35:31 +0200898static int tegra_drm_enable_vblank(struct drm_device *drm, unsigned int pipe)
Thierry Reding6e5ff992012-11-28 11:45:47 +0100899{
Shawn Guo75bcb052017-01-09 19:25:44 +0800900 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100901 struct tegra_dc *dc = to_tegra_dc(crtc);
902
903 if (!crtc)
904 return -ENODEV;
905
906 tegra_dc_enable_vblank(dc);
907
908 return 0;
909}
910
Thierry Reding88e72712015-09-24 18:35:31 +0200911static void tegra_drm_disable_vblank(struct drm_device *drm, unsigned int pipe)
Thierry Reding6e5ff992012-11-28 11:45:47 +0100912{
Shawn Guo75bcb052017-01-09 19:25:44 +0800913 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100914 struct tegra_dc *dc = to_tegra_dc(crtc);
915
916 if (crtc)
917 tegra_dc_disable_vblank(dc);
918}
919
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100920static int tegra_drm_context_cleanup(int id, void *p, void *data)
921{
922 struct tegra_drm_context *context = p;
923
924 tegra_drm_context_free(context);
925
926 return 0;
927}
928
Thierry Reding3c03c462012-11-28 12:00:18 +0100929static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
930{
Thierry Reding08943e62013-09-26 16:08:18 +0200931 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100932
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100933 mutex_lock(&fpriv->lock);
934 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
935 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200936
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100937 idr_destroy(&fpriv->contexts);
938 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200939 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100940}
941
Thierry Redinge450fcc2013-02-13 16:13:16 +0100942#ifdef CONFIG_DEBUG_FS
943static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
944{
945 struct drm_info_node *node = (struct drm_info_node *)s->private;
946 struct drm_device *drm = node->minor->dev;
947 struct drm_framebuffer *fb;
948
949 mutex_lock(&drm->mode_config.fb_lock);
950
951 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
952 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200953 fb->base.id, fb->width, fb->height,
954 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200955 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000956 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100957 }
958
959 mutex_unlock(&drm->mode_config.fb_lock);
960
961 return 0;
962}
963
Thierry Reding28c23372015-01-23 09:16:03 +0100964static int tegra_debugfs_iova(struct seq_file *s, void *data)
965{
966 struct drm_info_node *node = (struct drm_info_node *)s->private;
967 struct drm_device *drm = node->minor->dev;
968 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100969 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100970
Thierry Reding347ad49d2017-03-09 20:04:56 +0100971 mutex_lock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +0100972 drm_mm_print(&tegra->mm, &p);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100973 mutex_unlock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +0100974
975 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100976}
977
Thierry Redinge450fcc2013-02-13 16:13:16 +0100978static struct drm_info_list tegra_debugfs_list[] = {
979 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100980 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100981};
982
983static int tegra_debugfs_init(struct drm_minor *minor)
984{
985 return drm_debugfs_create_files(tegra_debugfs_list,
986 ARRAY_SIZE(tegra_debugfs_list),
987 minor->debugfs_root, minor);
988}
Thierry Redinge450fcc2013-02-13 16:13:16 +0100989#endif
990
Thierry Reding9b57f5f2013-11-08 13:17:14 +0100991static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +0200992 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
993 DRIVER_ATOMIC,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000994 .load = tegra_drm_load,
995 .unload = tegra_drm_unload,
996 .open = tegra_drm_open,
Thierry Reding3c03c462012-11-28 12:00:18 +0100997 .preclose = tegra_drm_preclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000998 .lastclose = tegra_drm_lastclose,
999
Thierry Reding6e5ff992012-11-28 11:45:47 +01001000 .get_vblank_counter = tegra_drm_get_vblank_counter,
1001 .enable_vblank = tegra_drm_enable_vblank,
1002 .disable_vblank = tegra_drm_disable_vblank,
1003
Thierry Redinge450fcc2013-02-13 16:13:16 +01001004#if defined(CONFIG_DEBUG_FS)
1005 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001006#endif
1007
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001008 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001009 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001010
1011 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1012 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1013 .gem_prime_export = tegra_gem_prime_export,
1014 .gem_prime_import = tegra_gem_prime_import,
1015
Arto Merilainende2ba662013-03-22 16:34:08 +02001016 .dumb_create = tegra_bo_dumb_create,
1017 .dumb_map_offset = tegra_bo_dumb_map_offset,
Daniel Vetter43387b32013-07-16 09:12:04 +02001018 .dumb_destroy = drm_gem_dumb_destroy,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001019
1020 .ioctls = tegra_drm_ioctls,
1021 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1022 .fops = &tegra_drm_fops,
1023
1024 .name = DRIVER_NAME,
1025 .desc = DRIVER_DESC,
1026 .date = DRIVER_DATE,
1027 .major = DRIVER_MAJOR,
1028 .minor = DRIVER_MINOR,
1029 .patchlevel = DRIVER_PATCHLEVEL,
1030};
Thierry Reding776dc382013-10-14 14:43:22 +02001031
1032int tegra_drm_register_client(struct tegra_drm *tegra,
1033 struct tegra_drm_client *client)
1034{
1035 mutex_lock(&tegra->clients_lock);
1036 list_add_tail(&client->list, &tegra->clients);
1037 mutex_unlock(&tegra->clients_lock);
1038
1039 return 0;
1040}
1041
1042int tegra_drm_unregister_client(struct tegra_drm *tegra,
1043 struct tegra_drm_client *client)
1044{
1045 mutex_lock(&tegra->clients_lock);
1046 list_del_init(&client->list);
1047 mutex_unlock(&tegra->clients_lock);
1048
1049 return 0;
1050}
1051
Mikko Perttunenad926012016-12-14 13:16:11 +02001052void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1053 dma_addr_t *dma)
1054{
1055 struct iova *alloc;
1056 void *virt;
1057 gfp_t gfp;
1058 int err;
1059
1060 if (tegra->domain)
1061 size = iova_align(&tegra->carveout.domain, size);
1062 else
1063 size = PAGE_ALIGN(size);
1064
1065 gfp = GFP_KERNEL | __GFP_ZERO;
1066 if (!tegra->domain) {
1067 /*
1068 * Many units only support 32-bit addresses, even on 64-bit
1069 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1070 * virtual address space, force allocations to be in the
1071 * lower 32-bit range.
1072 */
1073 gfp |= GFP_DMA;
1074 }
1075
1076 virt = (void *)__get_free_pages(gfp, get_order(size));
1077 if (!virt)
1078 return ERR_PTR(-ENOMEM);
1079
1080 if (!tegra->domain) {
1081 /*
1082 * If IOMMU is disabled, devices address physical memory
1083 * directly.
1084 */
1085 *dma = virt_to_phys(virt);
1086 return virt;
1087 }
1088
1089 alloc = alloc_iova(&tegra->carveout.domain,
1090 size >> tegra->carveout.shift,
1091 tegra->carveout.limit, true);
1092 if (!alloc) {
1093 err = -EBUSY;
1094 goto free_pages;
1095 }
1096
1097 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1098 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1099 size, IOMMU_READ | IOMMU_WRITE);
1100 if (err < 0)
1101 goto free_iova;
1102
1103 return virt;
1104
1105free_iova:
1106 __free_iova(&tegra->carveout.domain, alloc);
1107free_pages:
1108 free_pages((unsigned long)virt, get_order(size));
1109
1110 return ERR_PTR(err);
1111}
1112
1113void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1114 dma_addr_t dma)
1115{
1116 if (tegra->domain)
1117 size = iova_align(&tegra->carveout.domain, size);
1118 else
1119 size = PAGE_ALIGN(size);
1120
1121 if (tegra->domain) {
1122 iommu_unmap(tegra->domain, dma, size);
1123 free_iova(&tegra->carveout.domain,
1124 iova_pfn(&tegra->carveout.domain, dma));
1125 }
1126
1127 free_pages((unsigned long)virt, get_order(size));
1128}
1129
Thierry Reding9910f5c2014-05-22 09:57:15 +02001130static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001131{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001132 struct drm_driver *driver = &tegra_drm_driver;
1133 struct drm_device *drm;
1134 int err;
1135
1136 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001137 if (IS_ERR(drm))
1138 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001139
Thierry Reding9910f5c2014-05-22 09:57:15 +02001140 dev_set_drvdata(&dev->dev, drm);
1141
1142 err = drm_dev_register(drm, 0);
1143 if (err < 0)
1144 goto unref;
1145
Thierry Reding9910f5c2014-05-22 09:57:15 +02001146 return 0;
1147
1148unref:
1149 drm_dev_unref(drm);
1150 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001151}
1152
Thierry Reding9910f5c2014-05-22 09:57:15 +02001153static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001154{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001155 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1156
1157 drm_dev_unregister(drm);
1158 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001159
1160 return 0;
1161}
1162
Thierry Reding359ae682014-12-18 17:15:25 +01001163#ifdef CONFIG_PM_SLEEP
1164static int host1x_drm_suspend(struct device *dev)
1165{
1166 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001167 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001168
1169 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001170 tegra_drm_fb_suspend(drm);
1171
1172 tegra->state = drm_atomic_helper_suspend(drm);
1173 if (IS_ERR(tegra->state)) {
1174 tegra_drm_fb_resume(drm);
1175 drm_kms_helper_poll_enable(drm);
1176 return PTR_ERR(tegra->state);
1177 }
Thierry Reding359ae682014-12-18 17:15:25 +01001178
1179 return 0;
1180}
1181
1182static int host1x_drm_resume(struct device *dev)
1183{
1184 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001185 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001186
Thierry Reding986c58d2015-08-11 13:11:49 +02001187 drm_atomic_helper_resume(drm, tegra->state);
1188 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001189 drm_kms_helper_poll_enable(drm);
1190
1191 return 0;
1192}
1193#endif
1194
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001195static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1196 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001197
Thierry Reding776dc382013-10-14 14:43:22 +02001198static const struct of_device_id host1x_drm_subdevs[] = {
1199 { .compatible = "nvidia,tegra20-dc", },
1200 { .compatible = "nvidia,tegra20-hdmi", },
1201 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001202 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001203 { .compatible = "nvidia,tegra30-dc", },
1204 { .compatible = "nvidia,tegra30-hdmi", },
1205 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001206 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001207 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001208 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001209 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001210 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001211 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001212 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001213 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001214 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001215 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001216 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001217 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001218 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001219 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001220 { .compatible = "nvidia,tegra210-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001221 { /* sentinel */ }
1222};
1223
1224static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001225 .driver = {
1226 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001227 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001228 },
Thierry Reding776dc382013-10-14 14:43:22 +02001229 .probe = host1x_drm_probe,
1230 .remove = host1x_drm_remove,
1231 .subdevs = host1x_drm_subdevs,
1232};
1233
Thierry Reding473112e2015-09-10 16:07:14 +02001234static struct platform_driver * const drivers[] = {
1235 &tegra_dc_driver,
1236 &tegra_hdmi_driver,
1237 &tegra_dsi_driver,
1238 &tegra_dpaux_driver,
1239 &tegra_sor_driver,
1240 &tegra_gr2d_driver,
1241 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001242 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001243};
1244
Thierry Reding776dc382013-10-14 14:43:22 +02001245static int __init host1x_drm_init(void)
1246{
1247 int err;
1248
1249 err = host1x_driver_register(&host1x_drm_driver);
1250 if (err < 0)
1251 return err;
1252
Thierry Reding473112e2015-09-10 16:07:14 +02001253 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001254 if (err < 0)
1255 goto unregister_host1x;
1256
Thierry Reding776dc382013-10-14 14:43:22 +02001257 return 0;
1258
Thierry Reding776dc382013-10-14 14:43:22 +02001259unregister_host1x:
1260 host1x_driver_unregister(&host1x_drm_driver);
1261 return err;
1262}
1263module_init(host1x_drm_init);
1264
1265static void __exit host1x_drm_exit(void)
1266{
Thierry Reding473112e2015-09-10 16:07:14 +02001267 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001268 host1x_driver_unregister(&host1x_drm_driver);
1269}
1270module_exit(host1x_drm_exit);
1271
1272MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1273MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1274MODULE_LICENSE("GPL v2");