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Hans de Goedeba4bdc92014-03-01 18:09:26 +01001Allwinner sun4i USB PHY
2-----------------------
3
4Required properties:
Maxime Ripardfecc2d72014-05-14 14:58:57 +02005- compatible : should be one of
6 * allwinner,sun4i-a10-usb-phy
7 * allwinner,sun5i-a13-usb-phy
8 * allwinner,sun6i-a31-usb-phy
9 * allwinner,sun7i-a20-usb-phy
Hans de Goede123dfdb2015-06-13 14:37:48 +020010 * allwinner,sun8i-a23-usb-phy
Hans de Goedefc1f45e2015-06-13 14:37:49 +020011 * allwinner,sun8i-a33-usb-phy
Chen-Yu Tsai1af556462017-08-03 16:14:05 +080012 * allwinner,sun8i-a83t-usb-phy
Reinder de Haan626a6302015-12-11 16:32:18 +010013 * allwinner,sun8i-h3-usb-phy
Icenowy Zheng16c40362017-01-03 23:25:31 +080014 * allwinner,sun8i-v3s-usb-phy
Icenowy Zheng732e35d2016-08-12 11:06:20 +080015 * allwinner,sun50i-a64-usb-phy
Hans de Goedeba4bdc92014-03-01 18:09:26 +010016- reg : a list of offset + length pairs
Maxime Ripardfecc2d72014-05-14 14:58:57 +020017- reg-names :
18 * "phy_ctrl"
Icenowy Zhenga0b19102017-03-25 22:50:08 +080019 * "pmu0" for H3, V3s and A64
Maxime Ripardfecc2d72014-05-14 14:58:57 +020020 * "pmu1"
Chen-Yu Tsai1af556462017-08-03 16:14:05 +080021 * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
Chen-Yu Tsai7a1de062017-08-03 16:14:04 +080022 * "pmu3" for sun8i-h3
Hans de Goedeba4bdc92014-03-01 18:09:26 +010023- #phy-cells : from the generic phy bindings, must be 1
Maxime Ripardfecc2d72014-05-14 14:58:57 +020024- clocks : phandle + clock specifier for the phy clocks
25- clock-names :
26 * "usb_phy" for sun4i, sun5i or sun7i
27 * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
Hans de Goede123dfdb2015-06-13 14:37:48 +020028 * "usb0_phy", "usb1_phy" for sun8i
Chen-Yu Tsai1af556462017-08-03 16:14:05 +080029 * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
Chen-Yu Tsai7a1de062017-08-03 16:14:04 +080030 * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
Hans de Goedeba4bdc92014-03-01 18:09:26 +010031- resets : a list of phandle + reset specifier pairs
Maxime Ripardfecc2d72014-05-14 14:58:57 +020032- reset-names :
33 * "usb0_reset"
34 * "usb1_reset"
Chen-Yu Tsai1af556462017-08-03 16:14:05 +080035 * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
Chen-Yu Tsai7a1de062017-08-03 16:14:04 +080036 * "usb3_reset" for sun8i-h3
Hans de Goedeba4bdc92014-03-01 18:09:26 +010037
Hans de Goeded2332302015-06-13 14:37:45 +020038Optional properties:
39- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
40- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
Hans de Goede8665c182015-06-13 14:37:51 +020041- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
Hans de Goeded2332302015-06-13 14:37:45 +020042- usb0_vbus-supply : regulator phandle for controller usb0 vbus
43- usb1_vbus-supply : regulator phandle for controller usb1 vbus
44- usb2_vbus-supply : regulator phandle for controller usb2 vbus
Chen-Yu Tsai7a1de062017-08-03 16:14:04 +080045- usb3_vbus-supply : regulator phandle for controller usb3 vbus
Hans de Goeded2332302015-06-13 14:37:45 +020046
Hans de Goedeba4bdc92014-03-01 18:09:26 +010047Example:
48 usbphy: phy@0x01c13400 {
49 #phy-cells = <1>;
50 compatible = "allwinner,sun4i-a10-usb-phy";
51 /* phy base regs, phy1 pmu reg, phy2 pmu reg */
52 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
53 reg-names = "phy_ctrl", "pmu1", "pmu2";
54 clocks = <&usb_clk 8>;
55 clock-names = "usb_phy";
Hans de Goeded2332302015-06-13 14:37:45 +020056 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
57 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
58 pinctrl-names = "default";
59 pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
60 usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
61 usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
62 usb0_vbus-supply = <&reg_usb0_vbus>;
63 usb1_vbus-supply = <&reg_usb1_vbus>;
64 usb2_vbus-supply = <&reg_usb2_vbus>;
Hans de Goedeba4bdc92014-03-01 18:09:26 +010065 };