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Stefan Agnerefb45b32014-11-02 21:36:46 +01001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "vf610-pinfunc.h"
11#include <dt-bindings/clock/vf610-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
Stefan Agner2b36bda2014-11-04 14:07:08 +010013#include <dt-bindings/gpio/gpio.h>
Stefan Agnerefb45b32014-11-02 21:36:46 +010014
15/ {
16 aliases {
17 can0 = &can0;
18 can1 = &can1;
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
32 };
33
34 fxosc: fxosc {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24000000>;
38 };
39
40 sxosc: sxosc {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 };
45
46 soc {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "simple-bus";
50 ranges;
51
52 aips0: aips-bus@40000000 {
53 compatible = "fsl,aips-bus", "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57
58 edma0: dma-controller@40018000 {
59 #dma-cells = <2>;
60 compatible = "fsl,vf610-edma";
61 reg = <0x40018000 0x2000>,
62 <0x40024000 0x1000>,
63 <0x40025000 0x1000>;
64 dma-channels = <32>;
65 clock-names = "dmamux0", "dmamux1";
66 clocks = <&clks VF610_CLK_DMAMUX0>,
67 <&clks VF610_CLK_DMAMUX1>;
68 status = "disabled";
69 };
70
71 can0: flexcan@40020000 {
72 compatible = "fsl,vf610-flexcan";
73 reg = <0x40020000 0x4000>;
74 clocks = <&clks VF610_CLK_FLEXCAN0>,
75 <&clks VF610_CLK_FLEXCAN0>;
76 clock-names = "ipg", "per";
77 status = "disabled";
78 };
79
80 uart0: serial@40027000 {
81 compatible = "fsl,vf610-lpuart";
82 reg = <0x40027000 0x1000>;
83 clocks = <&clks VF610_CLK_UART0>;
84 clock-names = "ipg";
85 dmas = <&edma0 0 2>,
86 <&edma0 0 3>;
87 dma-names = "rx","tx";
88 status = "disabled";
89 };
90
91 uart1: serial@40028000 {
92 compatible = "fsl,vf610-lpuart";
93 reg = <0x40028000 0x1000>;
94 clocks = <&clks VF610_CLK_UART1>;
95 clock-names = "ipg";
96 dmas = <&edma0 0 4>,
97 <&edma0 0 5>;
98 dma-names = "rx","tx";
99 status = "disabled";
100 };
101
102 uart2: serial@40029000 {
103 compatible = "fsl,vf610-lpuart";
104 reg = <0x40029000 0x1000>;
105 clocks = <&clks VF610_CLK_UART2>;
106 clock-names = "ipg";
107 dmas = <&edma0 0 6>,
108 <&edma0 0 7>;
109 dma-names = "rx","tx";
110 status = "disabled";
111 };
112
113 uart3: serial@4002a000 {
114 compatible = "fsl,vf610-lpuart";
115 reg = <0x4002a000 0x1000>;
116 clocks = <&clks VF610_CLK_UART3>;
117 clock-names = "ipg";
118 dmas = <&edma0 0 8>,
119 <&edma0 0 9>;
120 dma-names = "rx","tx";
121 status = "disabled";
122 };
123
124 dspi0: dspi0@4002c000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,vf610-dspi";
128 reg = <0x4002c000 0x1000>;
129 clocks = <&clks VF610_CLK_DSPI0>;
130 clock-names = "dspi";
131 spi-num-chipselects = <5>;
132 status = "disabled";
133 };
134
135 sai2: sai@40031000 {
136 compatible = "fsl,vf610-sai";
137 reg = <0x40031000 0x1000>;
138 clocks = <&clks VF610_CLK_SAI2>;
139 clock-names = "sai";
140 dma-names = "tx", "rx";
141 dmas = <&edma0 0 21>,
142 <&edma0 0 20>;
143 status = "disabled";
144 };
145
146 pit: pit@40037000 {
147 compatible = "fsl,vf610-pit";
148 reg = <0x40037000 0x1000>;
149 clocks = <&clks VF610_CLK_PIT>;
150 clock-names = "pit";
151 };
152
153 pwm0: pwm@40038000 {
154 compatible = "fsl,vf610-ftm-pwm";
155 #pwm-cells = <3>;
156 reg = <0x40038000 0x1000>;
157 clock-names = "ftm_sys", "ftm_ext",
158 "ftm_fix", "ftm_cnt_clk_en";
159 clocks = <&clks VF610_CLK_FTM0>,
160 <&clks VF610_CLK_FTM0_EXT_SEL>,
161 <&clks VF610_CLK_FTM0_FIX_SEL>,
162 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
163 status = "disabled";
164 };
165
166 pwm1: pwm@40039000 {
167 compatible = "fsl,vf610-ftm-pwm";
168 #pwm-cells = <3>;
169 reg = <0x40039000 0x1000>;
170 clock-names = "ftm_sys", "ftm_ext",
171 "ftm_fix", "ftm_cnt_clk_en";
172 clocks = <&clks VF610_CLK_FTM1>,
173 <&clks VF610_CLK_FTM1_EXT_SEL>,
174 <&clks VF610_CLK_FTM1_FIX_SEL>,
175 <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
176 status = "disabled";
177 };
178
179 adc0: adc@4003b000 {
180 compatible = "fsl,vf610-adc";
181 reg = <0x4003b000 0x1000>;
182 clocks = <&clks VF610_CLK_ADC0>;
183 clock-names = "adc";
184 status = "disabled";
185 };
186
Stefan Agnerc134e092014-11-28 00:35:36 +0100187 wdoga5: wdog@4003e000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100188 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
189 reg = <0x4003e000 0x1000>;
190 clocks = <&clks VF610_CLK_WDT>;
191 clock-names = "wdog";
192 status = "disabled";
193 };
194
195 qspi0: quadspi@40044000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,vf610-qspi";
199 reg = <0x40044000 0x1000>;
200 clocks = <&clks VF610_CLK_QSPI0_EN>,
201 <&clks VF610_CLK_QSPI0>;
202 clock-names = "qspi_en", "qspi";
203 status = "disabled";
204 };
205
206 iomuxc: iomuxc@40048000 {
207 compatible = "fsl,vf610-iomuxc";
208 reg = <0x40048000 0x1000>;
209 #gpio-range-cells = <3>;
210 };
211
212 gpio1: gpio@40049000 {
213 compatible = "fsl,vf610-gpio";
214 reg = <0x40049000 0x1000 0x400ff000 0x40>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 gpio-ranges = <&iomuxc 0 0 32>;
220 };
221
222 gpio2: gpio@4004a000 {
223 compatible = "fsl,vf610-gpio";
224 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 gpio-ranges = <&iomuxc 0 32 32>;
230 };
231
232 gpio3: gpio@4004b000 {
233 compatible = "fsl,vf610-gpio";
234 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-ranges = <&iomuxc 0 64 32>;
240 };
241
242 gpio4: gpio@4004c000 {
243 compatible = "fsl,vf610-gpio";
244 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 gpio-ranges = <&iomuxc 0 96 32>;
250 };
251
252 gpio5: gpio@4004d000 {
253 compatible = "fsl,vf610-gpio";
254 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 gpio-ranges = <&iomuxc 0 128 7>;
260 };
261
262 anatop: anatop@40050000 {
263 compatible = "fsl,vf610-anatop", "syscon";
264 reg = <0x40050000 0x400>;
265 };
266
267 usbphy0: usbphy@40050800 {
268 compatible = "fsl,vf610-usbphy";
269 reg = <0x40050800 0x400>;
270 clocks = <&clks VF610_CLK_USBPHY0>;
271 fsl,anatop = <&anatop>;
272 status = "disabled";
273 };
274
275 usbphy1: usbphy@40050c00 {
276 compatible = "fsl,vf610-usbphy";
277 reg = <0x40050c00 0x400>;
278 clocks = <&clks VF610_CLK_USBPHY1>;
279 fsl,anatop = <&anatop>;
280 status = "disabled";
281 };
282
283 i2c0: i2c@40066000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,vf610-i2c";
287 reg = <0x40066000 0x1000>;
288 clocks = <&clks VF610_CLK_I2C0>;
289 clock-names = "ipg";
290 dmas = <&edma0 0 50>,
291 <&edma0 0 51>;
292 dma-names = "rx","tx";
293 status = "disabled";
294 };
295
296 clks: ccm@4006b000 {
297 compatible = "fsl,vf610-ccm";
298 reg = <0x4006b000 0x1000>;
299 clocks = <&sxosc>, <&fxosc>;
300 clock-names = "sxosc", "fxosc";
301 #clock-cells = <1>;
302 };
303
304 usbdev0: usb@40034000 {
305 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
306 reg = <0x40034000 0x800>;
307 clocks = <&clks VF610_CLK_USBC0>;
308 fsl,usbphy = <&usbphy0>;
309 fsl,usbmisc = <&usbmisc0 0>;
310 dr_mode = "peripheral";
311 status = "disabled";
312 };
313
314 usbmisc0: usb@40034800 {
315 #index-cells = <1>;
316 compatible = "fsl,vf610-usbmisc";
317 reg = <0x40034800 0x200>;
318 clocks = <&clks VF610_CLK_USBC0>;
319 status = "disabled";
320 };
321 };
322
323 aips1: aips-bus@40080000 {
324 compatible = "fsl,aips-bus", "simple-bus";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges;
328
329 edma1: dma-controller@40098000 {
330 #dma-cells = <2>;
331 compatible = "fsl,vf610-edma";
332 reg = <0x40098000 0x2000>,
333 <0x400a1000 0x1000>,
334 <0x400a2000 0x1000>;
335 dma-channels = <32>;
336 clock-names = "dmamux0", "dmamux1";
337 clocks = <&clks VF610_CLK_DMAMUX2>,
338 <&clks VF610_CLK_DMAMUX3>;
339 status = "disabled";
340 };
341
342 uart4: serial@400a9000 {
343 compatible = "fsl,vf610-lpuart";
344 reg = <0x400a9000 0x1000>;
345 clocks = <&clks VF610_CLK_UART4>;
346 clock-names = "ipg";
347 status = "disabled";
348 };
349
350 uart5: serial@400aa000 {
351 compatible = "fsl,vf610-lpuart";
352 reg = <0x400aa000 0x1000>;
353 clocks = <&clks VF610_CLK_UART5>;
354 clock-names = "ipg";
355 status = "disabled";
356 };
357
358 adc1: adc@400bb000 {
359 compatible = "fsl,vf610-adc";
360 reg = <0x400bb000 0x1000>;
361 clocks = <&clks VF610_CLK_ADC1>;
362 clock-names = "adc";
363 status = "disabled";
364 };
365
366 esdhc1: esdhc@400b2000 {
367 compatible = "fsl,imx53-esdhc";
368 reg = <0x400b2000 0x1000>;
369 clocks = <&clks VF610_CLK_IPG_BUS>,
370 <&clks VF610_CLK_PLATFORM_BUS>,
371 <&clks VF610_CLK_ESDHC1>;
372 clock-names = "ipg", "ahb", "per";
373 status = "disabled";
374 };
375
376 usbh1: usb@400b4000 {
377 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
378 reg = <0x400b4000 0x800>;
379 clocks = <&clks VF610_CLK_USBC1>;
380 fsl,usbphy = <&usbphy1>;
381 fsl,usbmisc = <&usbmisc1 0>;
382 dr_mode = "host";
383 status = "disabled";
384 };
385
386 usbmisc1: usb@400b4800 {
387 #index-cells = <1>;
388 compatible = "fsl,vf610-usbmisc";
389 reg = <0x400b4800 0x200>;
390 clocks = <&clks VF610_CLK_USBC1>;
391 status = "disabled";
392 };
393
394 ftm: ftm@400b8000 {
395 compatible = "fsl,ftm-timer";
396 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
397 clock-names = "ftm-evt", "ftm-src",
398 "ftm-evt-counter-en", "ftm-src-counter-en";
399 clocks = <&clks VF610_CLK_FTM2>,
400 <&clks VF610_CLK_FTM3>,
401 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
402 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
403 status = "disabled";
404 };
405
406 fec0: ethernet@400d0000 {
407 compatible = "fsl,mvf600-fec";
408 reg = <0x400d0000 0x1000>;
409 clocks = <&clks VF610_CLK_ENET0>,
410 <&clks VF610_CLK_ENET0>,
411 <&clks VF610_CLK_ENET>;
412 clock-names = "ipg", "ahb", "ptp";
413 status = "disabled";
414 };
415
416 fec1: ethernet@400d1000 {
417 compatible = "fsl,mvf600-fec";
418 reg = <0x400d1000 0x1000>;
419 clocks = <&clks VF610_CLK_ENET1>,
420 <&clks VF610_CLK_ENET1>,
421 <&clks VF610_CLK_ENET>;
422 clock-names = "ipg", "ahb", "ptp";
423 status = "disabled";
424 };
425
426 can1: flexcan@400d4000 {
427 compatible = "fsl,vf610-flexcan";
428 reg = <0x400d4000 0x4000>;
429 clocks = <&clks VF610_CLK_FLEXCAN1>,
430 <&clks VF610_CLK_FLEXCAN1>;
431 clock-names = "ipg", "per";
432 status = "disabled";
433 };
434
435 };
436 };
437};