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Thomas Mair82041c02012-05-18 14:47:40 -03001/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef RTL2832_PRIV_H
22#define RTL2832_PRIV_H
23
24#include "dvb_frontend.h"
25#include "rtl2832.h"
Antti Palosaari8823f022013-11-26 12:53:46 -030026#include <linux/i2c-mux.h>
Thomas Mair82041c02012-05-18 14:47:40 -030027
Thomas Mair82041c02012-05-18 14:47:40 -030028struct rtl2832_priv {
29 struct i2c_adapter *i2c;
Antti Palosaari8823f022013-11-26 12:53:46 -030030 struct i2c_adapter *i2c_adapter;
Antti Palosaari0ea872d2013-12-03 18:19:39 -030031 struct i2c_adapter *i2c_adapter_tuner;
Thomas Mair82041c02012-05-18 14:47:40 -030032 struct dvb_frontend fe;
33 struct rtl2832_config cfg;
34
35 bool i2c_gate_state;
36 bool sleeping;
37
38 u8 tuner;
39 u8 page; /* active register page */
40};
41
42struct rtl2832_reg_entry {
43 u8 page;
44 u8 start_address;
45 u8 msb;
46 u8 lsb;
47};
48
49struct rtl2832_reg_value {
50 int reg;
51 u32 value;
52};
53
54
55/* Demod register bit names */
56enum DVBT_REG_BIT_NAME {
57 DVBT_SOFT_RST,
58 DVBT_IIC_REPEAT,
59 DVBT_TR_WAIT_MIN_8K,
60 DVBT_RSD_BER_FAIL_VAL,
61 DVBT_EN_BK_TRK,
62 DVBT_REG_PI,
63 DVBT_REG_PFREQ_1_0,
64 DVBT_PD_DA8,
65 DVBT_LOCK_TH,
66 DVBT_BER_PASS_SCAL,
67 DVBT_CE_FFSM_BYPASS,
68 DVBT_ALPHAIIR_N,
69 DVBT_ALPHAIIR_DIF,
70 DVBT_EN_TRK_SPAN,
71 DVBT_LOCK_TH_LEN,
72 DVBT_CCI_THRE,
73 DVBT_CCI_MON_SCAL,
74 DVBT_CCI_M0,
75 DVBT_CCI_M1,
76 DVBT_CCI_M2,
77 DVBT_CCI_M3,
78 DVBT_SPEC_INIT_0,
79 DVBT_SPEC_INIT_1,
80 DVBT_SPEC_INIT_2,
81 DVBT_AD_EN_REG,
82 DVBT_AD_EN_REG1,
83 DVBT_EN_BBIN,
84 DVBT_MGD_THD0,
85 DVBT_MGD_THD1,
86 DVBT_MGD_THD2,
87 DVBT_MGD_THD3,
88 DVBT_MGD_THD4,
89 DVBT_MGD_THD5,
90 DVBT_MGD_THD6,
91 DVBT_MGD_THD7,
92 DVBT_EN_CACQ_NOTCH,
93 DVBT_AD_AV_REF,
94 DVBT_PIP_ON,
95 DVBT_SCALE1_B92,
96 DVBT_SCALE1_B93,
97 DVBT_SCALE1_BA7,
98 DVBT_SCALE1_BA9,
99 DVBT_SCALE1_BAA,
100 DVBT_SCALE1_BAB,
101 DVBT_SCALE1_BAC,
102 DVBT_SCALE1_BB0,
103 DVBT_SCALE1_BB1,
104 DVBT_KB_P1,
105 DVBT_KB_P2,
106 DVBT_KB_P3,
107 DVBT_OPT_ADC_IQ,
108 DVBT_AD_AVI,
109 DVBT_AD_AVQ,
110 DVBT_K1_CR_STEP12,
111 DVBT_TRK_KS_P2,
112 DVBT_TRK_KS_I2,
113 DVBT_TR_THD_SET2,
114 DVBT_TRK_KC_P2,
115 DVBT_TRK_KC_I2,
116 DVBT_CR_THD_SET2,
117 DVBT_PSET_IFFREQ,
118 DVBT_SPEC_INV,
119 DVBT_BW_INDEX,
120 DVBT_RSAMP_RATIO,
121 DVBT_CFREQ_OFF_RATIO,
122 DVBT_FSM_STAGE,
123 DVBT_RX_CONSTEL,
124 DVBT_RX_HIER,
125 DVBT_RX_C_RATE_LP,
126 DVBT_RX_C_RATE_HP,
127 DVBT_GI_IDX,
128 DVBT_FFT_MODE_IDX,
129 DVBT_RSD_BER_EST,
130 DVBT_CE_EST_EVM,
131 DVBT_RF_AGC_VAL,
132 DVBT_IF_AGC_VAL,
133 DVBT_DAGC_VAL,
134 DVBT_SFREQ_OFF,
135 DVBT_CFREQ_OFF,
136 DVBT_POLAR_RF_AGC,
137 DVBT_POLAR_IF_AGC,
138 DVBT_AAGC_HOLD,
139 DVBT_EN_RF_AGC,
140 DVBT_EN_IF_AGC,
141 DVBT_IF_AGC_MIN,
142 DVBT_IF_AGC_MAX,
143 DVBT_RF_AGC_MIN,
144 DVBT_RF_AGC_MAX,
145 DVBT_IF_AGC_MAN,
146 DVBT_IF_AGC_MAN_VAL,
147 DVBT_RF_AGC_MAN,
148 DVBT_RF_AGC_MAN_VAL,
149 DVBT_DAGC_TRG_VAL,
150 DVBT_AGC_TARG_VAL,
151 DVBT_LOOP_GAIN_3_0,
152 DVBT_LOOP_GAIN_4,
153 DVBT_VTOP,
154 DVBT_KRF,
155 DVBT_AGC_TARG_VAL_0,
156 DVBT_AGC_TARG_VAL_8_1,
157 DVBT_AAGC_LOOP_GAIN,
158 DVBT_LOOP_GAIN2_3_0,
159 DVBT_LOOP_GAIN2_4,
160 DVBT_LOOP_GAIN3,
161 DVBT_VTOP1,
162 DVBT_VTOP2,
163 DVBT_VTOP3,
164 DVBT_KRF1,
165 DVBT_KRF2,
166 DVBT_KRF3,
167 DVBT_KRF4,
168 DVBT_EN_GI_PGA,
169 DVBT_THD_LOCK_UP,
170 DVBT_THD_LOCK_DW,
171 DVBT_THD_UP1,
172 DVBT_THD_DW1,
173 DVBT_INTER_CNT_LEN,
174 DVBT_GI_PGA_STATE,
175 DVBT_EN_AGC_PGA,
176 DVBT_CKOUTPAR,
177 DVBT_CKOUT_PWR,
178 DVBT_SYNC_DUR,
179 DVBT_ERR_DUR,
180 DVBT_SYNC_LVL,
181 DVBT_ERR_LVL,
182 DVBT_VAL_LVL,
183 DVBT_SERIAL,
184 DVBT_SER_LSB,
185 DVBT_CDIV_PH0,
186 DVBT_CDIV_PH1,
187 DVBT_MPEG_IO_OPT_2_2,
188 DVBT_MPEG_IO_OPT_1_0,
189 DVBT_CKOUTPAR_PIP,
190 DVBT_CKOUT_PWR_PIP,
191 DVBT_SYNC_LVL_PIP,
192 DVBT_ERR_LVL_PIP,
193 DVBT_VAL_LVL_PIP,
194 DVBT_CKOUTPAR_PID,
195 DVBT_CKOUT_PWR_PID,
196 DVBT_SYNC_LVL_PID,
197 DVBT_ERR_LVL_PID,
198 DVBT_VAL_LVL_PID,
199 DVBT_SM_PASS,
200 DVBT_UPDATE_REG_2,
201 DVBT_BTHD_P3,
202 DVBT_BTHD_D3,
203 DVBT_FUNC4_REG0,
204 DVBT_FUNC4_REG1,
205 DVBT_FUNC4_REG2,
206 DVBT_FUNC4_REG3,
207 DVBT_FUNC4_REG4,
208 DVBT_FUNC4_REG5,
209 DVBT_FUNC4_REG6,
210 DVBT_FUNC4_REG7,
211 DVBT_FUNC4_REG8,
212 DVBT_FUNC4_REG9,
213 DVBT_FUNC4_REG10,
214 DVBT_FUNC5_REG0,
215 DVBT_FUNC5_REG1,
216 DVBT_FUNC5_REG2,
217 DVBT_FUNC5_REG3,
218 DVBT_FUNC5_REG4,
219 DVBT_FUNC5_REG5,
220 DVBT_FUNC5_REG6,
221 DVBT_FUNC5_REG7,
222 DVBT_FUNC5_REG8,
223 DVBT_FUNC5_REG9,
224 DVBT_FUNC5_REG10,
225 DVBT_FUNC5_REG11,
226 DVBT_FUNC5_REG12,
227 DVBT_FUNC5_REG13,
228 DVBT_FUNC5_REG14,
229 DVBT_FUNC5_REG15,
230 DVBT_FUNC5_REG16,
231 DVBT_FUNC5_REG17,
232 DVBT_FUNC5_REG18,
233 DVBT_AD7_SETTING,
234 DVBT_RSSI_R,
235 DVBT_ACI_DET_IND,
236 DVBT_REG_MON,
237 DVBT_REG_MONSEL,
238 DVBT_REG_GPE,
239 DVBT_REG_GPO,
240 DVBT_REG_4MSEL,
241 DVBT_TEST_REG_1,
242 DVBT_TEST_REG_2,
243 DVBT_TEST_REG_3,
244 DVBT_TEST_REG_4,
245 DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
246};
247
Antti Palosaari5db41872012-09-11 22:27:08 -0300248static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
249 {DVBT_DAGC_TRG_VAL, 0x39},
250 {DVBT_AGC_TARG_VAL_0, 0x0},
251 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
252 {DVBT_AAGC_LOOP_GAIN, 0x16},
253 {DVBT_LOOP_GAIN2_3_0, 0x6},
254 {DVBT_LOOP_GAIN2_4, 0x1},
255 {DVBT_LOOP_GAIN3, 0x16},
256 {DVBT_VTOP1, 0x35},
257 {DVBT_VTOP2, 0x21},
258 {DVBT_VTOP3, 0x21},
259 {DVBT_KRF1, 0x0},
260 {DVBT_KRF2, 0x40},
261 {DVBT_KRF3, 0x10},
262 {DVBT_KRF4, 0x10},
263 {DVBT_IF_AGC_MIN, 0x80},
264 {DVBT_IF_AGC_MAX, 0x7f},
265 {DVBT_RF_AGC_MIN, 0x9c},
266 {DVBT_RF_AGC_MAX, 0x7f},
267 {DVBT_POLAR_RF_AGC, 0x0},
268 {DVBT_POLAR_IF_AGC, 0x0},
269 {DVBT_AD7_SETTING, 0xe9f4},
270 {DVBT_OPT_ADC_IQ, 0x1},
271 {DVBT_AD_AVI, 0x0},
272 {DVBT_AD_AVQ, 0x0},
Antti Palosaari3ca24182013-10-13 00:06:44 -0300273 {DVBT_SPEC_INV, 0x0},
Antti Palosaari5db41872012-09-11 22:27:08 -0300274};
275
Antti Palosaari832cc7c2012-09-11 22:27:04 -0300276static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
277 {DVBT_DAGC_TRG_VAL, 0x5a},
278 {DVBT_AGC_TARG_VAL_0, 0x0},
279 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
280 {DVBT_AAGC_LOOP_GAIN, 0x16},
281 {DVBT_LOOP_GAIN2_3_0, 0x6},
282 {DVBT_LOOP_GAIN2_4, 0x1},
283 {DVBT_LOOP_GAIN3, 0x16},
284 {DVBT_VTOP1, 0x35},
285 {DVBT_VTOP2, 0x21},
286 {DVBT_VTOP3, 0x21},
287 {DVBT_KRF1, 0x0},
288 {DVBT_KRF2, 0x40},
289 {DVBT_KRF3, 0x10},
290 {DVBT_KRF4, 0x10},
291 {DVBT_IF_AGC_MIN, 0x80},
292 {DVBT_IF_AGC_MAX, 0x7f},
293 {DVBT_RF_AGC_MIN, 0x80},
294 {DVBT_RF_AGC_MAX, 0x7f},
295 {DVBT_POLAR_RF_AGC, 0x0},
296 {DVBT_POLAR_IF_AGC, 0x0},
297 {DVBT_AD7_SETTING, 0xe9bf},
298 {DVBT_EN_GI_PGA, 0x0},
299 {DVBT_THD_LOCK_UP, 0x0},
300 {DVBT_THD_LOCK_DW, 0x0},
301 {DVBT_THD_UP1, 0x11},
302 {DVBT_THD_DW1, 0xef},
303 {DVBT_INTER_CNT_LEN, 0xc},
304 {DVBT_GI_PGA_STATE, 0x0},
305 {DVBT_EN_AGC_PGA, 0x1},
306 {DVBT_IF_AGC_MAN, 0x0},
Antti Palosaari3ca24182013-10-13 00:06:44 -0300307 {DVBT_SPEC_INV, 0x0},
Antti Palosaari832cc7c2012-09-11 22:27:04 -0300308};
309
Antti Palosaari7e688de2012-09-17 17:53:04 -0300310static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
311 {DVBT_DAGC_TRG_VAL, 0x5a},
312 {DVBT_AGC_TARG_VAL_0, 0x0},
313 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
314 {DVBT_AAGC_LOOP_GAIN, 0x18},
315 {DVBT_LOOP_GAIN2_3_0, 0x8},
316 {DVBT_LOOP_GAIN2_4, 0x1},
317 {DVBT_LOOP_GAIN3, 0x18},
318 {DVBT_VTOP1, 0x35},
319 {DVBT_VTOP2, 0x21},
320 {DVBT_VTOP3, 0x21},
321 {DVBT_KRF1, 0x0},
322 {DVBT_KRF2, 0x40},
323 {DVBT_KRF3, 0x10},
324 {DVBT_KRF4, 0x10},
325 {DVBT_IF_AGC_MIN, 0x80},
326 {DVBT_IF_AGC_MAX, 0x7f},
327 {DVBT_RF_AGC_MIN, 0x80},
328 {DVBT_RF_AGC_MAX, 0x7f},
329 {DVBT_POLAR_RF_AGC, 0x0},
330 {DVBT_POLAR_IF_AGC, 0x0},
331 {DVBT_AD7_SETTING, 0xe9d4},
332 {DVBT_EN_GI_PGA, 0x0},
333 {DVBT_THD_LOCK_UP, 0x0},
334 {DVBT_THD_LOCK_DW, 0x0},
335 {DVBT_THD_UP1, 0x14},
336 {DVBT_THD_DW1, 0xec},
337 {DVBT_INTER_CNT_LEN, 0xc},
338 {DVBT_GI_PGA_STATE, 0x0},
339 {DVBT_EN_AGC_PGA, 0x1},
340 {DVBT_REG_GPE, 0x1},
341 {DVBT_REG_GPO, 0x1},
342 {DVBT_REG_MONSEL, 0x1},
343 {DVBT_REG_MON, 0x1},
344 {DVBT_REG_4MSEL, 0x0},
Antti Palosaari3ca24182013-10-13 00:06:44 -0300345 {DVBT_SPEC_INV, 0x0},
Mauro Carvalho Chehabfa4bfd22013-04-09 18:19:50 -0300346};
347
348static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
Antti Palosaari3ca24182013-10-13 00:06:44 -0300349 {DVBT_DAGC_TRG_VAL, 0x39},
350 {DVBT_AGC_TARG_VAL_0, 0x0},
351 {DVBT_AGC_TARG_VAL_8_1, 0x40},
352 {DVBT_AAGC_LOOP_GAIN, 0x16},
353 {DVBT_LOOP_GAIN2_3_0, 0x8},
354 {DVBT_LOOP_GAIN2_4, 0x1},
355 {DVBT_LOOP_GAIN3, 0x18},
356 {DVBT_VTOP1, 0x35},
357 {DVBT_VTOP2, 0x21},
358 {DVBT_VTOP3, 0x21},
359 {DVBT_KRF1, 0x0},
360 {DVBT_KRF2, 0x40},
361 {DVBT_KRF3, 0x10},
362 {DVBT_KRF4, 0x10},
363 {DVBT_IF_AGC_MIN, 0x80},
364 {DVBT_IF_AGC_MAX, 0x7f},
365 {DVBT_RF_AGC_MIN, 0x80},
366 {DVBT_RF_AGC_MAX, 0x7f},
367 {DVBT_POLAR_RF_AGC, 0x0},
368 {DVBT_POLAR_IF_AGC, 0x0},
369 {DVBT_AD7_SETTING, 0xe9f4},
370 {DVBT_SPEC_INV, 0x1},
Antti Palosaari7e688de2012-09-17 17:53:04 -0300371};
372
Thomas Mair82041c02012-05-18 14:47:40 -0300373#endif /* RTL2832_PRIV_H */