| Alex Deucher | 0fcdb61 | 2010-03-24 13:20:41 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2010 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Alex Deucher |
| 23 | */ |
| 24 | #ifndef EVERGREEND_H |
| 25 | #define EVERGREEND_H |
| 26 | |
| 27 | /* Registers */ |
| 28 | |
| 29 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
| 30 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
| 31 | #define BACKEND_DISABLE(x) ((x) << 16) |
| 32 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
| 33 | |
| 34 | #define CGTS_SYS_TCC_DISABLE 0x3F90 |
| 35 | #define CGTS_TCC_DISABLE 0x9148 |
| 36 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 |
| 37 | #define CGTS_USER_TCC_DISABLE 0x914C |
| 38 | |
| 39 | #define CONFIG_MEMSIZE 0x5428 |
| 40 | |
| 41 | #define CP_ME_CNTL 0x86D8 |
| 42 | #define CP_ME_HALT (1<<28) |
| 43 | #define CP_PFP_HALT (1<<26) |
| 44 | #define CP_ME_RAM_DATA 0xC160 |
| 45 | #define CP_ME_RAM_RADDR 0xC158 |
| 46 | #define CP_ME_RAM_WADDR 0xC15C |
| 47 | #define CP_MEQ_THRESHOLDS 0x8764 |
| 48 | #define STQ_SPLIT(x) ((x) << 0) |
| 49 | #define CP_PERFMON_CNTL 0x87FC |
| 50 | #define CP_PFP_UCODE_ADDR 0xC150 |
| 51 | #define CP_PFP_UCODE_DATA 0xC154 |
| 52 | #define CP_QUEUE_THRESHOLDS 0x8760 |
| 53 | #define ROQ_IB1_START(x) ((x) << 0) |
| 54 | #define ROQ_IB2_START(x) ((x) << 8) |
| 55 | #define CP_RB_CNTL 0xC104 |
| 56 | #define RB_BUFSZ(x) ((x)<<0) |
| 57 | #define RB_BLKSZ(x) ((x)<<8) |
| 58 | #define RB_NO_UPDATE (1<<27) |
| 59 | #define RB_RPTR_WR_ENA (1<<31) |
| 60 | #define BUF_SWAP_32BIT (2 << 16) |
| 61 | #define CP_RB_RPTR 0x8700 |
| 62 | #define CP_RB_RPTR_ADDR 0xC10C |
| 63 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
| 64 | #define CP_RB_RPTR_WR 0xC108 |
| 65 | #define CP_RB_WPTR 0xC114 |
| 66 | #define CP_RB_WPTR_ADDR 0xC118 |
| 67 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
| 68 | #define CP_RB_WPTR_DELAY 0x8704 |
| 69 | #define CP_SEM_WAIT_TIMER 0x85BC |
| 70 | |
| 71 | |
| 72 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
| 73 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
| 74 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
| 75 | #define INACTIVE_SIMDS(x) ((x) << 16) |
| 76 | #define INACTIVE_SIMDS_MASK 0x00FF0000 |
| 77 | |
| 78 | #define GRBM_CNTL 0x8000 |
| 79 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 80 | #define GRBM_SOFT_RESET 0x8020 |
| 81 | #define SOFT_RESET_CP (1<<0) |
| 82 | #define GRBM_STATUS 0x8010 |
| 83 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
| 84 | #define GUI_ACTIVE (1<<31) |
| 85 | |
| 86 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 87 | #define HDP_NONSURFACE_BASE 0x2C04 |
| 88 | #define HDP_NONSURFACE_INFO 0x2C08 |
| 89 | #define HDP_NONSURFACE_SIZE 0x2C0C |
| 90 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
| 91 | #define HDP_TILING_CONFIG 0x2F3C |
| 92 | |
| 93 | #define MC_SHARED_CHMAP 0x2004 |
| 94 | #define NOOFCHAN_SHIFT 12 |
| 95 | #define NOOFCHAN_MASK 0x00003000 |
| 96 | |
| 97 | #define MC_ARB_RAMCFG 0x2760 |
| 98 | #define NOOFBANK_SHIFT 0 |
| 99 | #define NOOFBANK_MASK 0x00000003 |
| 100 | #define NOOFRANK_SHIFT 2 |
| 101 | #define NOOFRANK_MASK 0x00000004 |
| 102 | #define NOOFROWS_SHIFT 3 |
| 103 | #define NOOFROWS_MASK 0x00000038 |
| 104 | #define NOOFCOLS_SHIFT 6 |
| 105 | #define NOOFCOLS_MASK 0x000000C0 |
| 106 | #define CHANSIZE_SHIFT 8 |
| 107 | #define CHANSIZE_MASK 0x00000100 |
| 108 | #define BURSTLENGTH_SHIFT 9 |
| 109 | #define BURSTLENGTH_MASK 0x00000200 |
| 110 | #define CHANSIZE_OVERRIDE (1 << 11) |
| 111 | #define MC_VM_AGP_TOP 0x2028 |
| 112 | #define MC_VM_AGP_BOT 0x202C |
| 113 | #define MC_VM_AGP_BASE 0x2030 |
| 114 | #define MC_VM_FB_LOCATION 0x2024 |
| 115 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 |
| 116 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 |
| 117 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C |
| 118 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 |
| 119 | #define ENABLE_L1_TLB (1 << 0) |
| 120 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
| 121 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) |
| 122 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) |
| 123 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) |
| 124 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) |
| 125 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) |
| 126 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) |
| 127 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) |
| 128 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 |
| 129 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 |
| 130 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C |
| 131 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
| 132 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
| 133 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
| 134 | |
| 135 | #define PA_CL_ENHANCE 0x8A14 |
| 136 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
| 137 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
| 138 | #define PA_SC_AA_CONFIG 0x28C04 |
| 139 | #define PA_SC_CLIPRECT_RULE 0x2820C |
| 140 | #define PA_SC_EDGERULE 0x28230 |
| 141 | #define PA_SC_FIFO_SIZE 0x8BCC |
| 142 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) |
| 143 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) |
| 144 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
| 145 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) |
| 146 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) |
| 147 | #define PA_SC_LINE_STIPPLE 0x28A0C |
| 148 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
| 149 | |
| 150 | #define SCRATCH_REG0 0x8500 |
| 151 | #define SCRATCH_REG1 0x8504 |
| 152 | #define SCRATCH_REG2 0x8508 |
| 153 | #define SCRATCH_REG3 0x850C |
| 154 | #define SCRATCH_REG4 0x8510 |
| 155 | #define SCRATCH_REG5 0x8514 |
| 156 | #define SCRATCH_REG6 0x8518 |
| 157 | #define SCRATCH_REG7 0x851C |
| 158 | #define SCRATCH_UMSK 0x8540 |
| 159 | #define SCRATCH_ADDR 0x8544 |
| 160 | |
| 161 | #define SMX_DC_CTL0 0xA020 |
| 162 | #define USE_HASH_FUNCTION (1 << 0) |
| 163 | #define CACHE_DEPTH(x) ((x) << 1) |
| 164 | #define FLUSH_ALL_ON_EVENT (1 << 10) |
| 165 | #define STALL_ON_EVENT (1 << 11) |
| 166 | #define SMX_EVENT_CTL 0xA02C |
| 167 | #define ES_FLUSH_CTL(x) ((x) << 0) |
| 168 | #define GS_FLUSH_CTL(x) ((x) << 3) |
| 169 | #define ACK_FLUSH_CTL(x) ((x) << 6) |
| 170 | #define SYNC_FLUSH_CTL (1 << 8) |
| 171 | |
| 172 | #define SPI_CONFIG_CNTL 0x9100 |
| 173 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) |
| 174 | #define SPI_CONFIG_CNTL_1 0x913C |
| 175 | #define VTX_DONE_DELAY(x) ((x) << 0) |
| 176 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
| 177 | #define SPI_INPUT_Z 0x286D8 |
| 178 | #define SPI_PS_IN_CONTROL_0 0x286CC |
| 179 | #define NUM_INTERP(x) ((x)<<0) |
| 180 | #define POSITION_ENA (1<<8) |
| 181 | #define POSITION_CENTROID (1<<9) |
| 182 | #define POSITION_ADDR(x) ((x)<<10) |
| 183 | #define PARAM_GEN(x) ((x)<<15) |
| 184 | #define PARAM_GEN_ADDR(x) ((x)<<19) |
| 185 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) |
| 186 | #define PERSP_GRADIENT_ENA (1<<28) |
| 187 | #define LINEAR_GRADIENT_ENA (1<<29) |
| 188 | #define POSITION_SAMPLE (1<<30) |
| 189 | #define BARYC_AT_SAMPLE_ENA (1<<31) |
| 190 | |
| 191 | #define SQ_CONFIG 0x8C00 |
| 192 | #define VC_ENABLE (1 << 0) |
| 193 | #define EXPORT_SRC_C (1 << 1) |
| 194 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 |
| 195 | #define NUM_PS_GPRS(x) ((x) << 0) |
| 196 | #define NUM_VS_GPRS(x) ((x) << 16) |
| 197 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
| 198 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 |
| 199 | #define NUM_GS_GPRS(x) ((x) << 0) |
| 200 | #define NUM_ES_GPRS(x) ((x) << 16) |
| 201 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
| 202 | #define CACHE_FIFO_SIZE(x) ((x) << 0) |
| 203 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) |
| 204 | #define DONE_FIFO_HIWATER(x) ((x) << 16) |
| 205 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
| 206 | |
| 207 | #define SX_DEBUG_1 0x9058 |
| 208 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |
| 209 | #define SX_EXPORT_BUFFER_SIZES 0x900C |
| 210 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) |
| 211 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) |
| 212 | #define SMX_BUFFER_SIZE(x) ((x) << 16) |
| 213 | #define SX_MISC 0x28350 |
| 214 | |
| 215 | #define TA_CNTL_AUX 0x9508 |
| 216 | #define DISABLE_CUBE_WRAP (1 << 0) |
| 217 | #define DISABLE_CUBE_ANISO (1 << 1) |
| 218 | #define SYNC_GRADIENT (1 << 24) |
| 219 | #define SYNC_WALKER (1 << 25) |
| 220 | #define SYNC_ALIGNER (1 << 26) |
| 221 | |
| 222 | #define VGT_CACHE_INVALIDATION 0x88C4 |
| 223 | #define CACHE_INVALIDATION(x) ((x)<<0) |
| 224 | #define VC_ONLY 0 |
| 225 | #define TC_ONLY 1 |
| 226 | #define VC_AND_TC 2 |
| 227 | #define AUTO_INVLD_EN(x) ((x) << 6) |
| 228 | #define NO_AUTO 0 |
| 229 | #define ES_AUTO 1 |
| 230 | #define GS_AUTO 2 |
| 231 | #define ES_AND_GS_AUTO 3 |
| 232 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
| 233 | #define VGT_NUM_INSTANCES 0x8974 |
| 234 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C |
| 235 | #define DEALLOC_DIST_MASK 0x0000007F |
| 236 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
| 237 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
| 238 | |
| 239 | #define VM_CONTEXT0_CNTL 0x1410 |
| 240 | #define ENABLE_CONTEXT (1 << 0) |
| 241 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
| 242 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
| 243 | #define VM_CONTEXT1_CNTL 0x1414 |
| 244 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
| 245 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
| 246 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
| 247 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
| 248 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
| 249 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
| 250 | #define RESPONSE_TYPE_MASK 0x000000F0 |
| 251 | #define RESPONSE_TYPE_SHIFT 4 |
| 252 | #define VM_L2_CNTL 0x1400 |
| 253 | #define ENABLE_L2_CACHE (1 << 0) |
| 254 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
| 255 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
| 256 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) |
| 257 | #define VM_L2_CNTL2 0x1404 |
| 258 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
| 259 | #define INVALIDATE_L2_CACHE (1 << 1) |
| 260 | #define VM_L2_CNTL3 0x1408 |
| 261 | #define BANK_SELECT(x) ((x) << 0) |
| 262 | #define CACHE_UPDATE_MODE(x) ((x) << 6) |
| 263 | #define VM_L2_STATUS 0x140C |
| 264 | #define L2_BUSY (1 << 0) |
| 265 | |
| 266 | #define WAIT_UNTIL 0x8040 |
| 267 | |
| 268 | #define SRBM_STATUS 0x0E50 |
| 269 | |
| 270 | #endif |