Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 1 | /* |
| 2 | * ahci.h - Common AHCI SATA definitions and declarations |
| 3 | * |
Tejun Heo | 8c3d3d4 | 2013-05-14 11:09:50 -0700 | [diff] [blame] | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * Copyright 2004-2005 Red Hat, Inc. |
| 9 | * |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
| 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
| 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
| 32 | * |
| 33 | */ |
| 34 | |
| 35 | #ifndef _AHCI_H |
| 36 | #define _AHCI_H |
| 37 | |
Viresh Kumar | f1e70c2 | 2012-08-27 10:37:19 +0530 | [diff] [blame] | 38 | #include <linux/clk.h> |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 39 | #include <linux/libata.h> |
Roger Quadros | 21b5fae | 2014-02-22 16:53:40 +0100 | [diff] [blame] | 40 | #include <linux/phy/phy.h> |
Hans de Goede | 4b3e603 | 2014-02-22 16:53:32 +0100 | [diff] [blame] | 41 | #include <linux/regulator/consumer.h> |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 42 | |
| 43 | /* Enclosure Management Control */ |
| 44 | #define EM_CTRL_MSG_TYPE 0x000f0000 |
| 45 | |
| 46 | /* Enclosure Management LED Message Type */ |
| 47 | #define EM_MSG_LED_HBA_PORT 0x0000000f |
| 48 | #define EM_MSG_LED_PMP_SLOT 0x0000ff00 |
| 49 | #define EM_MSG_LED_VALUE 0xffff0000 |
| 50 | #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 |
| 51 | #define EM_MSG_LED_VALUE_OFF 0xfff80000 |
| 52 | #define EM_MSG_LED_VALUE_ON 0x00010000 |
| 53 | |
| 54 | enum { |
| 55 | AHCI_MAX_PORTS = 32, |
Kumar Gala | ee309f3 | 2014-09-22 15:09:45 -0500 | [diff] [blame] | 56 | AHCI_MAX_CLKS = 5, |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 57 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 58 | AHCI_DMA_BOUNDARY = 0xffffffff, |
| 59 | AHCI_MAX_CMDS = 32, |
| 60 | AHCI_CMD_SZ = 32, |
| 61 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
| 62 | AHCI_RX_FIS_SZ = 256, |
| 63 | AHCI_CMD_TBL_CDB = 0x40, |
| 64 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 65 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 66 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 67 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
| 68 | AHCI_RX_FIS_SZ, |
| 69 | AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + |
| 70 | AHCI_CMD_TBL_AR_SZ + |
| 71 | (AHCI_RX_FIS_SZ * 16), |
| 72 | AHCI_IRQ_ON_SG = (1 << 31), |
| 73 | AHCI_CMD_ATAPI = (1 << 5), |
| 74 | AHCI_CMD_WRITE = (1 << 6), |
| 75 | AHCI_CMD_PREFETCH = (1 << 7), |
| 76 | AHCI_CMD_RESET = (1 << 8), |
| 77 | AHCI_CMD_CLR_BUSY = (1 << 10), |
| 78 | |
Tejun Heo | 6ad6019 | 2010-10-15 11:00:08 +0200 | [diff] [blame] | 79 | RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 80 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
| 81 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
| 82 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
| 83 | |
| 84 | /* global controller registers */ |
| 85 | HOST_CAP = 0x00, /* host capabilities */ |
| 86 | HOST_CTL = 0x04, /* global host control */ |
| 87 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 88 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 89 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 90 | HOST_EM_LOC = 0x1c, /* Enclosure Management location */ |
| 91 | HOST_EM_CTL = 0x20, /* Enclosure Management Control */ |
| 92 | HOST_CAP2 = 0x24, /* host capabilities, extended */ |
| 93 | |
| 94 | /* HOST_CTL bits */ |
| 95 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 96 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
Alexander Gordeev | ab0f9e7 | 2014-04-17 14:13:49 +0200 | [diff] [blame] | 97 | HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 98 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 99 | |
| 100 | /* HOST_CAP bits */ |
| 101 | HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ |
| 102 | HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ |
| 103 | HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ |
| 104 | HOST_CAP_PART = (1 << 13), /* Partial state capable */ |
| 105 | HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ |
| 106 | HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ |
| 107 | HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ |
| 108 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
| 109 | HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ |
| 110 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
| 111 | HOST_CAP_LED = (1 << 25), /* Supports activity LED */ |
| 112 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
| 113 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
| 114 | HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ |
| 115 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
| 116 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
| 117 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
| 118 | |
| 119 | /* HOST_CAP2 bits */ |
| 120 | HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ |
| 121 | HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ |
| 122 | HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ |
Shane Huang | 65fe1f0 | 2012-09-07 22:40:01 +0800 | [diff] [blame] | 123 | HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ |
| 124 | HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ |
| 125 | HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 126 | |
| 127 | /* registers for each SATA port */ |
| 128 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 129 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 130 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 131 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 132 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 133 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 134 | PORT_CMD = 0x18, /* port command */ |
| 135 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 136 | PORT_SIG = 0x24, /* device TF signature */ |
| 137 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
| 138 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 139 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 140 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 141 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
| 142 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
| 143 | PORT_FBS = 0x40, /* FIS-based Switching */ |
Shane Huang | 65fe1f0 | 2012-09-07 22:40:01 +0800 | [diff] [blame] | 144 | PORT_DEVSLP = 0x44, /* device sleep */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 145 | |
| 146 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 147 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 148 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 149 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 150 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 151 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 152 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 153 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 154 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 155 | |
| 156 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 157 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 158 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 159 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 160 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 161 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 162 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 163 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 164 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 165 | |
| 166 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 167 | PORT_IRQ_IF_ERR | |
| 168 | PORT_IRQ_CONNECT | |
| 169 | PORT_IRQ_PHYRDY | |
| 170 | PORT_IRQ_UNK_FIS | |
| 171 | PORT_IRQ_BAD_PMP, |
| 172 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 173 | PORT_IRQ_TF_ERR | |
| 174 | PORT_IRQ_HBUS_DATA_ERR, |
| 175 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 176 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 177 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
| 178 | |
| 179 | /* PORT_CMD bits */ |
| 180 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
| 181 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ |
| 182 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
| 183 | PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ |
| 184 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
| 185 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 186 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 187 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
| 188 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
| 189 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 190 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 191 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 192 | |
| 193 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
| 194 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 195 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 196 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
| 197 | |
Shane Huang | 65fe1f0 | 2012-09-07 22:40:01 +0800 | [diff] [blame] | 198 | /* PORT_FBS bits */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 199 | PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ |
| 200 | PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ |
| 201 | PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ |
| 202 | PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ |
| 203 | PORT_FBS_SDE = (1 << 2), /* FBS single device error */ |
| 204 | PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ |
| 205 | PORT_FBS_EN = (1 << 0), /* Enable FBS */ |
| 206 | |
Shane Huang | 65fe1f0 | 2012-09-07 22:40:01 +0800 | [diff] [blame] | 207 | /* PORT_DEVSLP bits */ |
| 208 | PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ |
| 209 | PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */ |
| 210 | PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ |
| 211 | PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ |
| 212 | PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ |
| 213 | PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ |
| 214 | PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ |
| 215 | |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 216 | /* hpriv->flags bits */ |
Brian Norris | 55d5ec31 | 2012-02-21 10:38:43 -0800 | [diff] [blame] | 217 | |
| 218 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
| 219 | |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 220 | AHCI_HFLAG_NO_NCQ = (1 << 0), |
| 221 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ |
| 222 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ |
| 223 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ |
| 224 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ |
| 225 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ |
| 226 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 227 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
| 228 | AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ |
| 229 | AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ |
| 230 | AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as |
| 231 | link offline */ |
| 232 | AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ |
Tejun Heo | 83f2b96 | 2010-03-30 10:28:32 +0900 | [diff] [blame] | 233 | AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ |
Tejun Heo | 5f17310 | 2010-07-24 16:53:48 +0200 | [diff] [blame] | 234 | AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ |
Brian Norris | 66583c9 | 2012-02-21 10:38:42 -0800 | [diff] [blame] | 235 | AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on |
| 236 | port start (wait until |
| 237 | error-handling stage) */ |
Alexander Gordeev | 5ca72c4 | 2012-11-19 16:02:48 +0100 | [diff] [blame] | 238 | AHCI_HFLAG_MULTI_MSI = (1 << 16), /* multiple PCI MSIs */ |
Jacob Pan | 0cf4a7d | 2014-04-15 22:27:11 -0700 | [diff] [blame] | 239 | AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ |
Linus Torvalds | 6ea4fa70 | 2014-06-09 14:58:36 -0700 | [diff] [blame] | 240 | AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ |
Suman Tripathi | 5903b16 | 2015-05-06 00:51:11 +0530 | [diff] [blame] | 241 | AHCI_HFLAG_EDGE_IRQ = (1 << 19), /* HOST_IRQ_STAT behaves as |
| 242 | Edge Triggered */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 243 | |
| 244 | /* ap->flags bits */ |
| 245 | |
Sergei Shtylyov | 9cbe056 | 2011-02-04 22:05:48 +0300 | [diff] [blame] | 246 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
Sergei Shtylyov | 1a0f6b7 | 2011-02-04 22:08:22 +0300 | [diff] [blame] | 247 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 248 | |
| 249 | ICH_MAP = 0x90, /* ICH MAP register */ |
| 250 | |
| 251 | /* em constants */ |
| 252 | EM_MAX_SLOTS = 8, |
| 253 | EM_MAX_RETRY = 5, |
| 254 | |
| 255 | /* em_ctl bits */ |
Harry Zhang | c062316 | 2010-04-23 17:28:38 +0800 | [diff] [blame] | 256 | EM_CTL_RST = (1 << 9), /* Reset */ |
| 257 | EM_CTL_TM = (1 << 8), /* Transmit Message */ |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 258 | EM_CTL_MR = (1 << 0), /* Message Received */ |
Harry Zhang | c062316 | 2010-04-23 17:28:38 +0800 | [diff] [blame] | 259 | EM_CTL_ALHD = (1 << 26), /* Activity LED */ |
| 260 | EM_CTL_XMT = (1 << 25), /* Transmit Only */ |
| 261 | EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ |
Hannes Reinecke | 6e5fe5b1 | 2011-03-04 09:54:52 +0100 | [diff] [blame] | 262 | EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ |
| 263 | EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ |
| 264 | EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ |
| 265 | EM_CTL_LED = (1 << 16), /* LED messages supported */ |
Harry Zhang | 008dbd6 | 2010-04-23 17:27:19 +0800 | [diff] [blame] | 266 | |
| 267 | /* em message type */ |
| 268 | EM_MSG_TYPE_LED = (1 << 0), /* LED */ |
| 269 | EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ |
| 270 | EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ |
| 271 | EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 272 | }; |
| 273 | |
| 274 | struct ahci_cmd_hdr { |
| 275 | __le32 opts; |
| 276 | __le32 status; |
| 277 | __le32 tbl_addr; |
| 278 | __le32 tbl_addr_hi; |
| 279 | __le32 reserved[4]; |
| 280 | }; |
| 281 | |
| 282 | struct ahci_sg { |
| 283 | __le32 addr; |
| 284 | __le32 addr_hi; |
| 285 | __le32 reserved; |
| 286 | __le32 flags_size; |
| 287 | }; |
| 288 | |
| 289 | struct ahci_em_priv { |
| 290 | enum sw_activity blink_policy; |
| 291 | struct timer_list timer; |
| 292 | unsigned long saved_activity; |
| 293 | unsigned long activity; |
| 294 | unsigned long led_state; |
| 295 | }; |
| 296 | |
| 297 | struct ahci_port_priv { |
| 298 | struct ata_link *active_link; |
| 299 | struct ahci_cmd_hdr *cmd_slot; |
| 300 | dma_addr_t cmd_slot_dma; |
| 301 | void *cmd_tbl; |
| 302 | dma_addr_t cmd_tbl_dma; |
| 303 | void *rx_fis; |
| 304 | dma_addr_t rx_fis_dma; |
| 305 | /* for NCQ spurious interrupt analysis */ |
| 306 | unsigned int ncq_saw_d2h:1; |
| 307 | unsigned int ncq_saw_dmas:1; |
| 308 | unsigned int ncq_saw_sdb:1; |
Alexander Gordeev | 227dfb4 | 2014-09-29 18:26:01 +0200 | [diff] [blame] | 309 | atomic_t intr_status; /* interrupts to handle */ |
Alexander Gordeev | 5ca72c4 | 2012-11-19 16:02:48 +0100 | [diff] [blame] | 310 | spinlock_t lock; /* protects parent ata_port */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 311 | u32 intr_mask; /* interrupts to enable */ |
| 312 | bool fbs_supported; /* set iff FBS is supported */ |
| 313 | bool fbs_enabled; /* set iff FBS is enabled */ |
| 314 | int fbs_last_dev; /* save FBS.DEV of last FIS */ |
| 315 | /* enclosure management info per PM slot */ |
| 316 | struct ahci_em_priv em_priv[EM_MAX_SLOTS]; |
Alexander Gordeev | b29900e | 2013-05-22 08:53:48 +0900 | [diff] [blame] | 317 | char *irq_desc; /* desc in /proc/interrupts */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 318 | }; |
| 319 | |
| 320 | struct ahci_host_priv { |
Antoine Ténart | 725c7b5 | 2014-07-30 20:13:56 +0200 | [diff] [blame] | 321 | /* Input fields */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 322 | unsigned int flags; /* AHCI_HFLAG_* */ |
Antoine Ténart | 725c7b5 | 2014-07-30 20:13:56 +0200 | [diff] [blame] | 323 | u32 force_port_map; /* force port map */ |
| 324 | u32 mask_port_map; /* mask out particular bits */ |
| 325 | |
| 326 | void __iomem * mmio; /* bus-independent mem map */ |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 327 | u32 cap; /* cap to use */ |
| 328 | u32 cap2; /* cap2 to use */ |
| 329 | u32 port_map; /* port map to use */ |
| 330 | u32 saved_cap; /* saved initial cap */ |
| 331 | u32 saved_cap2; /* saved initial cap2 */ |
| 332 | u32 saved_port_map; /* saved initial port_map */ |
| 333 | u32 em_loc; /* enclosure management location */ |
Harry Zhang | c062316 | 2010-04-23 17:28:38 +0800 | [diff] [blame] | 334 | u32 em_buf_sz; /* EM buffer size in byte */ |
Harry Zhang | 008dbd6 | 2010-04-23 17:27:19 +0800 | [diff] [blame] | 335 | u32 em_msg_type; /* EM message type */ |
Roger Quadros | e708e46 | 2014-02-22 16:53:41 +0100 | [diff] [blame] | 336 | bool got_runtime_pm; /* Did we do pm_runtime_get? */ |
Hans de Goede | 156c588 | 2014-02-22 16:53:31 +0100 | [diff] [blame] | 337 | struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ |
Gregory CLEMENT | c7d7dde | 2015-01-15 15:09:37 +0100 | [diff] [blame] | 338 | struct regulator **target_pwrs; /* Optional */ |
Antoine Ténart | b1a9edbd | 2014-07-30 20:13:57 +0200 | [diff] [blame] | 339 | /* |
| 340 | * If platform uses PHYs. There is a 1:1 relation between the port number and |
| 341 | * the PHY position in this array. |
| 342 | */ |
| 343 | struct phy **phys; |
| 344 | unsigned nports; /* Number of ports */ |
Mark Langsdorf | d50b110 | 2013-06-06 07:52:41 -0500 | [diff] [blame] | 345 | void *plat_data; /* Other platform data */ |
Robert Richter | 21bfd1a | 2015-05-31 13:55:18 +0200 | [diff] [blame] | 346 | unsigned int irq; /* interrupt line */ |
Hans de Goede | 039ece3 | 2014-02-22 16:53:30 +0100 | [diff] [blame] | 347 | /* |
| 348 | * Optional ahci_start_engine override, if not set this gets set to the |
| 349 | * default ahci_start_engine during ahci_save_initial_config, this can |
| 350 | * be overridden anytime before the host is activated. |
| 351 | */ |
| 352 | void (*start_engine)(struct ata_port *ap); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 353 | }; |
| 354 | |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 355 | extern int ahci_ignore_sss; |
| 356 | |
Tejun Heo | fad16e7 | 2010-09-21 09:25:48 +0200 | [diff] [blame] | 357 | extern struct device_attribute *ahci_shost_attrs[]; |
| 358 | extern struct device_attribute *ahci_sdev_attrs[]; |
| 359 | |
Akinobu Mita | 018d5ef | 2015-01-29 08:30:29 +0900 | [diff] [blame] | 360 | /* |
| 361 | * This must be instantiated by the edge drivers. Read the comments |
| 362 | * for ATA_BASE_SHT |
| 363 | */ |
Tejun Heo | fad16e7 | 2010-09-21 09:25:48 +0200 | [diff] [blame] | 364 | #define AHCI_SHT(drv_name) \ |
| 365 | ATA_NCQ_SHT(drv_name), \ |
| 366 | .can_queue = AHCI_MAX_CMDS - 1, \ |
| 367 | .sg_tablesize = AHCI_MAX_SG, \ |
| 368 | .dma_boundary = AHCI_DMA_BOUNDARY, \ |
| 369 | .shost_attrs = ahci_shost_attrs, \ |
| 370 | .sdev_attrs = ahci_sdev_attrs |
| 371 | |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 372 | extern struct ata_port_operations ahci_ops; |
Richard Zhu | 8b789d8 | 2013-10-15 10:44:54 +0800 | [diff] [blame] | 373 | extern struct ata_port_operations ahci_platform_ops; |
Yuan-Hsin Chen | 345347c | 2011-06-21 17:17:38 +0800 | [diff] [blame] | 374 | extern struct ata_port_operations ahci_pmp_retry_srst_ops; |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 375 | |
Rob Herring | bbb4ab4 | 2012-08-17 09:51:50 -0500 | [diff] [blame] | 376 | unsigned int ahci_dev_classify(struct ata_port *ap); |
David Milburn | 02cdfcf | 2010-11-12 15:38:21 -0600 | [diff] [blame] | 377 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 378 | u32 opts); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 379 | void ahci_save_initial_config(struct device *dev, |
Antoine Ténart | 725c7b5 | 2014-07-30 20:13:56 +0200 | [diff] [blame] | 380 | struct ahci_host_priv *hpriv); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 381 | void ahci_init_controller(struct ata_host *host); |
| 382 | int ahci_reset_controller(struct ata_host *host); |
| 383 | |
| 384 | int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
| 385 | int pmp, unsigned long deadline, |
| 386 | int (*check_ready)(struct ata_link *link)); |
| 387 | |
Suman Tripathi | 39e0ee9 | 2014-07-07 22:33:04 +0530 | [diff] [blame] | 388 | unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 389 | int ahci_stop_engine(struct ata_port *ap); |
Suman Tripathi | 39e0ee9 | 2014-07-07 22:33:04 +0530 | [diff] [blame] | 390 | void ahci_start_fis_rx(struct ata_port *ap); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 391 | void ahci_start_engine(struct ata_port *ap); |
| 392 | int ahci_check_ready(struct ata_link *link); |
| 393 | int ahci_kick_engine(struct ata_port *ap); |
David Milburn | 02cdfcf | 2010-11-12 15:38:21 -0600 | [diff] [blame] | 394 | int ahci_port_resume(struct ata_port *ap); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 395 | void ahci_set_em_messages(struct ahci_host_priv *hpriv, |
| 396 | struct ata_port_info *pi); |
| 397 | int ahci_reset_em(struct ata_host *host); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 398 | void ahci_print_info(struct ata_host *host, const char *scc_s); |
Robert Richter | 21bfd1a | 2015-05-31 13:55:18 +0200 | [diff] [blame] | 399 | int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht); |
Richard Zhu | 8b789d8 | 2013-10-15 10:44:54 +0800 | [diff] [blame] | 400 | void ahci_error_handler(struct ata_port *ap); |
Anton Vorontsov | 365cfa1 | 2010-03-28 00:22:14 -0400 | [diff] [blame] | 401 | |
| 402 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
| 403 | unsigned int port_no) |
| 404 | { |
| 405 | struct ahci_host_priv *hpriv = host->private_data; |
| 406 | void __iomem *mmio = hpriv->mmio; |
| 407 | |
| 408 | return mmio + 0x100 + (port_no * 0x80); |
| 409 | } |
| 410 | |
| 411 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
| 412 | { |
| 413 | return __ahci_port_base(ap->host, ap->port_no); |
| 414 | } |
| 415 | |
| 416 | static inline int ahci_nr_ports(u32 cap) |
| 417 | { |
| 418 | return (cap & 0x1f) + 1; |
| 419 | } |
| 420 | |
| 421 | #endif /* _AHCI_H */ |