Stepan Moskovchenko | 41f3f51 | 2011-02-24 18:00:39 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * You should have received a copy of the GNU General Public License |
| 13 | * along with this program; if not, write to the Free Software |
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 15 | * 02110-1301, USA. |
| 16 | */ |
| 17 | |
| 18 | #ifndef MSM_IOMMU_H |
| 19 | #define MSM_IOMMU_H |
| 20 | |
| 21 | #include <linux/interrupt.h> |
Stepan Moskovchenko | 41f3f51 | 2011-02-24 18:00:39 -0800 | [diff] [blame] | 22 | #include <linux/clk.h> |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 23 | |
Stepan Moskovchenko | 08bd683 | 2010-11-15 18:19:35 -0800 | [diff] [blame] | 24 | /* Sharability attributes of MSM IOMMU mappings */ |
| 25 | #define MSM_IOMMU_ATTR_NON_SH 0x0 |
| 26 | #define MSM_IOMMU_ATTR_SH 0x4 |
| 27 | |
| 28 | /* Cacheability attributes of MSM IOMMU mappings */ |
| 29 | #define MSM_IOMMU_ATTR_NONCACHED 0x0 |
| 30 | #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 |
| 31 | #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 |
| 32 | #define MSM_IOMMU_ATTR_CACHED_WT 0x3 |
| 33 | |
| 34 | /* Mask for the cache policy attribute */ |
| 35 | #define MSM_IOMMU_CP_MASK 0x03 |
| 36 | |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 37 | /* Maximum number of Machine IDs that we are allowing to be mapped to the same |
| 38 | * context bank. The number of MIDs mapped to the same CB does not affect |
| 39 | * performance, but there is a practical limit on how many distinct MIDs may |
| 40 | * be present. These mappings are typically determined at design time and are |
| 41 | * not expected to change at run time. |
| 42 | */ |
Stepan Moskovchenko | 23513c3 | 2010-11-12 19:29:47 -0800 | [diff] [blame] | 43 | #define MAX_NUM_MIDS 32 |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 44 | |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 45 | /* Maximum number of context banks that can be present in IOMMU */ |
| 46 | #define IOMMU_MAX_CBS 128 |
| 47 | |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 48 | /** |
| 49 | * struct msm_iommu_dev - a single IOMMU hardware instance |
Stepan Moskovchenko | a43d8c1 | 2011-02-24 18:00:42 -0800 | [diff] [blame] | 50 | * ncb Number of context banks present on this IOMMU HW instance |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 51 | * dev: IOMMU device |
| 52 | * irq: Interrupt number |
| 53 | * clk: The bus clock for this IOMMU hardware instance |
| 54 | * pclk: The clock for the IOMMU bus interconnect |
| 55 | * dev_node: list head in qcom_iommu_device_list |
| 56 | * dom_node: list head for domain |
| 57 | * ctx_list: list of 'struct msm_iommu_ctx_dev' |
| 58 | * context_map: Bitmap to track allocated context banks |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 59 | */ |
| 60 | struct msm_iommu_dev { |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 61 | void __iomem *base; |
Stepan Moskovchenko | a43d8c1 | 2011-02-24 18:00:42 -0800 | [diff] [blame] | 62 | int ncb; |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 63 | struct device *dev; |
| 64 | int irq; |
| 65 | struct clk *clk; |
| 66 | struct clk *pclk; |
| 67 | struct list_head dev_node; |
| 68 | struct list_head dom_node; |
| 69 | struct list_head ctx_list; |
| 70 | DECLARE_BITMAP(context_map, IOMMU_MAX_CBS); |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | /** |
| 74 | * struct msm_iommu_ctx_dev - an IOMMU context bank instance |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 75 | * of_node node ptr of client device |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 76 | * num Index of this context bank within the hardware |
| 77 | * mids List of Machine IDs that are to be mapped into this context |
| 78 | * bank, terminated by -1. The MID is a set of signals on the |
| 79 | * AXI bus that identifies the function associated with a specific |
| 80 | * memory request. (See ARM spec). |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 81 | * num_mids Total number of mids |
| 82 | * node list head in ctx_list |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 83 | */ |
| 84 | struct msm_iommu_ctx_dev { |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 85 | struct device_node *of_node; |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 86 | int num; |
| 87 | int mids[MAX_NUM_MIDS]; |
Sricharan R | 109bd48 | 2016-06-13 17:06:02 +0530 | [diff] [blame^] | 88 | int num_mids; |
| 89 | struct list_head list; |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 90 | }; |
| 91 | |
Stepan Moskovchenko | 0720d1f | 2010-08-24 18:31:10 -0700 | [diff] [blame] | 92 | /* |
| 93 | * Interrupt handler for the IOMMU context fault interrupt. Hooking the |
| 94 | * interrupt is not supported in the API yet, but this will print an error |
| 95 | * message and dump useful IOMMU registers. |
| 96 | */ |
| 97 | irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id); |
| 98 | |
| 99 | #endif |