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Linus Walleij2744e8a2011-05-02 20:50:54 +02001PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
Linus Walleijae6b4d82011-10-19 18:14:33 +020010- Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
12 load capacitance etc.
Linus Walleij2744e8a2011-05-02 20:50:54 +020013
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +000021 set drive strength, etc. for individual pins or groups of pins.
Linus Walleij2744e8a2011-05-02 20:50:54 +020022
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
30 pin exists.
31
Linus Walleij336cdba02011-11-10 09:27:41 +010032When a PIN CONTROLLER is instantiated, it will register a descriptor to the
Linus Walleij2744e8a2011-05-02 20:50:54 +020033pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38 A B C D E F G H
39
40 8 o o o o o o o o
41
42 7 o o o o o o o o
43
44 6 o o o o o o o o
45
46 5 o o o o o o o o
47
48 4 o o o o o o o o
49
50 3 o o o o o o o o
51
52 2 o o o o o o o o
53
54 1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
Linus Walleij336cdba02011-11-10 09:27:41 +010061const struct pinctrl_pin_desc foo_pins[] = {
62 PINCTRL_PIN(0, "A8"),
63 PINCTRL_PIN(1, "B8"),
64 PINCTRL_PIN(2, "C8"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020065 ...
Linus Walleij336cdba02011-11-10 09:27:41 +010066 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020069};
70
71static struct pinctrl_desc foo_desc = {
72 .name = "foo",
73 .pins = foo_pins,
74 .npins = ARRAY_SIZE(foo_pins),
Linus Walleij2744e8a2011-05-02 20:50:54 +020075 .owner = THIS_MODULE,
76};
77
78int __init foo_probe(void)
79{
80 struct pinctrl_dev *pctl;
81
Tony Lindgren950b0d92017-01-11 14:13:34 -080082 return pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl);
Linus Walleij2744e8a2011-05-02 20:50:54 +020083}
84
Linus Walleijae6b4d82011-10-19 18:14:33 +020085To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
86selected drivers, you need to select them from your machine's Kconfig entry,
87since these are so tightly integrated with the machines they are used on.
88See for example arch/arm/mach-u300/Kconfig for an example.
89
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +000090Pins usually have fancier names than this. You can find these in the datasheet
Linus Walleij2744e8a2011-05-02 20:50:54 +020091for your chip. Notice that the core pinctrl.h file provides a fancy macro
92called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
Linus Walleij336cdba02011-11-10 09:27:41 +010093the pins from 0 in the upper left corner to 63 in the lower right corner.
94This enumeration was arbitrarily chosen, in practice you need to think
Linus Walleij2744e8a2011-05-02 20:50:54 +020095through your numbering system so that it matches the layout of registers
96and such things in your driver, or the code may become complicated. You must
97also consider matching of offsets to the GPIO ranges that may be handled by
98the pin controller.
99
100For a padring with 467 pads, as opposed to actual pins, I used an enumeration
101like this, walking around the edge of the chip, which seems to be industry
102standard too (all these pads had names, too):
103
104
105 0 ..... 104
106 466 105
107 . .
108 . .
109 358 224
110 357 .... 225
111
112
113Pin groups
114==========
115
116Many controllers need to deal with groups of pins, so the pin controller
117subsystem has a mechanism for enumerating groups of pins and retrieving the
118actual enumerated pins that are part of a certain group.
119
120For example, say that we have a group of pins dealing with an SPI interface
121on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
122on { 24, 25 }.
123
124These two groups are presented to the pin control subsystem by implementing
125some generic pinctrl_ops like this:
126
127#include <linux/pinctrl/pinctrl.h>
128
129struct foo_group {
130 const char *name;
131 const unsigned int *pins;
132 const unsigned num_pins;
133};
134
Linus Walleij336cdba02011-11-10 09:27:41 +0100135static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
136static const unsigned int i2c0_pins[] = { 24, 25 };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200137
138static const struct foo_group foo_groups[] = {
139 {
140 .name = "spi0_grp",
141 .pins = spi0_pins,
142 .num_pins = ARRAY_SIZE(spi0_pins),
143 },
144 {
145 .name = "i2c0_grp",
146 .pins = i2c0_pins,
147 .num_pins = ARRAY_SIZE(i2c0_pins),
148 },
149};
150
151
Viresh Kumard1e90e92012-03-30 11:25:40 +0530152static int foo_get_groups_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200153{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530154 return ARRAY_SIZE(foo_groups);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200155}
156
157static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
158 unsigned selector)
159{
160 return foo_groups[selector].name;
161}
162
163static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
Baruch Siach838d0302015-03-09 19:20:30 +0200164 const unsigned **pins,
165 unsigned *num_pins)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200166{
167 *pins = (unsigned *) foo_groups[selector].pins;
168 *num_pins = foo_groups[selector].num_pins;
169 return 0;
170}
171
172static struct pinctrl_ops foo_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530173 .get_groups_count = foo_get_groups_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200174 .get_group_name = foo_get_group_name,
175 .get_group_pins = foo_get_group_pins,
176};
177
178
179static struct pinctrl_desc foo_desc = {
180 ...
181 .pctlops = &foo_pctrl_ops,
182};
183
Viresh Kumard1e90e92012-03-30 11:25:40 +0530184The pin control subsystem will call the .get_groups_count() function to
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000185determine the total number of legal selectors, then it will call the other functions
Viresh Kumard1e90e92012-03-30 11:25:40 +0530186to retrieve the name and pins of the group. Maintaining the data structure of
187the groups is up to the driver, this is just a simple example - in practice you
188may need more entries in your group structure, for example specific register
189ranges associated with each group and so on.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200190
191
Linus Walleijae6b4d82011-10-19 18:14:33 +0200192Pin configuration
193=================
194
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000195Pins can sometimes be software-configured in various ways, mostly related
Linus Walleijae6b4d82011-10-19 18:14:33 +0200196to their electronic properties when used as inputs or outputs. For example you
197may be able to make an output pin high impedance, or "tristate" meaning it is
198effectively disconnected. You may be able to connect an input pin to VDD or GND
199using a certain resistor value - pull up and pull down - so that the pin has a
200stable value when nothing is driving the rail it is connected to, or when it's
201unconnected.
202
Linus Walleijad42fc62013-06-24 15:06:19 +0200203Pin configuration can be programmed by adding configuration entries into the
204mapping table; see section "Board/machine configuration" below.
Linus Walleijae6b4d82011-10-19 18:14:33 +0200205
Stephen Warren1e2082b2012-03-02 13:05:48 -0700206The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
207above, is entirely defined by the pin controller driver.
208
209The pin configuration driver implements callbacks for changing pin
210configuration in the pin controller ops like this:
Linus Walleijae6b4d82011-10-19 18:14:33 +0200211
212#include <linux/pinctrl/pinctrl.h>
213#include <linux/pinctrl/pinconf.h>
214#include "platform_x_pindefs.h"
215
Dong Aishenge6337c32011-12-20 17:51:59 +0800216static int foo_pin_config_get(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200217 unsigned offset,
218 unsigned long *config)
219{
220 struct my_conftype conf;
221
222 ... Find setting for pin @ offset ...
223
224 *config = (unsigned long) conf;
225}
226
Dong Aishenge6337c32011-12-20 17:51:59 +0800227static int foo_pin_config_set(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200228 unsigned offset,
229 unsigned long config)
230{
231 struct my_conftype *conf = (struct my_conftype *) config;
232
233 switch (conf) {
234 case PLATFORM_X_PULL_UP:
235 ...
236 }
237 }
238}
239
Dong Aishenge6337c32011-12-20 17:51:59 +0800240static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200241 unsigned selector,
242 unsigned long *config)
243{
244 ...
245}
246
Dong Aishenge6337c32011-12-20 17:51:59 +0800247static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200248 unsigned selector,
249 unsigned long config)
250{
251 ...
252}
253
254static struct pinconf_ops foo_pconf_ops = {
255 .pin_config_get = foo_pin_config_get,
256 .pin_config_set = foo_pin_config_set,
257 .pin_config_group_get = foo_pin_config_group_get,
258 .pin_config_group_set = foo_pin_config_group_set,
259};
260
261/* Pin config operations are handled by some pin controller */
262static struct pinctrl_desc foo_desc = {
263 ...
264 .confops = &foo_pconf_ops,
265};
266
267Since some controllers have special logic for handling entire groups of pins
268they can exploit the special whole-group pin control function. The
269pin_config_group_set() callback is allowed to return the error code -EAGAIN,
270for groups it does not want to handle, or if it just wants to do some
271group-level handling and then fall through to iterate over all pins, in which
272case each individual pin will be treated by separate pin_config_set() calls as
273well.
274
275
Linus Walleij2744e8a2011-05-02 20:50:54 +0200276Interaction with the GPIO subsystem
277===================================
278
279The GPIO drivers may want to perform operations of various types on the same
280physical pins that are also registered as pin controller pins.
281
Linus Walleijc31a00c2012-09-10 17:22:00 +0200282First and foremost, the two subsystems can be used as completely orthogonal,
283see the section named "pin control requests from drivers" and
284"drivers needing both pin control and GPIOs" below for details. But in some
285situations a cross-subsystem mapping between pins and GPIOs is needed.
286
Andrew Jeffery73f8fed2016-06-10 16:46:36 +0930287Since the pin controller subsystem has its pinspace local to the pin controller
288we need a mapping so that the pin control subsystem can figure out which pin
289controller handles control of a certain GPIO pin. Since a single pin controller
290may be muxing several GPIO ranges (typically SoCs that have one set of pins,
291but internally several GPIO silicon blocks, each modelled as a struct
292gpio_chip) any number of GPIO ranges can be added to a pin controller instance
293like this:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200294
295struct gpio_chip chip_a;
296struct gpio_chip chip_b;
297
298static struct pinctrl_gpio_range gpio_range_a = {
299 .name = "chip a",
300 .id = 0,
301 .base = 32,
Chanho Park3c739ad2011-11-11 18:47:58 +0900302 .pin_base = 32,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200303 .npins = 16,
304 .gc = &chip_a;
305};
306
Chanho Park3c739ad2011-11-11 18:47:58 +0900307static struct pinctrl_gpio_range gpio_range_b = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200308 .name = "chip b",
309 .id = 0,
310 .base = 48,
Chanho Park3c739ad2011-11-11 18:47:58 +0900311 .pin_base = 64,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200312 .npins = 8,
313 .gc = &chip_b;
314};
315
Linus Walleij2744e8a2011-05-02 20:50:54 +0200316{
317 struct pinctrl_dev *pctl;
318 ...
319 pinctrl_add_gpio_range(pctl, &gpio_range_a);
320 pinctrl_add_gpio_range(pctl, &gpio_range_b);
321}
322
323So this complex system has one pin controller handling two different
Chanho Park3c739ad2011-11-11 18:47:58 +0900324GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
325"chip b" have different .pin_base, which means a start pin number of the
326GPIO range.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200327
Chanho Park3c739ad2011-11-11 18:47:58 +0900328The GPIO range of "chip a" starts from the GPIO base of 32 and actual
329pin range also starts from 32. However "chip b" has different starting
330offset for the GPIO range and pin range. The GPIO range of "chip b" starts
331from GPIO number 48, while the pin range of "chip b" starts from 64.
332
333We can convert a gpio number to actual pin number using this "pin_base".
334They are mapped in the global GPIO pin space at:
335
336chip a:
337 - GPIO range : [32 .. 47]
338 - pin range : [32 .. 47]
339chip b:
340 - GPIO range : [48 .. 55]
341 - pin range : [64 .. 71]
Linus Walleij2744e8a2011-05-02 20:50:54 +0200342
Linus Walleij30cf8212013-06-16 12:15:36 +0200343The above examples assume the mapping between the GPIOs and pins is
344linear. If the mapping is sparse or haphazard, an array of arbitrary pin
345numbers can be encoded in the range like this:
346
347static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
348
349static struct pinctrl_gpio_range gpio_range = {
350 .name = "chip",
351 .id = 0,
352 .base = 32,
353 .pins = &range_pins,
354 .npins = ARRAY_SIZE(range_pins),
355 .gc = &chip;
356};
357
Christian Ruppertfe610522013-10-16 14:56:54 +0200358In this case the pin_base property will be ignored. If the name of a pin
359group is known, the pins and npins elements of the above structure can be
360initialised using the function pinctrl_get_group_pins(), e.g. for pin
361group "foo":
362
363pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
Linus Walleij30cf8212013-06-16 12:15:36 +0200364
Linus Walleij2744e8a2011-05-02 20:50:54 +0200365When GPIO-specific functions in the pin control subsystem are called, these
Linus Walleij336cdba02011-11-10 09:27:41 +0100366ranges will be used to look up the appropriate pin controller by inspecting
Linus Walleij2744e8a2011-05-02 20:50:54 +0200367and matching the pin to the pin ranges across all controllers. When a
368pin controller handling the matching range is found, GPIO-specific functions
369will be called on that specific pin controller.
370
371For all functionalities dealing with pin biasing, pin muxing etc, the pin
Linus Walleij30cf8212013-06-16 12:15:36 +0200372controller subsystem will look up the corresponding pin number from the passed
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000373in gpio number, and use the range's internals to retrieve a pin number. After
Linus Walleij30cf8212013-06-16 12:15:36 +0200374that, the subsystem passes it on to the pin control driver, so the driver
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000375will get a pin number into its handled number range. Further it is also passed
Linus Walleij2744e8a2011-05-02 20:50:54 +0200376the range ID value, so that the pin controller knows which range it should
377deal with.
378
Shiraz Hashimf23f1512012-10-27 15:21:36 +0530379Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
380section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
381pinctrl and gpio drivers.
Linus Walleijc31a00c2012-09-10 17:22:00 +0200382
Linus Walleij30cf8212013-06-16 12:15:36 +0200383
Linus Walleij2744e8a2011-05-02 20:50:54 +0200384PINMUX interfaces
385=================
386
387These calls use the pinmux_* naming prefix. No other calls should use that
388prefix.
389
390
391What is pinmuxing?
392==================
393
394PINMUX, also known as padmux, ballmux, alternate functions or mission modes
395is a way for chip vendors producing some kind of electrical packages to use
396a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
397functions, depending on the application. By "application" in this context
398we usually mean a way of soldering or wiring the package into an electronic
399system, even though the framework makes it possible to also change the function
400at runtime.
401
402Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
403
404 A B C D E F G H
405 +---+
406 8 | o | o o o o o o o
407 | |
408 7 | o | o o o o o o o
409 | |
410 6 | o | o o o o o o o
411 +---+---+
412 5 | o | o | o o o o o o
413 +---+---+ +---+
414 4 o o o o o o | o | o
415 | |
416 3 o o o o o o | o | o
417 | |
418 2 o o o o o o | o | o
419 +-------+-------+-------+---+---+
420 1 | o o | o o | o o | o | o |
421 +-------+-------+-------+---+---+
422
423This is not tetris. The game to think of is chess. Not all PGA/BGA packages
424are chessboard-like, big ones have "holes" in some arrangement according to
425different design patterns, but we're using this as a simple example. Of the
426pins you see some will be taken by things like a few VCC and GND to feed power
427to the chip, and quite a few will be taken by large ports like an external
428memory interface. The remaining pins will often be subject to pin multiplexing.
429
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000430The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
431to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
Linus Walleij2744e8a2011-05-02 20:50:54 +0200432pinctrl_register_pins() and a suitable data set as shown earlier.
433
434In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
435(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
436some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
437be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
438we cannot use the SPI port and I2C port at the same time. However in the inside
439of the package the silicon performing the SPI logic can alternatively be routed
440out on pins { G4, G3, G2, G1 }.
441
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000442On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
Linus Walleij2744e8a2011-05-02 20:50:54 +0200443special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
444consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
445{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
446port on pins { G4, G3, G2, G1 } of course.
447
448This way the silicon blocks present inside the chip can be multiplexed "muxed"
449out on different pin ranges. Often contemporary SoC (systems on chip) will
450contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
451different pins by pinmux settings.
452
453Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
454common to be able to use almost any pin as a GPIO pin if it is not currently
455in use by some other I/O port.
456
457
458Pinmux conventions
459==================
460
461The purpose of the pinmux functionality in the pin controller subsystem is to
462abstract and provide pinmux settings to the devices you choose to instantiate
463in your machine configuration. It is inspired by the clk, GPIO and regulator
464subsystems, so devices will request their mux setting, but it's also possible
465to request a single pin for e.g. GPIO.
466
467Definitions:
468
469- FUNCTIONS can be switched in and out by a driver residing with the pin
470 control subsystem in the drivers/pinctrl/* directory of the kernel. The
471 pin control driver knows the possible functions. In the example above you can
472 identify three pinmux functions, one for spi, one for i2c and one for mmc.
473
474- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
475 In this case the array could be something like: { spi0, i2c0, mmc0 }
476 for the three available functions.
477
478- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
479 function is *always* associated with a certain set of pin groups, could
480 be just a single one, but could also be many. In the example above the
481 function i2c is associated with the pins { A5, B5 }, enumerated as
482 { 24, 25 } in the controller pin space.
483
484 The Function spi is associated with pin groups { A8, A7, A6, A5 }
485 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
486 { 38, 46, 54, 62 } respectively.
487
488 Group names must be unique per pin controller, no two groups on the same
489 controller may have the same name.
490
491- The combination of a FUNCTION and a PIN GROUP determine a certain function
492 for a certain set of pins. The knowledge of the functions and pin groups
493 and their machine-specific particulars are kept inside the pinmux driver,
Andrew Jeffery191a79f2016-06-10 16:46:34 +0930494 from the outside only the enumerators are known, and the driver core can
495 request:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200496
Andrew Jeffery191a79f2016-06-10 16:46:34 +0930497 - The name of a function with a certain selector (>= 0)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200498 - A list of groups associated with a certain function
Andrew Jeffery191a79f2016-06-10 16:46:34 +0930499 - That a certain group in that list to be activated for a certain function
Linus Walleij2744e8a2011-05-02 20:50:54 +0200500
501 As already described above, pin groups are in turn self-descriptive, so
502 the core will retrieve the actual pin range in a certain group from the
503 driver.
504
505- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
506 device by the board file, device tree or similar machine setup configuration
507 mechanism, similar to how regulators are connected to devices, usually by
508 name. Defining a pin controller, function and group thus uniquely identify
509 the set of pins to be used by a certain device. (If only one possible group
510 of pins is available for the function, no group name need to be supplied -
511 the core will simply select the first and only group available.)
512
513 In the example case we can define that this particular machine shall
514 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
515 fi2c0 group gi2c0, on the primary pin controller, we get mappings
516 like these:
517
518 {
519 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
520 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
521 }
522
Stephen Warren1681f5a2012-02-22 14:25:58 -0700523 Every map must be assigned a state name, pin controller, device and
524 function. The group is not compulsory - if it is omitted the first group
525 presented by the driver as applicable for the function will be selected,
526 which is useful for simple cases.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200527
528 It is possible to map several groups to the same combination of device,
529 pin controller and function. This is for cases where a certain function on
530 a certain pin controller may use different sets of pins in different
531 configurations.
532
533- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
534 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
535 other device mux setting or GPIO pin request has already taken your physical
536 pin, you will be denied the use of it. To get (activate) a new setting, the
537 old one has to be put (deactivated) first.
538
539Sometimes the documentation and hardware registers will be oriented around
540pads (or "fingers") rather than pins - these are the soldering surfaces on the
541silicon inside the package, and may or may not match the actual number of
542pins/balls underneath the capsule. Pick some enumeration that makes sense to
543you. Define enumerators only for the pins you can control if that makes sense.
544
545Assumptions:
546
Linus Walleij336cdba02011-11-10 09:27:41 +0100547We assume that the number of possible function maps to pin groups is limited by
Linus Walleij2744e8a2011-05-02 20:50:54 +0200548the hardware. I.e. we assume that there is no system where any function can be
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000549mapped to any pin, like in a phone exchange. So the available pin groups for
Linus Walleij2744e8a2011-05-02 20:50:54 +0200550a certain function will be limited to a few choices (say up to eight or so),
551not hundreds or any amount of choices. This is the characteristic we have found
552by inspecting available pinmux hardware, and a necessary assumption since we
553expect pinmux drivers to present *all* possible function vs pin group mappings
554to the subsystem.
555
556
557Pinmux drivers
558==============
559
560The pinmux core takes care of preventing conflicts on pins and calling
561the pin controller driver to execute different settings.
562
563It is the responsibility of the pinmux driver to impose further restrictions
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000564(say for example infer electronic limitations due to load, etc.) to determine
Linus Walleij2744e8a2011-05-02 20:50:54 +0200565whether or not the requested function can actually be allowed, and in case it
566is possible to perform the requested mux setting, poke the hardware so that
567this happens.
568
569Pinmux drivers are required to supply a few callback functions, some are
Baruch Siach260463d2015-03-08 10:51:45 +0200570optional. Usually the set_mux() function is implemented, writing values into
571some certain registers to activate a certain mux setting for a certain pin.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200572
573A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
574into some register named MUX to select a certain function with a certain
575group of pins would work something like this:
576
577#include <linux/pinctrl/pinctrl.h>
578#include <linux/pinctrl/pinmux.h>
579
580struct foo_group {
581 const char *name;
582 const unsigned int *pins;
583 const unsigned num_pins;
584};
585
586static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
587static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
588static const unsigned i2c0_pins[] = { 24, 25 };
589static const unsigned mmc0_1_pins[] = { 56, 57 };
590static const unsigned mmc0_2_pins[] = { 58, 59 };
591static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
592
593static const struct foo_group foo_groups[] = {
594 {
595 .name = "spi0_0_grp",
596 .pins = spi0_0_pins,
597 .num_pins = ARRAY_SIZE(spi0_0_pins),
598 },
599 {
600 .name = "spi0_1_grp",
601 .pins = spi0_1_pins,
602 .num_pins = ARRAY_SIZE(spi0_1_pins),
603 },
604 {
605 .name = "i2c0_grp",
606 .pins = i2c0_pins,
607 .num_pins = ARRAY_SIZE(i2c0_pins),
608 },
609 {
610 .name = "mmc0_1_grp",
611 .pins = mmc0_1_pins,
612 .num_pins = ARRAY_SIZE(mmc0_1_pins),
613 },
614 {
615 .name = "mmc0_2_grp",
616 .pins = mmc0_2_pins,
617 .num_pins = ARRAY_SIZE(mmc0_2_pins),
618 },
619 {
620 .name = "mmc0_3_grp",
621 .pins = mmc0_3_pins,
622 .num_pins = ARRAY_SIZE(mmc0_3_pins),
623 },
624};
625
626
Viresh Kumard1e90e92012-03-30 11:25:40 +0530627static int foo_get_groups_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200628{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530629 return ARRAY_SIZE(foo_groups);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200630}
631
632static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
633 unsigned selector)
634{
635 return foo_groups[selector].name;
636}
637
638static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
639 unsigned ** const pins,
640 unsigned * const num_pins)
641{
642 *pins = (unsigned *) foo_groups[selector].pins;
643 *num_pins = foo_groups[selector].num_pins;
644 return 0;
645}
646
647static struct pinctrl_ops foo_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530648 .get_groups_count = foo_get_groups_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200649 .get_group_name = foo_get_group_name,
650 .get_group_pins = foo_get_group_pins,
651};
652
653struct foo_pmx_func {
654 const char *name;
655 const char * const *groups;
656 const unsigned num_groups;
657};
658
Viresh Kumareb181c32012-03-29 11:03:27 +0530659static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200660static const char * const i2c0_groups[] = { "i2c0_grp" };
661static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
662 "mmc0_3_grp" };
663
664static const struct foo_pmx_func foo_functions[] = {
665 {
666 .name = "spi0",
667 .groups = spi0_groups,
668 .num_groups = ARRAY_SIZE(spi0_groups),
669 },
670 {
671 .name = "i2c0",
672 .groups = i2c0_groups,
673 .num_groups = ARRAY_SIZE(i2c0_groups),
674 },
675 {
676 .name = "mmc0",
677 .groups = mmc0_groups,
678 .num_groups = ARRAY_SIZE(mmc0_groups),
679 },
680};
681
Baruch Siachc58e0312015-03-08 12:03:05 +0200682static int foo_get_functions_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200683{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530684 return ARRAY_SIZE(foo_functions);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200685}
686
Baruch Siachc58e0312015-03-08 12:03:05 +0200687static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200688{
Linus Walleij336cdba02011-11-10 09:27:41 +0100689 return foo_functions[selector].name;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200690}
691
692static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
693 const char * const **groups,
694 unsigned * const num_groups)
695{
696 *groups = foo_functions[selector].groups;
697 *num_groups = foo_functions[selector].num_groups;
698 return 0;
699}
700
Baruch Siachc58e0312015-03-08 12:03:05 +0200701static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200702 unsigned group)
703{
Linus Walleij336cdba02011-11-10 09:27:41 +0100704 u8 regbit = (1 << selector + group);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200705
706 writeb((readb(MUX)|regbit), MUX)
707 return 0;
708}
709
Baruch Siachc58e0312015-03-08 12:03:05 +0200710static struct pinmux_ops foo_pmxops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530711 .get_functions_count = foo_get_functions_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200712 .get_function_name = foo_get_fname,
713 .get_function_groups = foo_get_groups,
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200714 .set_mux = foo_set_mux,
Linus Walleij8c4c2012015-05-06 14:19:13 +0200715 .strict = true,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200716};
717
718/* Pinmux operations are handled by some pin controller */
719static struct pinctrl_desc foo_desc = {
720 ...
721 .pctlops = &foo_pctrl_ops,
722 .pmxops = &foo_pmxops,
723};
724
725In the example activating muxing 0 and 1 at the same time setting bits
7260 and 1, uses one pin in common so they would collide.
727
728The beauty of the pinmux subsystem is that since it keeps track of all
729pins and who is using them, it will already have denied an impossible
730request like that, so the driver does not need to worry about such
731things - when it gets a selector passed in, the pinmux subsystem makes
732sure no other device or GPIO assignment is already using the selected
733pins. Thus bits 0 and 1 in the control register will never be set at the
734same time.
735
736All the above functions are mandatory to implement for a pinmux driver.
737
738
Linus Walleije93bcee2012-02-09 07:23:28 +0100739Pin control interaction with the GPIO subsystem
740===============================================
Linus Walleij2744e8a2011-05-02 20:50:54 +0200741
Linus Walleijfdba2d02013-03-15 12:01:20 +0100742Note that the following implies that the use case is to use a certain pin
743from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
744and similar functions. There are cases where you may be using something
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000745that your datasheet calls "GPIO mode", but actually is just an electrical
Linus Walleijfdba2d02013-03-15 12:01:20 +0100746configuration for a certain device. See the section below named
747"GPIO mode pitfalls" for more details on this scenario.
748
Linus Walleije93bcee2012-02-09 07:23:28 +0100749The public pinmux API contains two functions named pinctrl_request_gpio()
750and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
Linus Walleij542e7042011-11-14 10:06:22 +0100751gpiolib-based drivers as part of their gpio_request() and
Linus Walleije93bcee2012-02-09 07:23:28 +0100752gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
Linus Walleij542e7042011-11-14 10:06:22 +0100753shall only be called from within respective gpio_direction_[input|output]
754gpiolib implementation.
755
756NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
Linus Walleije93bcee2012-02-09 07:23:28 +0100757controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
758that driver request proper muxing and other control for its pins.
Linus Walleij542e7042011-11-14 10:06:22 +0100759
Linus Walleij2744e8a2011-05-02 20:50:54 +0200760The function list could become long, especially if you can convert every
761individual pin into a GPIO pin independent of any other pins, and then try
762the approach to define every pin as a function.
763
764In this case, the function array would become 64 entries for each GPIO
765setting and then the device functions.
766
Linus Walleije93bcee2012-02-09 07:23:28 +0100767For this reason there are two functions a pin control driver can implement
Linus Walleij542e7042011-11-14 10:06:22 +0100768to enable only GPIO on an individual pin: .gpio_request_enable() and
769.gpio_disable_free().
Linus Walleij2744e8a2011-05-02 20:50:54 +0200770
771This function will pass in the affected GPIO range identified by the pin
772controller core, so you know which GPIO pins are being affected by the request
773operation.
774
Linus Walleij542e7042011-11-14 10:06:22 +0100775If your driver needs to have an indication from the framework of whether the
776GPIO pin shall be used for input or output you can implement the
777.gpio_set_direction() function. As described this shall be called from the
778gpiolib driver and the affected GPIO range, pin offset and desired direction
779will be passed along to this function.
780
781Alternatively to using these special functions, it is fully allowed to use
Linus Walleije93bcee2012-02-09 07:23:28 +0100782named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
Linus Walleij542e7042011-11-14 10:06:22 +0100783obtain the function "gpioN" where "N" is the global GPIO pin number if no
784special GPIO-handler is registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200785
786
Linus Walleijfdba2d02013-03-15 12:01:20 +0100787GPIO mode pitfalls
788==================
789
Linus Walleijeb6002d2013-06-25 16:17:15 +0200790Due to the naming conventions used by hardware engineers, where "GPIO"
791is taken to mean different things than what the kernel does, the developer
792may be confused by a datasheet talking about a pin being possible to set
793into "GPIO mode". It appears that what hardware engineers mean with
794"GPIO mode" is not necessarily the use case that is implied in the kernel
795interface <linux/gpio.h>: a pin that you grab from kernel code and then
796either listen for input or drive high/low to assert/deassert some
797external line.
Linus Walleijfdba2d02013-03-15 12:01:20 +0100798
799Rather hardware engineers think that "GPIO mode" means that you can
800software-control a few electrical properties of the pin that you would
801not be able to control if the pin was in some other mode, such as muxed in
802for a device.
803
Linus Walleijeb6002d2013-06-25 16:17:15 +0200804The GPIO portions of a pin and its relation to a certain pin controller
805configuration and muxing logic can be constructed in several ways. Here
806are two examples:
807
808(A)
809 pin config
810 logic regs
811 | +- SPI
812 Physical pins --- pad --- pinmux -+- I2C
813 | +- mmc
814 | +- GPIO
815 pin
816 multiplex
817 logic regs
818
819Here some electrical properties of the pin can be configured no matter
820whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
821pin, you can also drive it high/low from "GPIO" registers.
822Alternatively, the pin can be controlled by a certain peripheral, while
823still applying desired pin config properties. GPIO functionality is thus
824orthogonal to any other device using the pin.
825
826In this arrangement the registers for the GPIO portions of the pin controller,
827or the registers for the GPIO hardware module are likely to reside in a
828separate memory range only intended for GPIO driving, and the register
829range dealing with pin config and pin multiplexing get placed into a
830different memory range and a separate section of the data sheet.
831
Andy Shevchenko74409262016-06-21 01:40:48 +0300832A flag "strict" in struct pinmux_ops is available to check and deny
Sonic Zhangfa76a3d2015-04-09 11:13:07 +0800833simultaneous access to the same pin from GPIO and pin multiplexing
834consumers on hardware of this type. The pinctrl driver should set this flag
835accordingly.
836
Linus Walleijeb6002d2013-06-25 16:17:15 +0200837(B)
838
839 pin config
840 logic regs
841 | +- SPI
842 Physical pins --- pad --- pinmux -+- I2C
843 | | +- mmc
844 | |
845 GPIO pin
846 multiplex
847 logic regs
848
849In this arrangement, the GPIO functionality can always be enabled, such that
850e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
851pulsed out. It is likely possible to disrupt the traffic on the pin by doing
852wrong things on the GPIO block, as it is never really disconnected. It is
853possible that the GPIO, pin config and pin multiplex registers are placed into
854the same memory range and the same section of the data sheet, although that
855need not be the case.
856
Sonic Zhangfa76a3d2015-04-09 11:13:07 +0800857In some pin controllers, although the physical pins are designed in the same
858way as (B), the GPIO function still can't be enabled at the same time as the
859peripheral functions. So again the "strict" flag should be set, denying
860simultaneous activation by GPIO and other muxed in devices.
861
Linus Walleijeb6002d2013-06-25 16:17:15 +0200862From a kernel point of view, however, these are different aspects of the
863hardware and shall be put into different subsystems:
864
865- Registers (or fields within registers) that control electrical
866 properties of the pin such as biasing and drive strength should be
867 exposed through the pinctrl subsystem, as "pin configuration" settings.
868
869- Registers (or fields within registers) that control muxing of signals
870 from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000871 be exposed through the pinctrl subsystem, as mux functions.
Linus Walleijeb6002d2013-06-25 16:17:15 +0200872
873- Registers (or fields within registers) that control GPIO functionality
874 such as setting a GPIO's output value, reading a GPIO's input value, or
875 setting GPIO pin direction should be exposed through the GPIO subsystem,
876 and if they also support interrupt capabilities, through the irqchip
877 abstraction.
878
879Depending on the exact HW register design, some functions exposed by the
880GPIO subsystem may call into the pinctrl subsystem in order to
881co-ordinate register settings across HW modules. In particular, this may
882be needed for HW with separate GPIO and pin controller HW modules, where
883e.g. GPIO direction is determined by a register in the pin controller HW
884module rather than the GPIO HW module.
885
886Electrical properties of the pin such as biasing and drive strength
887may be placed at some pin-specific register in all cases or as part
888of the GPIO register in case (B) especially. This doesn't mean that such
889properties necessarily pertain to what the Linux kernel calls "GPIO".
890
Linus Walleijfdba2d02013-03-15 12:01:20 +0100891Example: a pin is usually muxed in to be used as a UART TX line. But during
892system sleep, we need to put this pin into "GPIO mode" and ground it.
893
894If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000895to think that you need to come up with something really complex, that the
Linus Walleijfdba2d02013-03-15 12:01:20 +0100896pin shall be used for UART TX and GPIO at the same time, that you will grab
897a pin control handle and set it to a certain state to enable UART TX to be
898muxed in, then twist it over to GPIO mode and use gpio_direction_output()
899to drive it low during sleep, then mux it over to UART TX again when you
900wake up and maybe even gpio_request/gpio_free as part of this cycle. This
901all gets very complicated.
902
903The solution is to not think that what the datasheet calls "GPIO mode"
904has to be handled by the <linux/gpio.h> interface. Instead view this as
905a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
906and you find this in the documentation:
907
908 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
909 1 to indicate high level, argument 0 to indicate low level.
910
911So it is perfectly possible to push a pin into "GPIO mode" and drive the
912line low as part of the usual pin control map. So for example your UART
913driver may look like this:
914
915#include <linux/pinctrl/consumer.h>
916
917struct pinctrl *pinctrl;
918struct pinctrl_state *pins_default;
919struct pinctrl_state *pins_sleep;
920
921pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
922pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
923
924/* Normal mode */
925retval = pinctrl_select_state(pinctrl, pins_default);
926/* Sleep mode */
927retval = pinctrl_select_state(pinctrl, pins_sleep);
928
929And your machine configuration may look like this:
930--------------------------------------------------
931
932static unsigned long uart_default_mode[] = {
933 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
934};
935
936static unsigned long uart_sleep_mode[] = {
937 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
938};
939
Sachin Kamat2868a072013-08-08 10:50:59 +0530940static struct pinctrl_map pinmap[] __initdata = {
Linus Walleijfdba2d02013-03-15 12:01:20 +0100941 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
942 "u0_group", "u0"),
943 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
944 "UART_TX_PIN", uart_default_mode),
945 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
946 "u0_group", "gpio-mode"),
947 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
948 "UART_TX_PIN", uart_sleep_mode),
949};
950
951foo_init(void) {
952 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
953}
954
955Here the pins we want to control are in the "u0_group" and there is some
956function called "u0" that can be enabled on this group of pins, and then
957everything is UART business as usual. But there is also some function
958named "gpio-mode" that can be mapped onto the same pins to move them into
959GPIO mode.
960
961This will give the desired effect without any bogus interaction with the
962GPIO subsystem. It is just an electrical configuration used by that device
963when going to sleep, it might imply that the pin is set into something the
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000964datasheet calls "GPIO mode", but that is not the point: it is still used
Linus Walleijfdba2d02013-03-15 12:01:20 +0100965by that UART device to control the pins that pertain to that very UART
966driver, putting them into modes needed by the UART. GPIO in the Linux
967kernel sense are just some 1-bit line, and is a different use case.
968
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000969How the registers are poked to attain the push or pull, and output low
Linus Walleijfdba2d02013-03-15 12:01:20 +0100970configuration and the muxing of the "u0" or "gpio-mode" group onto these
971pins is a question for the driver.
972
973Some datasheets will be more helpful and refer to the "GPIO mode" as
974"low power mode" rather than anything to do with GPIO. This often means
975the same thing electrically speaking, but in this latter case the
976software engineers will usually quickly identify that this is some
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000977specific muxing or configuration rather than anything related to the GPIO
Linus Walleijfdba2d02013-03-15 12:01:20 +0100978API.
979
980
Stephen Warren1e2082b2012-03-02 13:05:48 -0700981Board/machine configuration
Linus Walleij2744e8a2011-05-02 20:50:54 +0200982==================================
983
984Boards and machines define how a certain complete running system is put
985together, including how GPIOs and devices are muxed, how regulators are
986constrained and how the clock tree looks. Of course pinmux settings are also
987part of this.
988
Stephen Warren1e2082b2012-03-02 13:05:48 -0700989A pin controller configuration for a machine looks pretty much like a simple
990regulator configuration, so for the example array above we want to enable i2c
991and spi on the second function mapping:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200992
993#include <linux/pinctrl/machine.h>
994
Uwe Kleine-König122dbe72012-03-30 22:04:51 +0200995static const struct pinctrl_map mapping[] __initconst = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200996 {
Stephen Warren806d3142012-02-23 17:04:39 -0700997 .dev_name = "foo-spi.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -0700998 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -0700999 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001000 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001001 .data.mux.function = "spi0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001002 },
1003 {
Stephen Warren806d3142012-02-23 17:04:39 -07001004 .dev_name = "foo-i2c.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -07001005 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001006 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001007 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001008 .data.mux.function = "i2c0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001009 },
1010 {
Stephen Warren806d3142012-02-23 17:04:39 -07001011 .dev_name = "foo-mmc.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -07001012 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001013 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001014 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001015 .data.mux.function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001016 },
1017};
1018
1019The dev_name here matches to the unique device name that can be used to look
1020up the device struct (just like with clockdev or regulators). The function name
1021must match a function provided by the pinmux driver handling this pin range.
1022
1023As you can see we may have several pin controllers on the system and thus
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +00001024we need to specify which one of them contains the functions we wish to map.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001025
1026You register this pinmux mapping to the pinmux subsystem by simply:
1027
Linus Walleije93bcee2012-02-09 07:23:28 +01001028 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
Linus Walleij2744e8a2011-05-02 20:50:54 +02001029
1030Since the above construct is pretty common there is a helper macro to make
Stephen Warren51cd24e2011-12-09 16:59:05 -07001031it even more compact which assumes you want to use pinctrl-foo and position
Linus Walleij2744e8a2011-05-02 20:50:54 +020010320 for mapping, for example:
1033
Sachin Kamat2868a072013-08-08 10:50:59 +05301034static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001035 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1036};
1037
1038The mapping table may also contain pin configuration entries. It's common for
1039each pin/group to have a number of configuration entries that affect it, so
1040the table entries for configuration reference an array of config parameters
1041and values. An example using the convenience macros is shown below:
1042
1043static unsigned long i2c_grp_configs[] = {
1044 FOO_PIN_DRIVEN,
1045 FOO_PIN_PULLUP,
1046};
1047
1048static unsigned long i2c_pin_configs[] = {
1049 FOO_OPEN_COLLECTOR,
1050 FOO_SLEW_RATE_SLOW,
1051};
1052
Sachin Kamat2868a072013-08-08 10:50:59 +05301053static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001054 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
Daniel Mackd1a83d32012-08-09 21:02:19 +02001055 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1056 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1057 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
Stephen Warren1e2082b2012-03-02 13:05:48 -07001058};
1059
1060Finally, some devices expect the mapping table to contain certain specific
1061named states. When running on hardware that doesn't need any pin controller
1062configuration, the mapping table must still contain those named states, in
1063order to explicitly indicate that the states were provided and intended to
1064be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1065a named state without causing any pin controller to be programmed:
1066
Sachin Kamat2868a072013-08-08 10:50:59 +05301067static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001068 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
Linus Walleij2744e8a2011-05-02 20:50:54 +02001069};
1070
1071
1072Complex mappings
1073================
1074
1075As it is possible to map a function to different groups of pins an optional
1076.group can be specified like this:
1077
1078...
1079{
Stephen Warren806d3142012-02-23 17:04:39 -07001080 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001081 .name = "spi0-pos-A",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001082 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001083 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001084 .function = "spi0",
1085 .group = "spi0_0_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001086},
1087{
Stephen Warren806d3142012-02-23 17:04:39 -07001088 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001089 .name = "spi0-pos-B",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001090 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001091 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001092 .function = "spi0",
1093 .group = "spi0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001094},
1095...
1096
1097This example mapping is used to switch between two positions for spi0 at
1098runtime, as described further below under the heading "Runtime pinmuxing".
1099
Stephen Warren6e5e9592012-03-02 13:05:47 -07001100Further it is possible for one named state to affect the muxing of several
1101groups of pins, say for example in the mmc0 example above, where you can
Linus Walleij2744e8a2011-05-02 20:50:54 +02001102additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1103three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1104case), we define a mapping like this:
1105
1106...
1107{
Stephen Warren806d3142012-02-23 17:04:39 -07001108 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001109 .name = "2bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001110 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001111 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001112 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +01001113 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001114},
1115{
Stephen Warren806d3142012-02-23 17:04:39 -07001116 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001117 .name = "4bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001118 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001119 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001120 .function = "mmc0",
1121 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001122},
1123{
Stephen Warren806d3142012-02-23 17:04:39 -07001124 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001125 .name = "4bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001126 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001127 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001128 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +01001129 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001130},
1131{
Stephen Warren806d3142012-02-23 17:04:39 -07001132 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001133 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001134 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001135 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren6e5e9592012-03-02 13:05:47 -07001136 .function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001137 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001138},
1139{
Stephen Warren806d3142012-02-23 17:04:39 -07001140 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001141 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001142 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001143 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001144 .function = "mmc0",
1145 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001146},
Linus Walleij336cdba02011-11-10 09:27:41 +01001147{
Stephen Warren806d3142012-02-23 17:04:39 -07001148 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001149 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001150 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001151 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij336cdba02011-11-10 09:27:41 +01001152 .function = "mmc0",
1153 .group = "mmc0_3_grp",
Linus Walleij336cdba02011-11-10 09:27:41 +01001154},
Linus Walleij2744e8a2011-05-02 20:50:54 +02001155...
1156
1157The result of grabbing this mapping from the device with something like
1158this (see next paragraph):
1159
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001160 p = devm_pinctrl_get(dev);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001161 s = pinctrl_lookup_state(p, "8bit");
1162 ret = pinctrl_select_state(p, s);
1163
1164or more simply:
1165
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001166 p = devm_pinctrl_get_select(dev, "8bit");
Linus Walleij2744e8a2011-05-02 20:50:54 +02001167
1168Will be that you activate all the three bottom records in the mapping at
Stephen Warren6e5e9592012-03-02 13:05:47 -07001169once. Since they share the same name, pin controller device, function and
Linus Walleij2744e8a2011-05-02 20:50:54 +02001170device, and since we allow multiple groups to match to a single device, they
1171all get selected, and they all get enabled and disable simultaneously by the
1172pinmux core.
1173
1174
Linus Walleijc31a00c2012-09-10 17:22:00 +02001175Pin control requests from drivers
1176=================================
Linus Walleij2744e8a2011-05-02 20:50:54 +02001177
Linus Walleijab780292013-01-22 10:56:14 -07001178When a device driver is about to probe the device core will automatically
1179attempt to issue pinctrl_get_select_default() on these devices.
1180This way driver writers do not need to add any of the boilerplate code
1181of the type found below. However when doing fine-grained state selection
1182and not using the "default" state, you may have to do some device driver
1183handling of the pinctrl handles and states.
1184
1185So if you just want to put the pins for a certain device into the default
1186state and be done with it, there is nothing you need to do besides
1187providing the proper mapping table. The device core will take care of
1188the rest.
1189
Linus Walleije93bcee2012-02-09 07:23:28 +01001190Generally it is discouraged to let individual drivers get and enable pin
1191control. So if possible, handle the pin control in platform code or some other
1192place where you have access to all the affected struct device * pointers. In
1193some cases where a driver needs to e.g. switch between different mux mappings
1194at runtime this is not possible.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001195
Linus Walleijc31a00c2012-09-10 17:22:00 +02001196A typical case is if a driver needs to switch bias of pins from normal
1197operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1198PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1199current in sleep mode.
1200
Linus Walleije93bcee2012-02-09 07:23:28 +01001201A driver may request a certain control state to be activated, usually just the
1202default state like this:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001203
Linus Walleij28a8d142012-02-09 01:52:22 +01001204#include <linux/pinctrl/consumer.h>
Linus Walleij2744e8a2011-05-02 20:50:54 +02001205
1206struct foo_state {
Linus Walleije93bcee2012-02-09 07:23:28 +01001207 struct pinctrl *p;
Stephen Warren6e5e9592012-03-02 13:05:47 -07001208 struct pinctrl_state *s;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001209 ...
1210};
1211
1212foo_probe()
1213{
Stephen Warren6e5e9592012-03-02 13:05:47 -07001214 /* Allocate a state holder named "foo" etc */
1215 struct foo_state *foo = ...;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001216
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001217 foo->p = devm_pinctrl_get(&device);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001218 if (IS_ERR(foo->p)) {
1219 /* FIXME: clean up "foo" here */
1220 return PTR_ERR(foo->p);
1221 }
Linus Walleij2744e8a2011-05-02 20:50:54 +02001222
Stephen Warren6e5e9592012-03-02 13:05:47 -07001223 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1224 if (IS_ERR(foo->s)) {
Stephen Warren6e5e9592012-03-02 13:05:47 -07001225 /* FIXME: clean up "foo" here */
1226 return PTR_ERR(s);
1227 }
1228
1229 ret = pinctrl_select_state(foo->s);
1230 if (ret < 0) {
Stephen Warren6e5e9592012-03-02 13:05:47 -07001231 /* FIXME: clean up "foo" here */
1232 return ret;
1233 }
Linus Walleij2744e8a2011-05-02 20:50:54 +02001234}
1235
Stephen Warren6e5e9592012-03-02 13:05:47 -07001236This get/lookup/select/put sequence can just as well be handled by bus drivers
Linus Walleij2744e8a2011-05-02 20:50:54 +02001237if you don't want each and every driver to handle it and you know the
1238arrangement on your bus.
1239
Stephen Warren6e5e9592012-03-02 13:05:47 -07001240The semantics of the pinctrl APIs are:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001241
Stephen Warren6e5e9592012-03-02 13:05:47 -07001242- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1243 information for a given client device. It will allocate a struct from the
1244 kernel memory to hold the pinmux state. All mapping table parsing or similar
1245 slow operations take place within this API.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001246
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001247- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1248 to be called automatically on the retrieved pointer when the associated
1249 device is removed. It is recommended to use this function over plain
1250 pinctrl_get().
1251
Stephen Warren6e5e9592012-03-02 13:05:47 -07001252- pinctrl_lookup_state() is called in process context to obtain a handle to a
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +00001253 specific state for a client device. This operation may be slow, too.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001254
Stephen Warren6e5e9592012-03-02 13:05:47 -07001255- pinctrl_select_state() programs pin controller hardware according to the
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +00001256 definition of the state as given by the mapping table. In theory, this is a
Stephen Warren6e5e9592012-03-02 13:05:47 -07001257 fast-path operation, since it only involved blasting some register settings
1258 into hardware. However, note that some pin controllers may have their
1259 registers on a slow/IRQ-based bus, so client devices should not assume they
1260 can call pinctrl_select_state() from non-blocking contexts.
1261
1262- pinctrl_put() frees all information associated with a pinctrl handle.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001263
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001264- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1265 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1266 However, use of this function will be rare, due to the automatic cleanup
1267 that will occur even without calling it.
1268
1269 pinctrl_get() must be paired with a plain pinctrl_put().
1270 pinctrl_get() may not be paired with devm_pinctrl_put().
1271 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1272 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1273
Linus Walleije93bcee2012-02-09 07:23:28 +01001274Usually the pin control core handled the get/put pair and call out to the
1275device drivers bookkeeping operations, like checking available functions and
Baruch Siachb18104c2015-03-08 10:51:46 +02001276the associated pins, whereas select_state pass on to the pin controller
Linus Walleij2744e8a2011-05-02 20:50:54 +02001277driver which takes care of activating and/or deactivating the mux setting by
1278quickly poking some registers.
1279
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001280The pins are allocated for your device when you issue the devm_pinctrl_get()
1281call, after this you should be able to see this in the debugfs listing of all
1282pins.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001283
Linus Walleijc05127c2012-04-10 10:00:38 +02001284NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1285requested pinctrl handles, for example if the pinctrl driver has not yet
1286registered. Thus make sure that the error path in your driver gracefully
1287cleans up and is ready to retry the probing later in the startup process.
1288
Linus Walleij2744e8a2011-05-02 20:50:54 +02001289
Linus Walleijc31a00c2012-09-10 17:22:00 +02001290Drivers needing both pin control and GPIOs
1291==========================================
1292
1293Again, it is discouraged to let drivers lookup and select pin control states
1294themselves, but again sometimes this is unavoidable.
1295
1296So say that your driver is fetching its resources like this:
1297
1298#include <linux/pinctrl/consumer.h>
1299#include <linux/gpio.h>
1300
1301struct pinctrl *pinctrl;
1302int gpio;
1303
1304pinctrl = devm_pinctrl_get_select_default(&dev);
1305gpio = devm_gpio_request(&dev, 14, "foo");
1306
1307Here we first request a certain pin state and then request GPIO 14 to be
1308used. If you're using the subsystems orthogonally like this, you should
1309nominally always get your pinctrl handle and select the desired pinctrl
1310state BEFORE requesting the GPIO. This is a semantic convention to avoid
1311situations that can be electrically unpleasant, you will certainly want to
1312mux in and bias pins in a certain way before the GPIO subsystems starts to
1313deal with them.
1314
Linus Walleijab780292013-01-22 10:56:14 -07001315The above can be hidden: using the device core, the pinctrl core may be
1316setting up the config and muxing for the pins right before the device is
1317probing, nevertheless orthogonal to the GPIO subsystem.
Linus Walleijc31a00c2012-09-10 17:22:00 +02001318
1319But there are also situations where it makes sense for the GPIO subsystem
James Hogan7bbc87b2013-05-28 10:31:48 +01001320to communicate directly with the pinctrl subsystem, using the latter as a
1321back-end. This is when the GPIO driver may call out to the functions
Linus Walleijc31a00c2012-09-10 17:22:00 +02001322described in the section "Pin control interaction with the GPIO subsystem"
1323above. This only involves per-pin multiplexing, and will be completely
1324hidden behind the gpio_*() function namespace. In this case, the driver
1325need not interact with the pin control subsystem at all.
1326
1327If a pin control driver and a GPIO driver is dealing with the same pins
1328and the use cases involve multiplexing, you MUST implement the pin controller
1329as a back-end for the GPIO driver like this, unless your hardware design
1330is such that the GPIO controller can override the pin controller's
1331multiplexing state through hardware without the need to interact with the
1332pin control system.
1333
1334
Linus Walleije93bcee2012-02-09 07:23:28 +01001335System pin control hogging
1336==========================
Linus Walleij2744e8a2011-05-02 20:50:54 +02001337
Stephen Warren1681f5a2012-02-22 14:25:58 -07001338Pin control map entries can be hogged by the core when the pin controller
Stephen Warren6e5e9592012-03-02 13:05:47 -07001339is registered. This means that the core will attempt to call pinctrl_get(),
1340lookup_state() and select_state() on it immediately after the pin control
1341device has been registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001342
Stephen Warren6e5e9592012-03-02 13:05:47 -07001343This occurs for mapping table entries where the client device name is equal
1344to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001345
1346{
Stephen Warren806d3142012-02-23 17:04:39 -07001347 .dev_name = "pinctrl-foo",
Stephen Warren46919ae2012-03-01 18:48:32 -07001348 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001349 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001350 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001351 .function = "power_func",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001352},
1353
1354Since it may be common to request the core to hog a few always-applicable
1355mux settings on the primary pin controller, there is a convenience macro for
1356this:
1357
Stephen Warren1e2082b2012-03-02 13:05:48 -07001358PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
Linus Walleij2744e8a2011-05-02 20:50:54 +02001359
1360This gives the exact same result as the above construction.
1361
1362
1363Runtime pinmuxing
1364=================
1365
1366It is possible to mux a certain function in and out at runtime, say to move
1367an SPI port from one set of pins to another set of pins. Say for example for
1368spi0 in the example above, we expose two different groups of pins for the same
1369function, but with different named in the mapping as described under
Stephen Warren6e5e9592012-03-02 13:05:47 -07001370"Advanced mapping" above. So that for an SPI device, we have two states named
1371"pos-A" and "pos-B".
Linus Walleij2744e8a2011-05-02 20:50:54 +02001372
Baruch Siachb18104c2015-03-08 10:51:46 +02001373This snippet first initializes a state object for both groups (in foo_probe()),
1374then muxes the function in the pins defined by group A, and finally muxes it in
1375on the pins defined by group B:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001376
Linus Walleij28a8d142012-02-09 01:52:22 +01001377#include <linux/pinctrl/consumer.h>
1378
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001379struct pinctrl *p;
1380struct pinctrl_state *s1, *s2;
Stephen Warren6e5e9592012-03-02 13:05:47 -07001381
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001382foo_probe()
1383{
Stephen Warren6e5e9592012-03-02 13:05:47 -07001384 /* Setup */
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001385 p = devm_pinctrl_get(&device);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001386 if (IS_ERR(p))
1387 ...
1388
1389 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1390 if (IS_ERR(s1))
1391 ...
1392
1393 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1394 if (IS_ERR(s2))
1395 ...
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001396}
Linus Walleij2744e8a2011-05-02 20:50:54 +02001397
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001398foo_switch()
1399{
Linus Walleij2744e8a2011-05-02 20:50:54 +02001400 /* Enable on position A */
Stephen Warren6e5e9592012-03-02 13:05:47 -07001401 ret = pinctrl_select_state(s1);
1402 if (ret < 0)
1403 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001404
Stephen Warren6e5e9592012-03-02 13:05:47 -07001405 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001406
1407 /* Enable on position B */
Stephen Warren6e5e9592012-03-02 13:05:47 -07001408 ret = pinctrl_select_state(s2);
1409 if (ret < 0)
1410 ...
1411
Linus Walleij2744e8a2011-05-02 20:50:54 +02001412 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001413}
1414
Linus Walleij1a789582012-10-17 20:51:54 +02001415The above has to be done from process context. The reservation of the pins
1416will be done when the state is activated, so in effect one specific pin
1417can be used by different functions at different times on a running system.