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Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +01001/*
2 * drivers/usb/musb/ux500_dma.c
3 *
Fabio Baltieri3ee1f2e2013-04-03 10:45:02 +02004 * U8500 DMA support code
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +01005 *
6 * Copyright (C) 2009 STMicroelectronics
7 * Copyright (C) 2011 ST-Ericsson SA
8 * Authors:
9 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
10 * Praveena Nadahally <praveen.nadahally@stericsson.com>
11 * Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
12 *
13 * This program is free software: you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation, either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 */
26
27#include <linux/device.h>
28#include <linux/interrupt.h>
29#include <linux/platform_device.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
32#include <linux/pfn.h>
Felipe Balbi0f53e482013-02-06 09:47:58 +020033#include <linux/sizes.h>
Arnd Bergmanndb298da2012-08-24 15:19:33 +020034#include <linux/platform_data/usb-musb-ux500.h>
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010035#include "musb_core.h"
36
Lee Jones2968da02013-05-15 10:51:47 +010037static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
38 "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
39static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
40 "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
41
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010042struct ux500_dma_channel {
43 struct dma_channel channel;
44 struct ux500_dma_controller *controller;
45 struct musb_hw_ep *hw_ep;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010046 struct dma_chan *dma_chan;
47 unsigned int cur_len;
48 dma_cookie_t cookie;
49 u8 ch_num;
50 u8 is_tx;
51 u8 is_allocated;
52};
53
54struct ux500_dma_controller {
55 struct dma_controller controller;
Lee Jonesbe2dbb02013-05-15 10:51:43 +010056 struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
57 struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010058 void *private_data;
59 dma_addr_t phy_base;
60};
61
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010062/* Work function invoked from DMA callback to handle rx transfers. */
Felipe Balbi6b0cfc62013-03-22 17:03:32 +020063static void ux500_dma_callback(void *private_data)
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010064{
Per Forlinbe18a252011-08-17 11:03:40 +020065 struct dma_channel *channel = private_data;
66 struct ux500_dma_channel *ux500_channel = channel->private_data;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010067 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
68 struct musb *musb = hw_ep->musb;
69 unsigned long flags;
70
Per Forlinafbd0742011-08-03 14:22:17 +020071 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
72 hw_ep->epnum);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010073
74 spin_lock_irqsave(&musb->lock, flags);
75 ux500_channel->channel.actual_len = ux500_channel->cur_len;
76 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
Fabio Baltieri3147dad2013-05-15 14:03:25 +020077 musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010078 spin_unlock_irqrestore(&musb->lock, flags);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010079
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010080}
81
82static bool ux500_configure_channel(struct dma_channel *channel,
83 u16 packet_sz, u8 mode,
84 dma_addr_t dma_addr, u32 len)
85{
86 struct ux500_dma_channel *ux500_channel = channel->private_data;
87 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
88 struct dma_chan *dma_chan = ux500_channel->dma_chan;
89 struct dma_async_tx_descriptor *dma_desc;
Vinod Koul83415442011-10-14 21:50:31 +053090 enum dma_transfer_direction direction;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010091 struct scatterlist sg;
92 struct dma_slave_config slave_conf;
93 enum dma_slave_buswidth addr_width;
Per Forlinafbd0742011-08-03 14:22:17 +020094 struct musb *musb = ux500_channel->controller->private_data;
Tony Lindgren1b40fc52014-11-24 11:05:02 -080095 dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
96 ux500_channel->controller->phy_base);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +010097
Per Forlinafbd0742011-08-03 14:22:17 +020098 dev_dbg(musb->controller,
Hans Wennborg50f9f792014-08-05 21:43:55 -070099 "packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
Felipe Balbi6a3b0032013-02-06 09:53:01 +0200100 packet_sz, mode, (unsigned long long) dma_addr,
101 len, ux500_channel->is_tx);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100102
103 ux500_channel->cur_len = len;
104
105 sg_init_table(&sg, 1);
106 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
107 offset_in_page(dma_addr));
108 sg_dma_address(&sg) = dma_addr;
109 sg_dma_len(&sg) = len;
110
Vinod Koul83415442011-10-14 21:50:31 +0530111 direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100112 addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
113 DMA_SLAVE_BUSWIDTH_4_BYTES;
114
115 slave_conf.direction = direction;
Per Forlind366d39b2011-08-02 17:33:39 +0200116 slave_conf.src_addr = usb_fifo_addr;
117 slave_conf.src_addr_width = addr_width;
118 slave_conf.src_maxburst = 16;
119 slave_conf.dst_addr = usb_fifo_addr;
120 slave_conf.dst_addr_width = addr_width;
121 slave_conf.dst_maxburst = 16;
Viresh Kumar258aea72012-02-01 16:12:19 +0530122 slave_conf.device_fc = false;
Per Forlind366d39b2011-08-02 17:33:39 +0200123
Vinod Koul3da67022014-10-11 21:10:38 +0530124 dmaengine_slave_config(dma_chan, &slave_conf);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100125
Alexandre Bounine16052822012-03-08 16:11:18 -0500126 dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100127 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
128 if (!dma_desc)
129 return false;
130
131 dma_desc->callback = ux500_dma_callback;
132 dma_desc->callback_param = channel;
133 ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
134
135 dma_async_issue_pending(dma_chan);
136
137 return true;
138}
139
140static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
141 struct musb_hw_ep *hw_ep, u8 is_tx)
142{
143 struct ux500_dma_controller *controller = container_of(c,
144 struct ux500_dma_controller, controller);
145 struct ux500_dma_channel *ux500_channel = NULL;
Per Forlinafbd0742011-08-03 14:22:17 +0200146 struct musb *musb = controller->private_data;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100147 u8 ch_num = hw_ep->epnum - 1;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100148
Lee Jonesbe2dbb02013-05-15 10:51:43 +0100149 /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100150 * to specified hw_ep. For example DMA channel 0 can only be allocated
151 * to hw_ep 1 and 9.
152 */
153 if (ch_num > 7)
154 ch_num -= 8;
155
Lee Jonesbe2dbb02013-05-15 10:51:43 +0100156 if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100157 return NULL;
158
159 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
160 &(controller->rx_channel[ch_num]) ;
161
162 /* Check if channel is already used. */
163 if (ux500_channel->is_allocated)
164 return NULL;
165
166 ux500_channel->hw_ep = hw_ep;
167 ux500_channel->is_allocated = 1;
168
Per Forlinafbd0742011-08-03 14:22:17 +0200169 dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100170 hw_ep->epnum, is_tx, ch_num);
171
172 return &(ux500_channel->channel);
173}
174
175static void ux500_dma_channel_release(struct dma_channel *channel)
176{
177 struct ux500_dma_channel *ux500_channel = channel->private_data;
Per Forlinafbd0742011-08-03 14:22:17 +0200178 struct musb *musb = ux500_channel->controller->private_data;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100179
Per Forlinafbd0742011-08-03 14:22:17 +0200180 dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100181
182 if (ux500_channel->is_allocated) {
183 ux500_channel->is_allocated = 0;
184 channel->status = MUSB_DMA_STATUS_FREE;
185 channel->actual_len = 0;
186 }
187}
188
189static int ux500_dma_is_compatible(struct dma_channel *channel,
190 u16 maxpacket, void *buf, u32 length)
191{
192 if ((maxpacket & 0x3) ||
Felipe Balbi6a3b0032013-02-06 09:53:01 +0200193 ((unsigned long int) buf & 0x3) ||
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100194 (length < 512) ||
195 (length & 0x3))
196 return false;
197 else
198 return true;
199}
200
201static int ux500_dma_channel_program(struct dma_channel *channel,
202 u16 packet_sz, u8 mode,
203 dma_addr_t dma_addr, u32 len)
204{
205 int ret;
206
207 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
208 channel->status == MUSB_DMA_STATUS_BUSY);
209
210 if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
211 return false;
212
213 channel->status = MUSB_DMA_STATUS_BUSY;
214 channel->actual_len = 0;
215 ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
216 if (!ret)
217 channel->status = MUSB_DMA_STATUS_FREE;
218
219 return ret;
220}
221
222static int ux500_dma_channel_abort(struct dma_channel *channel)
223{
224 struct ux500_dma_channel *ux500_channel = channel->private_data;
225 struct ux500_dma_controller *controller = ux500_channel->controller;
226 struct musb *musb = controller->private_data;
227 void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
228 u16 csr;
229
Per Forlinafbd0742011-08-03 14:22:17 +0200230 dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
231 ux500_channel->ch_num, ux500_channel->is_tx);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100232
233 if (channel->status == MUSB_DMA_STATUS_BUSY) {
234 if (ux500_channel->is_tx) {
235 csr = musb_readw(epio, MUSB_TXCSR);
236 csr &= ~(MUSB_TXCSR_AUTOSET |
237 MUSB_TXCSR_DMAENAB |
238 MUSB_TXCSR_DMAMODE);
239 musb_writew(epio, MUSB_TXCSR, csr);
240 } else {
241 csr = musb_readw(epio, MUSB_RXCSR);
242 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
243 MUSB_RXCSR_DMAENAB |
244 MUSB_RXCSR_DMAMODE);
245 musb_writew(epio, MUSB_RXCSR, csr);
246 }
247
Vinod Koul3da67022014-10-11 21:10:38 +0530248 dmaengine_terminate_all(ux500_channel->dma_chan);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100249 channel->status = MUSB_DMA_STATUS_FREE;
250 }
251 return 0;
252}
253
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200254static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100255{
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100256 struct ux500_dma_channel *ux500_channel;
257 struct dma_channel *channel;
258 u8 ch_num;
259
Lee Jonesbe2dbb02013-05-15 10:51:43 +0100260 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100261 channel = &controller->rx_channel[ch_num].channel;
262 ux500_channel = channel->private_data;
263
264 ux500_dma_channel_release(channel);
265
266 if (ux500_channel->dma_chan)
267 dma_release_channel(ux500_channel->dma_chan);
268 }
269
Lee Jonesbe2dbb02013-05-15 10:51:43 +0100270 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100271 channel = &controller->tx_channel[ch_num].channel;
272 ux500_channel = channel->private_data;
273
274 ux500_dma_channel_release(channel);
275
276 if (ux500_channel->dma_chan)
277 dma_release_channel(ux500_channel->dma_chan);
278 }
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100279}
280
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200281static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100282{
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100283 struct ux500_dma_channel *ux500_channel = NULL;
284 struct musb *musb = controller->private_data;
285 struct device *dev = musb->controller;
Jingoo Hanc1a7d672013-07-30 17:03:12 +0900286 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
Lee Jones5f6091a2013-05-15 10:51:46 +0100287 struct ux500_musb_board_data *data;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100288 struct dma_channel *dma_channel = NULL;
Lee Jones2968da02013-05-15 10:51:47 +0100289 char **chan_names;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100290 u32 ch_num;
291 u8 dir;
292 u8 is_tx = 0;
293
294 void **param_array;
295 struct ux500_dma_channel *channel_array;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100296 dma_cap_mask_t mask;
297
Lee Jones5f6091a2013-05-15 10:51:46 +0100298 if (!plat) {
299 dev_err(musb->controller, "No platform data\n");
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100300 return -EINVAL;
Lee Jones5f6091a2013-05-15 10:51:46 +0100301 }
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100302
Lee Jones5f6091a2013-05-15 10:51:46 +0100303 data = plat->board_data;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100304
305 dma_cap_zero(mask);
306 dma_cap_set(DMA_SLAVE, mask);
307
308 /* Prepare the loop for RX channels */
309 channel_array = controller->rx_channel;
Lee Jones5f6091a2013-05-15 10:51:46 +0100310 param_array = data ? data->dma_rx_param_array : NULL;
Lee Jones2968da02013-05-15 10:51:47 +0100311 chan_names = (char **)iep_chan_names;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100312
313 for (dir = 0; dir < 2; dir++) {
Lee Jonesbe2dbb02013-05-15 10:51:43 +0100314 for (ch_num = 0;
315 ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
316 ch_num++) {
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100317 ux500_channel = &channel_array[ch_num];
318 ux500_channel->controller = controller;
319 ux500_channel->ch_num = ch_num;
320 ux500_channel->is_tx = is_tx;
321
322 dma_channel = &(ux500_channel->channel);
323 dma_channel->private_data = ux500_channel;
324 dma_channel->status = MUSB_DMA_STATUS_FREE;
325 dma_channel->max_len = SZ_16M;
326
Lee Jones2968da02013-05-15 10:51:47 +0100327 ux500_channel->dma_chan =
328 dma_request_slave_channel(dev, chan_names[ch_num]);
329
330 if (!ux500_channel->dma_chan)
331 ux500_channel->dma_chan =
332 dma_request_channel(mask,
Lee Jones0f2aa8c2013-08-21 12:47:03 +0100333 data ?
334 data->dma_filter :
335 NULL,
Lee Jones086ed9a2013-12-13 10:47:28 +0000336 param_array ?
337 param_array[ch_num] :
338 NULL);
Lee Jones2968da02013-05-15 10:51:47 +0100339
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100340 if (!ux500_channel->dma_chan) {
341 ERR("Dma pipe allocation error dir=%d ch=%d\n",
342 dir, ch_num);
343
344 /* Release already allocated channels */
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200345 ux500_dma_controller_stop(controller);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100346
347 return -EBUSY;
348 }
349
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100350 }
351
352 /* Prepare the loop for TX channels */
353 channel_array = controller->tx_channel;
Lee Jones5f6091a2013-05-15 10:51:46 +0100354 param_array = data ? data->dma_tx_param_array : NULL;
Lee Jones2968da02013-05-15 10:51:47 +0100355 chan_names = (char **)oep_chan_names;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100356 is_tx = 1;
357 }
358
359 return 0;
360}
361
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700362void ux500_dma_controller_destroy(struct dma_controller *c)
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100363{
364 struct ux500_dma_controller *controller = container_of(c,
365 struct ux500_dma_controller, controller);
366
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200367 ux500_dma_controller_stop(controller);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100368 kfree(controller);
369}
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700370EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100371
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700372struct dma_controller *
373ux500_dma_controller_create(struct musb *musb, void __iomem *base)
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100374{
375 struct ux500_dma_controller *controller;
376 struct platform_device *pdev = to_platform_device(musb->controller);
377 struct resource *iomem;
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200378 int ret;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100379
380 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
381 if (!controller)
Virupax Sadashivpetimath399e0f42013-03-08 10:27:05 +0800382 goto kzalloc_fail;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100383
384 controller->private_data = musb;
385
386 /* Save physical address for DMA controller. */
387 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Virupax Sadashivpetimath399e0f42013-03-08 10:27:05 +0800388 if (!iomem) {
389 dev_err(musb->controller, "no memory resource defined\n");
390 goto plat_get_fail;
391 }
392
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100393 controller->phy_base = (dma_addr_t) iomem->start;
394
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100395 controller->controller.channel_alloc = ux500_dma_channel_allocate;
396 controller->controller.channel_release = ux500_dma_channel_release;
397 controller->controller.channel_program = ux500_dma_channel_program;
398 controller->controller.channel_abort = ux500_dma_channel_abort;
399 controller->controller.is_compatible = ux500_dma_is_compatible;
400
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200401 ret = ux500_dma_controller_start(controller);
402 if (ret)
403 goto plat_get_fail;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100404 return &controller->controller;
Virupax Sadashivpetimath399e0f42013-03-08 10:27:05 +0800405
406plat_get_fail:
407 kfree(controller);
408kzalloc_fail:
409 return NULL;
Mian Yousaf Kaukab8dcc8f72011-03-22 15:55:58 +0100410}
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700411EXPORT_SYMBOL_GPL(ux500_dma_controller_create);