Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Low-Level PCI Access for i386 machines. |
| 3 | * |
| 4 | * (c) 1999 Martin Mares <mj@ucw.cz> |
| 5 | */ |
| 6 | |
| 7 | #undef DEBUG |
| 8 | |
| 9 | #ifdef DEBUG |
| 10 | #define DBG(x...) printk(x) |
| 11 | #else |
| 12 | #define DBG(x...) |
| 13 | #endif |
| 14 | |
| 15 | #define PCI_PROBE_BIOS 0x0001 |
| 16 | #define PCI_PROBE_CONF1 0x0002 |
| 17 | #define PCI_PROBE_CONF2 0x0004 |
| 18 | #define PCI_PROBE_MMCONF 0x0008 |
Linus Torvalds | 79e453d | 2006-09-19 08:15:22 -0700 | [diff] [blame] | 19 | #define PCI_PROBE_MASK 0x000f |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 20 | #define PCI_PROBE_NOEARLY 0x0010 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #define PCI_NO_CHECKS 0x0400 |
| 23 | #define PCI_USE_PIRQ_MASK 0x0800 |
| 24 | #define PCI_ASSIGN_ROMS 0x1000 |
| 25 | #define PCI_BIOS_IRQ_SCAN 0x2000 |
| 26 | #define PCI_ASSIGN_ALL_BUSSES 0x4000 |
Gary Hade | 036fff4 | 2007-10-03 15:56:14 -0700 | [diff] [blame] | 27 | #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 |
Gary Hade | 62f420f | 2007-10-03 15:56:51 -0700 | [diff] [blame] | 28 | #define PCI_USE__CRS 0x10000 |
Yinghai Lu | 5f0b297 | 2008-04-14 16:08:25 -0700 | [diff] [blame] | 29 | #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 |
Robert Richter | 3a27dd1 | 2008-06-12 20:19:23 +0200 | [diff] [blame] | 30 | #define PCI_HAS_IO_ECS 0x40000 |
Linus Torvalds | dc7c65d | 2008-07-16 17:25:46 -0700 | [diff] [blame] | 31 | #define PCI_NOASSIGN_ROMS 0x80000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | |
| 33 | extern unsigned int pci_probe; |
jayalk@intworks.biz | 120bb42 | 2005-03-21 20:20:42 -0800 | [diff] [blame] | 34 | extern unsigned long pirq_table_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | |
Matt Domsch | 6b4b78f | 2006-09-29 15:23:23 -0500 | [diff] [blame] | 36 | enum pci_bf_sort_state { |
| 37 | pci_bf_sort_default, |
| 38 | pci_force_nobf, |
| 39 | pci_force_bf, |
| 40 | pci_dmi_bf, |
| 41 | }; |
| 42 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | /* pci-i386.c */ |
| 44 | |
| 45 | extern unsigned int pcibios_max_latency; |
| 46 | |
| 47 | void pcibios_resource_survey(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
| 49 | /* pci-pc.c */ |
| 50 | |
| 51 | extern int pcibios_last_bus; |
| 52 | extern struct pci_bus *pci_root_bus; |
| 53 | extern struct pci_ops pci_root_ops; |
| 54 | |
| 55 | /* pci-irq.c */ |
| 56 | |
| 57 | struct irq_info { |
| 58 | u8 bus, devfn; /* Bus, device and function */ |
| 59 | struct { |
| 60 | u8 link; /* IRQ line ID, chipset dependent, 0=not routed */ |
| 61 | u16 bitmap; /* Available IRQs */ |
| 62 | } __attribute__((packed)) irq[4]; |
| 63 | u8 slot; /* Slot number, 0=onboard */ |
| 64 | u8 rfu; |
| 65 | } __attribute__((packed)); |
| 66 | |
| 67 | struct irq_routing_table { |
| 68 | u32 signature; /* PIRQ_SIGNATURE should be here */ |
| 69 | u16 version; /* PIRQ_VERSION */ |
| 70 | u16 size; /* Table size in bytes */ |
| 71 | u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ |
| 72 | u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ |
| 73 | u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */ |
| 74 | u32 miniport_data; /* Crap */ |
| 75 | u8 rfu[11]; |
| 76 | u8 checksum; /* Modulo 256 checksum must give zero */ |
| 77 | struct irq_info slots[0]; |
| 78 | } __attribute__((packed)); |
| 79 | |
| 80 | extern unsigned int pcibios_irq_mask; |
| 81 | |
| 82 | extern int pcibios_scanned; |
| 83 | extern spinlock_t pci_config_lock; |
| 84 | |
| 85 | extern int (*pcibios_enable_irq)(struct pci_dev *dev); |
David Shaohua Li | 87bec66 | 2005-07-27 23:02:00 -0400 | [diff] [blame] | 86 | extern void (*pcibios_disable_irq)(struct pci_dev *dev); |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 87 | |
Matthew Wilcox | b6ce068 | 2008-02-10 09:45:28 -0500 | [diff] [blame] | 88 | struct pci_raw_ops { |
| 89 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, |
| 90 | int reg, int len, u32 *val); |
| 91 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, |
| 92 | int reg, int len, u32 val); |
| 93 | }; |
| 94 | |
| 95 | extern struct pci_raw_ops *raw_pci_ops; |
| 96 | extern struct pci_raw_ops *raw_pci_ext_ops; |
| 97 | |
| 98 | extern struct pci_raw_ops pci_direct_conf1; |
H. Peter Anvin | 14d7ca5 | 2008-11-11 16:19:48 -0800 | [diff] [blame^] | 99 | extern bool port_cf9_safe; |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 100 | |
Robert Richter | 8dd779b | 2008-07-02 22:50:29 +0200 | [diff] [blame] | 101 | /* arch_initcall level */ |
Andi Kleen | 5e544d6 | 2006-09-26 10:52:40 +0200 | [diff] [blame] | 102 | extern int pci_direct_probe(void); |
| 103 | extern void pci_direct_init(int type); |
Andi Kleen | 92c05fc | 2006-03-23 14:35:12 -0800 | [diff] [blame] | 104 | extern void pci_pcbios_init(void); |
Andres Salomon | 2bdd1b0 | 2008-06-05 14:14:41 -0700 | [diff] [blame] | 105 | extern int pci_olpc_init(void); |
Robert Richter | 8dd779b | 2008-07-02 22:50:29 +0200 | [diff] [blame] | 106 | extern void __init dmi_check_pciprobe(void); |
| 107 | extern void __init dmi_check_skip_isa_align(void); |
| 108 | |
| 109 | /* some common used subsys_initcalls */ |
| 110 | extern int __init pci_acpi_init(void); |
| 111 | extern int __init pcibios_irq_init(void); |
Robert Richter | 3cabf37 | 2008-07-11 12:26:59 +0200 | [diff] [blame] | 112 | extern int __init pci_visws_init(void); |
Robert Richter | e27cf3a | 2008-07-11 12:18:41 +0200 | [diff] [blame] | 113 | extern int __init pci_numaq_init(void); |
Robert Richter | 8dd779b | 2008-07-02 22:50:29 +0200 | [diff] [blame] | 114 | extern int __init pcibios_init(void); |
Andi Kleen | 5e544d6 | 2006-09-26 10:52:40 +0200 | [diff] [blame] | 115 | |
Olivier Galibert | b786739 | 2007-02-13 13:26:20 +0100 | [diff] [blame] | 116 | /* pci-mmconfig.c */ |
| 117 | |
OGAWA Hirofumi | 429d512 | 2007-02-13 13:26:20 +0100 | [diff] [blame] | 118 | extern int __init pci_mmcfg_arch_init(void); |
Yinghai Lu | 0b64ad7 | 2008-02-15 01:28:41 -0800 | [diff] [blame] | 119 | extern void __init pci_mmcfg_arch_free(void); |
dean gaudet | 3320ad9 | 2007-08-10 22:30:59 +0200 | [diff] [blame] | 120 | |
| 121 | /* |
| 122 | * AMD Fam10h CPUs are buggy, and cannot access MMIO config space |
| 123 | * on their northbrige except through the * %eax register. As such, you MUST |
| 124 | * NOT use normal IOMEM accesses, you need to only use the magic mmio-config |
| 125 | * accessor functions. |
| 126 | * In fact just use pci_config_*, nothing else please. |
| 127 | */ |
| 128 | static inline unsigned char mmio_config_readb(void __iomem *pos) |
| 129 | { |
| 130 | u8 val; |
| 131 | asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); |
| 132 | return val; |
| 133 | } |
| 134 | |
| 135 | static inline unsigned short mmio_config_readw(void __iomem *pos) |
| 136 | { |
| 137 | u16 val; |
| 138 | asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); |
| 139 | return val; |
| 140 | } |
| 141 | |
| 142 | static inline unsigned int mmio_config_readl(void __iomem *pos) |
| 143 | { |
| 144 | u32 val; |
| 145 | asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); |
| 146 | return val; |
| 147 | } |
| 148 | |
| 149 | static inline void mmio_config_writeb(void __iomem *pos, u8 val) |
| 150 | { |
| 151 | asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory"); |
| 152 | } |
| 153 | |
| 154 | static inline void mmio_config_writew(void __iomem *pos, u16 val) |
| 155 | { |
| 156 | asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory"); |
| 157 | } |
| 158 | |
| 159 | static inline void mmio_config_writel(void __iomem *pos, u32 val) |
| 160 | { |
| 161 | asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory"); |
| 162 | } |