blob: 70d7e3a279a052c9be7453311886d985751417b6 [file] [log] [blame]
Christian König56113502016-09-28 12:36:44 +02001/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24#ifndef __AMDGPU_SYNC_H__
25#define __AMDGPU_SYNC_H__
26
27#include <linux/hashtable.h>
28
Dave Airlie220196b2016-10-28 11:33:52 +100029struct dma_fence;
Christian König56113502016-09-28 12:36:44 +020030struct reservation_object;
31struct amdgpu_device;
32struct amdgpu_ring;
33
34/*
35 * Container for fences used to sync command submissions.
36 */
37struct amdgpu_sync {
38 DECLARE_HASHTABLE(fences, 4);
Dave Airlie220196b2016-10-28 11:33:52 +100039 struct dma_fence *last_vm_update;
Christian König56113502016-09-28 12:36:44 +020040};
41
42void amdgpu_sync_create(struct amdgpu_sync *sync);
43int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
Dave Airlie220196b2016-10-28 11:33:52 +100044 struct dma_fence *f);
Christian König56113502016-09-28 12:36:44 +020045int amdgpu_sync_resv(struct amdgpu_device *adev,
46 struct amdgpu_sync *sync,
47 struct reservation_object *resv,
Andres Rodriguez177ae092017-09-15 20:44:06 -040048 void *owner,
49 bool explicit_sync);
Dave Airlie220196b2016-10-28 11:33:52 +100050struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
Christian König56113502016-09-28 12:36:44 +020051 struct amdgpu_ring *ring);
Dave Airlie220196b2016-10-28 11:33:52 +100052struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
Harish Kasiviswanathana6583af2017-05-15 15:09:15 -040053int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
Christian König56113502016-09-28 12:36:44 +020054void amdgpu_sync_free(struct amdgpu_sync *sync);
55int amdgpu_sync_init(void);
56void amdgpu_sync_fini(void);
57
58#endif