blob: f093e3974d6a16839a612a3c9fd003619b3b6600 [file] [log] [blame]
Thomas Petazzonif3b42b72012-09-13 17:41:48 +02001/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16/include/ "armada-xp.dtsi"
17
18/ {
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
21
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020022 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 };
26
Gregory CLEMENT9d202782012-11-17 15:22:24 +010027 cpus {
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020028 #address-cells = <1>;
29 #size-cells = <0>;
Gregory CLEMENT9d202782012-11-17 15:22:24 +010030
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020031 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 };
Thomas Petazzoni44cfae92013-01-06 11:10:40 +010037
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020038 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 };
Andrew Lunn41be8dc2013-01-06 11:10:42 +010044 };
Gregory CLEMENT9d202782012-11-17 15:22:24 +010045
Thomas Petazzonif3b42b72012-09-13 17:41:48 +020046 soc {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030047 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x4/x1.
51 */
52 pcie-controller {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 bus-range = <0x00 0xff>;
61
62 ranges =
63 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
64 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
69 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
70 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
71 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
72 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
73 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
74 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
75 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
76 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
77 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
78
79 pcie@1,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
82 reg = <0x0800 0 0 0 0>;
83 #address-cells = <3>;
84 #size-cells = <2>;
85 #interrupt-cells = <1>;
86 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
87 0x81000000 0 0 0x81000000 0x1 0 1 0>;
88 interrupt-map-mask = <0 0 0 0>;
89 interrupt-map = <0 0 0 0 &mpic 58>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
93 status = "disabled";
94 };
95
96 pcie@2,0 {
97 device_type = "pci";
98 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
99 reg = <0x1000 0 0 0 0>;
100 #address-cells = <3>;
101 #size-cells = <2>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
104 0x81000000 0 0 0x81000000 0x2 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 59>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <1>;
109 clocks = <&gateclk 6>;
110 status = "disabled";
111 };
112
113 pcie@3,0 {
114 device_type = "pci";
115 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
116 reg = <0x1800 0 0 0 0>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
121 0x81000000 0 0 0x81000000 0x3 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 60>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <2>;
126 clocks = <&gateclk 7>;
127 status = "disabled";
128 };
129
130 pcie@4,0 {
131 device_type = "pci";
132 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
133 reg = <0x2000 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
138 0x81000000 0 0 0x81000000 0x4 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 61>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <3>;
143 clocks = <&gateclk 8>;
144 status = "disabled";
145 };
146
147 pcie@9,0 {
148 device_type = "pci";
149 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
150 reg = <0x4800 0 0 0 0>;
151 #address-cells = <3>;
152 #size-cells = <2>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
155 0x81000000 0 0 0x81000000 0x9 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 99>;
158 marvell,pcie-port = <2>;
159 marvell,pcie-lane = <0>;
160 clocks = <&gateclk 26>;
161 status = "disabled";
162 };
163 };
164
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200165 internal-regs {
166 pinctrl {
167 compatible = "marvell,mv78230-pinctrl";
168 reg = <0x18000 0x38>;
Thomas Petazzoni6d36e8e2012-12-21 15:49:06 +0100169
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200170 sdio_pins: sdio-pins {
171 marvell,pins = "mpp30", "mpp31", "mpp32",
172 "mpp33", "mpp34", "mpp35";
173 marvell,function = "sd0";
174 };
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200175 };
176
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200177 gpio0: gpio@18100 {
178 compatible = "marvell,orion-gpio";
179 reg = <0x18100 0x40>;
180 ngpios = <32>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupts-cells = <2>;
185 interrupts = <82>, <83>, <84>, <85>;
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200186 };
187
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200188 gpio1: gpio@18140 {
189 compatible = "marvell,orion-gpio";
190 reg = <0x18140 0x40>;
191 ngpios = <17>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
195 #interrupts-cells = <2>;
196 interrupts = <87>, <88>, <89>;
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200197 };
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200198 };
Thomas Petazzonif3b42b72012-09-13 17:41:48 +0200199 };
200};