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Mike Frysingerb03f2032009-01-07 23:14:38 +08001/* mach/dma.h - arch-specific DMA defines
Michael Hennerich59003142007-10-21 16:54:27 +08002 *
Mike Frysingerb03f2032009-01-07 23:14:38 +08003 * Copyright 2004-2008 Analog Devices Inc.
Michael Hennerich59003142007-10-21 16:54:27 +08004 *
Mike Frysingerb03f2032009-01-07 23:14:38 +08005 * Licensed under the GPL-2 or later.
Michael Hennerich59003142007-10-21 16:54:27 +08006 */
7
8#ifndef _MACH_DMA_H_
9#define _MACH_DMA_H_
10
Mike Frysinger211daf92009-01-07 23:14:39 +080011#define MAX_DMA_CHANNELS 16
Michael Hennerich59003142007-10-21 16:54:27 +080012
13#define CH_PPI 0 /* PPI receive/transmit or NFC */
Michael Hennerich59003142007-10-21 16:54:27 +080014#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
15#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
16#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
17#define CH_SPORT0_RX 3 /* SPORT0 receive */
18#define CH_SPORT0_TX 4 /* SPORT0 transmit */
19#define CH_SPORT1_RX 5 /* SPORT1 receive */
20#define CH_SPORT1_TX 6 /* SPORT1 transmit */
21#define CH_SPI 7 /* SPI transmit/receive */
22#define CH_UART0_RX 8 /* UART0 receive */
23#define CH_UART0_TX 9 /* UART0 transmit */
24#define CH_UART1_RX 10 /* UART1 receive */
25#define CH_UART1_TX 11 /* UART1 transmit */
26
27#define CH_MEM_STREAM0_DEST 12 /* TX */
28#define CH_MEM_STREAM0_SRC 13 /* RX */
29#define CH_MEM_STREAM1_DEST 14 /* TX */
30#define CH_MEM_STREAM1_SRC 15 /* RX */
31
Michael Hennerich64307f72007-10-29 16:55:18 +080032#if defined(CONFIG_BF527_NAND_D_PORTF)
33#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
34#elif defined(CONFIG_BF527_NAND_D_PORTH)
35#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
36#endif
37
Michael Hennerich59003142007-10-21 16:54:27 +080038#endif