Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/irq.c |
| 3 | * |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 4 | * Generic PXA IRQ handling |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 |
| 8 | * Copyright: MontaVista Software Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 17 | #include <linux/syscore_ops.h> |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 18 | #include <linux/io.h> |
| 19 | #include <linux/irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Jamie Iles | 5a567d7 | 2011-10-08 11:20:42 +0100 | [diff] [blame] | 21 | #include <asm/exception.h> |
| 22 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | #include <mach/hardware.h> |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 24 | #include <mach/irqs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
| 26 | #include "generic.h" |
| 27 | |
Arnd Bergmann | 97b09da | 2011-10-01 22:03:45 +0200 | [diff] [blame] | 28 | #define IRQ_BASE io_p2v(0x40d00000) |
Haojian Zhuang | c482ae4 | 2009-11-02 14:02:21 -0500 | [diff] [blame] | 29 | |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 30 | #define ICIP (0x000) |
| 31 | #define ICMR (0x004) |
| 32 | #define ICLR (0x008) |
| 33 | #define ICFR (0x00c) |
| 34 | #define ICPR (0x010) |
| 35 | #define ICCR (0x014) |
| 36 | #define ICHP (0x018) |
| 37 | #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ |
| 38 | ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ |
| 39 | (0x144 + (((i) - 64) << 2))) |
Eric Miao | a551e4f | 2011-04-27 22:48:05 +0800 | [diff] [blame] | 40 | #define ICHP_VAL_IRQ (1 << 31) |
| 41 | #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 42 | #define IPR_VALID (1 << 31) |
| 43 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) |
| 44 | |
| 45 | #define MAX_INTERNAL_IRQS 128 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
| 47 | /* |
| 48 | * This is for peripheral IRQs internal to the PXA chip. |
| 49 | */ |
| 50 | |
eric miao | f6fb7af | 2008-03-04 13:53:05 +0800 | [diff] [blame] | 51 | static int pxa_internal_irq_nr; |
| 52 | |
Haojian Zhuang | bb71bdd | 2010-11-17 19:03:36 +0800 | [diff] [blame] | 53 | static inline int cpu_has_ipr(void) |
| 54 | { |
| 55 | return !cpu_is_pxa25x(); |
| 56 | } |
| 57 | |
Eric Miao | a1015a1 | 2011-01-12 16:42:24 -0600 | [diff] [blame] | 58 | static inline void __iomem *irq_base(int i) |
| 59 | { |
| 60 | static unsigned long phys_base[] = { |
| 61 | 0x40d00000, |
| 62 | 0x40d0009c, |
| 63 | 0x40d00130, |
| 64 | }; |
| 65 | |
Arnd Bergmann | 97b09da | 2011-10-01 22:03:45 +0200 | [diff] [blame] | 66 | return io_p2v(phys_base[i]); |
Eric Miao | a1015a1 | 2011-01-12 16:42:24 -0600 | [diff] [blame] | 67 | } |
| 68 | |
Eric Miao | 5d284e3 | 2011-04-27 22:48:04 +0800 | [diff] [blame] | 69 | void pxa_mask_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | { |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 71 | void __iomem *base = irq_data_get_irq_chip_data(d); |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 72 | uint32_t icmr = __raw_readl(base + ICMR); |
| 73 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 74 | icmr &= ~(1 << IRQ_BIT(d->irq)); |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 75 | __raw_writel(icmr, base + ICMR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Eric Miao | 5d284e3 | 2011-04-27 22:48:04 +0800 | [diff] [blame] | 78 | void pxa_unmask_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | { |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 80 | void __iomem *base = irq_data_get_irq_chip_data(d); |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 81 | uint32_t icmr = __raw_readl(base + ICMR); |
| 82 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 83 | icmr |= 1 << IRQ_BIT(d->irq); |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 84 | __raw_writel(icmr, base + ICMR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | } |
| 86 | |
eric miao | f6fb7af | 2008-03-04 13:53:05 +0800 | [diff] [blame] | 87 | static struct irq_chip pxa_internal_irq_chip = { |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 88 | .name = "SC", |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 89 | .irq_ack = pxa_mask_irq, |
| 90 | .irq_mask = pxa_mask_irq, |
| 91 | .irq_unmask = pxa_unmask_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | }; |
| 93 | |
Eric Miao | a551e4f | 2011-04-27 22:48:05 +0800 | [diff] [blame] | 94 | asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) |
| 95 | { |
| 96 | uint32_t icip, icmr, mask; |
| 97 | |
| 98 | do { |
| 99 | icip = __raw_readl(IRQ_BASE + ICIP); |
| 100 | icmr = __raw_readl(IRQ_BASE + ICMR); |
| 101 | mask = icip & icmr; |
| 102 | |
| 103 | if (mask == 0) |
| 104 | break; |
| 105 | |
| 106 | handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); |
| 107 | } while (1); |
| 108 | } |
| 109 | |
| 110 | asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) |
| 111 | { |
| 112 | uint32_t ichp; |
| 113 | |
| 114 | do { |
| 115 | __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); |
| 116 | |
| 117 | if ((ichp & ICHP_VAL_IRQ) == 0) |
| 118 | break; |
| 119 | |
| 120 | handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); |
| 121 | } while (1); |
| 122 | } |
| 123 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 124 | void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) |
Eric Miao | 53665a5 | 2007-06-06 06:36:04 +0100 | [diff] [blame] | 125 | { |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 126 | int irq, i, n; |
Eric Miao | 53665a5 | 2007-06-06 06:36:04 +0100 | [diff] [blame] | 127 | |
Haojian Zhuang | c482ae4 | 2009-11-02 14:02:21 -0500 | [diff] [blame] | 128 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); |
| 129 | |
eric miao | f6fb7af | 2008-03-04 13:53:05 +0800 | [diff] [blame] | 130 | pxa_internal_irq_nr = irq_nr; |
Eric Miao | 53665a5 | 2007-06-06 06:36:04 +0100 | [diff] [blame] | 131 | |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 132 | for (n = 0; n < irq_nr; n += 32) { |
Marek Vasut | 1b624fb | 2011-01-10 23:53:12 +0100 | [diff] [blame] | 133 | void __iomem *base = irq_base(n >> 5); |
Eric Miao | 53665a5 | 2007-06-06 06:36:04 +0100 | [diff] [blame] | 134 | |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 135 | __raw_writel(0, base + ICMR); /* disable all IRQs */ |
| 136 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ |
| 137 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { |
| 138 | /* initialize interrupt priority */ |
| 139 | if (cpu_has_ipr()) |
| 140 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); |
| 141 | |
| 142 | irq = PXA_IRQ(i); |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 143 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, |
| 144 | handle_level_irq); |
Thomas Gleixner | 9323f261 | 2011-03-24 13:29:39 +0100 | [diff] [blame] | 145 | irq_set_chip_data(irq, base); |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 146 | set_irq_flags(irq, IRQF_VALID); |
| 147 | } |
Haojian Zhuang | d2c3706 | 2009-08-19 19:49:31 +0800 | [diff] [blame] | 148 | } |
| 149 | |
Eric Miao | 53665a5 | 2007-06-06 06:36:04 +0100 | [diff] [blame] | 150 | /* only unmasked interrupts kick us out of idle */ |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 151 | __raw_writel(1, irq_base(0) + ICCR); |
Eric Miao | 53665a5 | 2007-06-06 06:36:04 +0100 | [diff] [blame] | 152 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 153 | pxa_internal_irq_chip.irq_set_wake = fn; |
eric miao | c95530c | 2007-08-29 10:22:17 +0100 | [diff] [blame] | 154 | } |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 155 | |
| 156 | #ifdef CONFIG_PM |
Haojian Zhuang | c482ae4 | 2009-11-02 14:02:21 -0500 | [diff] [blame] | 157 | static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; |
| 158 | static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 159 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 160 | static int pxa_irq_suspend(void) |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 161 | { |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 162 | int i; |
eric miao | f6fb7af | 2008-03-04 13:53:05 +0800 | [diff] [blame] | 163 | |
Marek Vasut | 1b624fb | 2011-01-10 23:53:12 +0100 | [diff] [blame] | 164 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 165 | void __iomem *base = irq_base(i); |
| 166 | |
| 167 | saved_icmr[i] = __raw_readl(base + ICMR); |
| 168 | __raw_writel(0, base + ICMR); |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 169 | } |
Eric Miao | c70f5a6 | 2010-01-11 20:39:37 +0800 | [diff] [blame] | 170 | |
Haojian Zhuang | bb71bdd | 2010-11-17 19:03:36 +0800 | [diff] [blame] | 171 | if (cpu_has_ipr()) { |
Eric Miao | c70f5a6 | 2010-01-11 20:39:37 +0800 | [diff] [blame] | 172 | for (i = 0; i < pxa_internal_irq_nr; i++) |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 173 | saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); |
Eric Miao | c70f5a6 | 2010-01-11 20:39:37 +0800 | [diff] [blame] | 174 | } |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 175 | |
| 176 | return 0; |
| 177 | } |
| 178 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 179 | static void pxa_irq_resume(void) |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 180 | { |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 181 | int i; |
eric miao | f6fb7af | 2008-03-04 13:53:05 +0800 | [diff] [blame] | 182 | |
Marek Vasut | 1b624fb | 2011-01-10 23:53:12 +0100 | [diff] [blame] | 183 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 184 | void __iomem *base = irq_base(i); |
| 185 | |
| 186 | __raw_writel(saved_icmr[i], base + ICMR); |
| 187 | __raw_writel(0, base + ICLR); |
| 188 | } |
| 189 | |
Marek Vasut | 57879b8 | 2011-01-10 00:29:04 +0100 | [diff] [blame] | 190 | if (cpu_has_ipr()) |
Eric Miao | c70f5a6 | 2010-01-11 20:39:37 +0800 | [diff] [blame] | 191 | for (i = 0; i < pxa_internal_irq_nr; i++) |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 192 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); |
Eric Miao | c70f5a6 | 2010-01-11 20:39:37 +0800 | [diff] [blame] | 193 | |
Haojian Zhuang | a79a9ad | 2010-11-24 11:54:22 +0800 | [diff] [blame] | 194 | __raw_writel(1, IRQ_BASE + ICCR); |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 195 | } |
| 196 | #else |
| 197 | #define pxa_irq_suspend NULL |
| 198 | #define pxa_irq_resume NULL |
| 199 | #endif |
| 200 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 201 | struct syscore_ops pxa_irq_syscore_ops = { |
eric miao | c0165504 | 2008-01-28 23:00:02 +0000 | [diff] [blame] | 202 | .suspend = pxa_irq_suspend, |
| 203 | .resume = pxa_irq_resume, |
| 204 | }; |