| Haavard Skinnemoen | 18f65c7 | 2007-09-02 23:15:49 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel |
| 3 | * |
| 4 | * Copyright (C) 2006, 2007 Atmel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #ifndef __LTV350QV_H |
| 11 | #define __LTV350QV_H |
| 12 | |
| 13 | #define LTV_OPC_INDEX 0x74 |
| 14 | #define LTV_OPC_DATA 0x76 |
| 15 | |
| 16 | #define LTV_ID 0x00 /* ID Read */ |
| 17 | #define LTV_IFCTL 0x01 /* Display Interface Control */ |
| 18 | #define LTV_DATACTL 0x02 /* Display Data Control */ |
| 19 | #define LTV_ENTRY_MODE 0x03 /* Entry Mode */ |
| 20 | #define LTV_GATECTL1 0x04 /* Gate Control 1 */ |
| 21 | #define LTV_GATECTL2 0x05 /* Gate Control 2 */ |
| 22 | #define LTV_VBP 0x06 /* Vertical Back Porch */ |
| 23 | #define LTV_HBP 0x07 /* Horizontal Back Porch */ |
| 24 | #define LTV_SOTCTL 0x08 /* Source Output Timing Control */ |
| 25 | #define LTV_PWRCTL1 0x09 /* Power Control 1 */ |
| 26 | #define LTV_PWRCTL2 0x0a /* Power Control 2 */ |
| 27 | #define LTV_GAMMA(x) (0x10 + (x)) /* Gamma control */ |
| 28 | |
| 29 | /* Bit definitions for LTV_IFCTL */ |
| 30 | #define LTV_IM (1 << 15) |
| 31 | #define LTV_NMD (1 << 14) |
| 32 | #define LTV_SSMD (1 << 13) |
| 33 | #define LTV_REV (1 << 7) |
| 34 | #define LTV_NL(x) (((x) & 0x001f) << 0) |
| 35 | |
| 36 | /* Bit definitions for LTV_DATACTL */ |
| 37 | #define LTV_DS_SAME (0 << 12) |
| 38 | #define LTV_DS_D_TO_S (1 << 12) |
| 39 | #define LTV_DS_S_TO_D (2 << 12) |
| 40 | #define LTV_CHS_384 (0 << 9) |
| 41 | #define LTV_CHS_480 (1 << 9) |
| 42 | #define LTV_CHS_492 (2 << 9) |
| 43 | #define LTV_DF_RGB (0 << 6) |
| 44 | #define LTV_DF_RGBX (1 << 6) |
| 45 | #define LTV_DF_XRGB (2 << 6) |
| 46 | #define LTV_RGB_RGB (0 << 2) |
| 47 | #define LTV_RGB_BGR (1 << 2) |
| 48 | #define LTV_RGB_GRB (2 << 2) |
| 49 | #define LTV_RGB_RBG (3 << 2) |
| 50 | |
| 51 | /* Bit definitions for LTV_ENTRY_MODE */ |
| 52 | #define LTV_VSPL_ACTIVE_LOW (0 << 15) |
| 53 | #define LTV_VSPL_ACTIVE_HIGH (1 << 15) |
| 54 | #define LTV_HSPL_ACTIVE_LOW (0 << 14) |
| 55 | #define LTV_HSPL_ACTIVE_HIGH (1 << 14) |
| 56 | #define LTV_DPL_SAMPLE_RISING (0 << 13) |
| 57 | #define LTV_DPL_SAMPLE_FALLING (1 << 13) |
| 58 | #define LTV_EPL_ACTIVE_LOW (0 << 12) |
| 59 | #define LTV_EPL_ACTIVE_HIGH (1 << 12) |
| 60 | #define LTV_SS_LEFT_TO_RIGHT (0 << 8) |
| 61 | #define LTV_SS_RIGHT_TO_LEFT (1 << 8) |
| 62 | #define LTV_STB (1 << 1) |
| 63 | |
| 64 | /* Bit definitions for LTV_GATECTL1 */ |
| 65 | #define LTV_CLW(x) (((x) & 0x0007) << 12) |
| 66 | #define LTV_GAON (1 << 5) |
| 67 | #define LTV_SDR (1 << 3) |
| 68 | |
| 69 | /* Bit definitions for LTV_GATECTL2 */ |
| 70 | #define LTV_NW_INV_FRAME (0 << 14) |
| 71 | #define LTV_NW_INV_1LINE (1 << 14) |
| 72 | #define LTV_NW_INV_2LINE (2 << 14) |
| 73 | #define LTV_DSC (1 << 12) |
| 74 | #define LTV_GIF (1 << 8) |
| 75 | #define LTV_FHN (1 << 7) |
| 76 | #define LTV_FTI(x) (((x) & 0x0003) << 4) |
| 77 | #define LTV_FWI(x) (((x) & 0x0003) << 0) |
| 78 | |
| 79 | /* Bit definitions for LTV_SOTCTL */ |
| 80 | #define LTV_SDT(x) (((x) & 0x0007) << 10) |
| 81 | #define LTV_EQ(x) (((x) & 0x0007) << 2) |
| 82 | |
| 83 | /* Bit definitions for LTV_PWRCTL1 */ |
| 84 | #define LTV_VCOM_DISABLE (1 << 14) |
| 85 | #define LTV_VCOMOUT_ENABLE (1 << 11) |
| 86 | #define LTV_POWER_ON (1 << 9) |
| 87 | #define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */ |
| 88 | #define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */ |
| 89 | |
| 90 | /* Bit definitions for LTV_PWRCTL2 */ |
| 91 | #define LTV_VCOML_ENABLE (1 << 13) |
| 92 | #define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */ |
| 93 | #define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */ |
| 94 | |
| 95 | #endif /* __LTV350QV_H */ |