Blame - include/asm-blackfin/mach-bf548/defBF548.h - kernel/msm-4.19

Bryan Wu

19381f0

2007-05-21 18:09:31 +0800

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/*

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* File: include/asm-blackfin/mach-bf548/defBF548.h

* Based on:

* Author:

*

* Created:

* Description:

*

* Rev:

*

* Modified:

*

* Bugs: Enter bugs at http://blackfin.uclinux.org/

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*

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2, or (at your option)

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* any later version.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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*

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* You should have received a copy of the GNU General Public License

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* along with this program; see the file COPYING.

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* If not, write to the Free Software Foundation,

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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef _DEF_BF548_H

#define _DEF_BF548_H

/* Include all Core registers and bit definitions */

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#include <asm/mach-common/def_LPBlackfin.h>

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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */

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/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */

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#include "defBF54x_base.h"

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/* The following are the #defines needed by ADSP-BF548 that are not in the common header */

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/* Timer Registers */

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#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */

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#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */

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#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */

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#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */

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#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */

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#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */

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#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */

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#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */

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#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */

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#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */

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#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */

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#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */

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/* Timer Group of 3 Registers */

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#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */

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#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */

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#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */

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/* SPORT0 Registers */

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#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */

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#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */

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#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */

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#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */

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#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */

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#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */

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#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */

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#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */

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#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */

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#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */

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#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */

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#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */

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#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */

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#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */

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#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */

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#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */

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#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */

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#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */

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#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */

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#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */

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#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */

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#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */

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/* EPPI0 Registers */

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#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */

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#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */

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#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */

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#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */

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#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */

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#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */

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#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */

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#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */

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#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */

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#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */

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#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */

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#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */

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#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */

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#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */

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/* UART2 Registers */

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#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */

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#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */

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#define UART2_GCTL 0xffc02108 /* Global Control Register */

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#define UART2_LCR 0xffc0210c /* Line Control Register */

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#define UART2_MCR 0xffc02110 /* Modem Control Register */

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#define UART2_LSR 0xffc02114 /* Line Status Register */

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#define UART2_MSR 0xffc02118 /* Modem Status Register */

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#define UART2_SCR 0xffc0211c /* Scratch Register */

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#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */

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#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */

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#define UART2_RBR 0xffc0212c /* Receive Buffer Register */

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/* Two Wire Interface Registers (TWI1) */

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#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */

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#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */

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#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */

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#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */

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#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */

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#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */

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#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */

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#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */

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#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */

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#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */

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#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */

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#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */

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#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */

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#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */

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#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */

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#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */

/* SPI2 Registers */

#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */

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#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */

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#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */

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#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */

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#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */

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#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */

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#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */

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/* CAN Controller 1 Config 1 Registers */

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#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */

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#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */

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#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */

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#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */

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#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */

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#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */

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#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */

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#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */

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#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */

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#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */

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#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */

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#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */

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#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */

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/* CAN Controller 1 Config 2 Registers */

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#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */

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#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */

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#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */

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#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */

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#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */

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#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */

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#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */

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#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */

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#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */

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#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */

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#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */

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#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */

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#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */

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/* CAN Controller 1 Clock/Interrupt/Counter Registers */

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#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */

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#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */

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#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */

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#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */

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#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */

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#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */

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#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */

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#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */

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#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */

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#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */

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#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */

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#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */

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#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */

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#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */

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#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */

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#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */

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/* CAN Controller 1 Mailbox Acceptance Registers */

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#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */

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#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */

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#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */

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#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */

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#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */

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#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */

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#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */

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#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */

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#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */

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#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */

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#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */

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#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */

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#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */

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#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */

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#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */

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#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */

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#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */

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#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */

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#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */

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#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */

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#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */

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#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */

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#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */

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#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */

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#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */

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#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */

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#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */

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#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */

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#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */

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#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */

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#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */

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#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */

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/* CAN Controller 1 Mailbox Acceptance Registers */

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#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */

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#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */

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#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */

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#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */

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#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */

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#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */

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#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */

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#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */

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#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */

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#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */

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#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */

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#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */

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#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */

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#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */

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#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */

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#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */

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#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */

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#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */

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#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */

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#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */

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#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */

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#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */

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#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */

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#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */

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#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */

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#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */

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#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */

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#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */

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#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */

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#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */

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#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */

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#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */

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/* CAN Controller 1 Mailbox Data Registers */

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#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */

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#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */

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#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */

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#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */

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#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */

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#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */

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#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */

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#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */

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#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */

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#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */

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#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */

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#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */

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#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */

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#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */

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#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */

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#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */

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#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */

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#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */

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#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */

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#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */

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#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */

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#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */

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#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */

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#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */

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#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */

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#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */

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#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */

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#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */

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#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */

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#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */

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#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */

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#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */

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#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */

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#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */

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#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */

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#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */

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#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */

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#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */

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#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */

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#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */

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#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */

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#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */

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#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */

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#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */

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#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */

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#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */

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#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */

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#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */

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#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */

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#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */

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#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */

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#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */

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#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */

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#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */

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#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */

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#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */

329

#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */

330

#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */

331

#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */

332

#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */

333

#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */

334

#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */

335

#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */

336

#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */

337

#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */

338

#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */

339

#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */

340

#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */

341

#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */

342

#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */

343

#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */

344

#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */

345

#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */

346

#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */

347

#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */

348

#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */

349

#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */

350

#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */

351

#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */

352

#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */

353

#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */

354

#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */

355

#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */

356

#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */

357

#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */

358

#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */

359

#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */

360

#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */

361

#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */

362

#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */

363

#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */

364

#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */

365

#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */

366

#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */

367

#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */

368

#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */

369

#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */

370

#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */

371

#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */

372

#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */

373

#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */

374

#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */

375

#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */

376

#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */

377

#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */

378

#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */

379

#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */

380

#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */

381

#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */

382

#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */

383

#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */

384

#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */

385

#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */

386

#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */

387

#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */

388

#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */

389

#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */

390

#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */

391

#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */

392

#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */

393

#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */

394

#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */

395

#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */

396

#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */

397

#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */

398

#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */

399

#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */

400

#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */

401

402

/* CAN Controller 1 Mailbox Data Registers */

403

404

#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */

405

#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */

406

#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */

407

#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */

408

#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */

409

#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */

410

#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */

411

#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */

412

#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */

413

#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */

414

#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */

415

#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */

416

#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */

417

#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */

418

#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */

419

#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */

420

#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */

421

#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */

422

#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */

423

#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */

424

#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */

425

#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */

426

#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */

427

#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */

428

#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */

429

#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */

430

#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */

431

#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */

432

#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */

433

#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */

434

#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */

435

#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */

436

#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */

437

#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */

438

#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */

439

#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */

440

#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */

441

#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */

442

#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */

443

#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */

444

#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */

445

#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */

446

#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */

447

#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */

448

#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */

449

#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */

450

#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */

451

#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */

452

#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */

453

#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */

454

#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */

455

#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */

456

#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */

457

#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */

458

#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */

459

#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */

460

#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */

461

#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */

462

#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */

463

#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */

464

#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */

465

#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */

466

#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */

467

#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */

468

#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */

469

#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */

470

#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */

471

#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */

472

#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */

473

#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */

474

#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */

475

#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */

476

#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */

477

#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */

478

#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */

479

#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */

480

#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */

481

#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */

482

#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */

483

#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */

484

#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */

485

#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */

486

#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */

487

#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */

488

#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */

489

#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */

490

#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */

491

#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */

492

#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */

493

#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */

494

#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */

495

#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */

496

#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */

497

#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */

498

#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */

499

#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */

500

#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */

501

#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */

502

#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */

503

#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */

504

#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */

505

#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */

506

#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */

507

#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */

508

#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */

509

#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */

510

#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */

511

#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */

512

#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */

513

#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */

514

#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */

515

#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */

516

#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */

517

#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */

518

#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */

519

#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */

520

#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */

521

#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */

522

#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */

523

#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */

524

#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */

525

#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */

526

#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */

527

#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */

528

#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */

529

#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */

530

#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */

531

#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */

532

533

/* ATAPI Registers */

534

535

#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */

536

#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */

537

#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */

538

#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */

539

#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */

540

#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */

541

#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */

542

#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */

543

#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */

544

#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */

545

#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */

546

#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */

547

#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */

548

#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */

549

#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */

550

#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */

551

#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */

552

#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */

553

#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */

554

#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */

555

#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */

556

#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */

557

#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */

558

#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */

559

#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */

/* SDH Registers */

#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */

564

#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */

565

#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */

566

#define SDH_COMMAND 0xffc0390c /* SDH Command */

567

#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */

568

#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */

569

#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */

570

#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */

571

#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */

572

#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */

573

#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */

574

#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */

575

#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */

576

#define SDH_STATUS 0xffc03934 /* SDH Status */

577

#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */

578

#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */

579

#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */

580

#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */

581

#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */

582

#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */

583

#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */

584

#define SDH_CFG 0xffc039c8 /* SDH Configuration */

585

#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */

586

#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */

587

#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */

588

#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */

589

#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */

590

#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */

591

#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */

592

#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */

593

#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */

594

595

/* HOST Port Registers */

596

597

#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */

598

#define HOST_STATUS 0xffc03a04 /* HOST Status Register */

599

#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */

600

601

/* USB Control Registers */

602

603

#define USB_FADDR 0xffc03c00 /* Function address register */

604

#define USB_POWER 0xffc03c04 /* Power management register */

605

#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */

606

#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */

607

#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */

608

#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */

609

#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */

610

#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */

611

#define USB_FRAME 0xffc03c20 /* USB frame number */

612

#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */

613

#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */

614

#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */

615

#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */

616

617

/* USB Packet Control Registers */

618

619

#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */

620

#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */

621

#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */

622

#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */

623

#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */

624

#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */

625

#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */

626

#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */

627

#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */

628

#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */

629

#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */

630

#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */

631

#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */

632

633

/* USB Endpoint FIFO Registers */

634

635

#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */

636

#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */

637

#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */

638

#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */

639

#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */

640

#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */

641

#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */

642

#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */

643

644

/* USB OTG Control Registers */

645

646

#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */

647

#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */

648

#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */

649

650

/* USB Phy Control Registers */

651

652

#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */

653

#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */

654

#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */

655

#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */

656

#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */

657

658

/* (APHY_CNTRL is for ADI usage only) */

659

660

#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */

661

662

/* (APHY_CALIB is for ADI usage only) */

663

664

#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */

665

#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */

666

667

/* (PHY_TEST is for ADI usage only) */

668

669

#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */

670

#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */

671

#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */

672

673

/* USB Endpoint 0 Control Registers */

674

675

#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */

676

#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */

677

#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */

678

#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */

679

#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */

680

#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */

681

#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */

682

#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */

683

#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */

684

685

/* USB Endpoint 1 Control Registers */

686

687

#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */

688

#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */

689

#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */

690

#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */

691

#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */

692

#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */

693

#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */

694

#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */

695

#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */

696

#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */

697

698

/* USB Endpoint 2 Control Registers */

699

700

#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */

701

#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */

702

#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */

703

#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */

704

#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */

705

#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */

706

#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */

707

#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */

708

#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */

709

#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */

710

711

/* USB Endpoint 3 Control Registers */

712

713

#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */

714

#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */

715

#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */

716

#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */

717

#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */

718

#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */

719

#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */

720

#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */

721

#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */

722

#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */

723

724

/* USB Endpoint 4 Control Registers */

725

726

#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */

727

#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */

728

#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */

729

#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */

730

#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */

731

#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */

732

#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */

733

#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */

734

#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */

735

#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */

736

737

/* USB Endpoint 5 Control Registers */

738

739

#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */

740

#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */

741

#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */

742

#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */

743

#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */

744

#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */

745

#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */

746

#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */

747

#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */

748

#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */

749

750

/* USB Endpoint 6 Control Registers */

751

752

#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */

753

#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */

754

#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */

755

#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */

756

#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */

757

#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */

758

#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */

759

#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */

760

#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */

761

#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */

762

763

/* USB Endpoint 7 Control Registers */

764

765

#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */

766

#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */

767

#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */

768

#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */

769

#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */

770

#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */

771

#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */

772

#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */

773

#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */

774

#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */

775

#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */

776

#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */

777

778

/* USB Channel 0 Config Registers */

779

780

#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */

781

#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */

782

#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */

783

#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */

784

#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */

785

786

/* USB Channel 1 Config Registers */

787

788

#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */

789

#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */

790

#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */

791

#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */

792

#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */

793

794

/* USB Channel 2 Config Registers */

795

796

#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */

797

#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */

798

#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */

799

#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */

800

#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */

801

802

/* USB Channel 3 Config Registers */

803

804

#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */

805

#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */

806

#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */

807

#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */

808

#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */

809

810

/* USB Channel 4 Config Registers */

811

812

#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */

813

#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */

814

#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */

815

#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */

816

#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */

817

818

/* USB Channel 5 Config Registers */

819

820

#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */

821

#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */

822

#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */

823

#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */

824

#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */

825

826

/* USB Channel 6 Config Registers */

827

828

#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */

829

#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */

830

#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */

831

#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */

832

#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */

833

834

/* USB Channel 7 Config Registers */

835

836

#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */

837

#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */

838

#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */

839

#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */

840

#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */

841

842

/* Keypad Registers */

843

844

#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */

845

#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */

846

#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */

847

#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */

848

#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */

849

#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */

850

851

/* Pixel Compositor (PIXC) Registers */

852

853

#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */

854

#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */

855

#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */

856

#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */

857

#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */

858

#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */

859

#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */

860

#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */

861

#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */

862

#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */

863

#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */

864

#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */

865

#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */

866

#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */

867

#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */

868

#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */

869

#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */

870

#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */

871

#define PIXC_TC 0xffc04450 /* Holds the transparent color value */

872

873

/* Handshake MDMA 0 Registers */

874

875

#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */

876

#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */

877

#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */

878

#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */

879

#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */

880

#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */

881

#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */

882

883

/* Handshake MDMA 1 Registers */

884

885

#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */

886

#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */

887

#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */

888

#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */

889

#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */

890

#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */

891

#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */

892

893

894

/* ********************************************************** */

895

/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */

896

/* and MULTI BIT READ MACROS */

897

/* ********************************************************** */

898

899

/* Bit masks for PIXC_CTL */

900

901

#define PIXC_EN 0x1 /* Pixel Compositor Enable */

902

#define nPIXC_EN 0x0

903

#define OVR_A_EN 0x2 /* Overlay A Enable */

904

#define nOVR_A_EN 0x0

905

#define OVR_B_EN 0x4 /* Overlay B Enable */

906

#define nOVR_B_EN 0x0

907

#define IMG_FORM 0x8 /* Image Data Format */

908

#define nIMG_FORM 0x0

909

#define OVR_FORM 0x10 /* Overlay Data Format */

910

#define nOVR_FORM 0x0

911

#define OUT_FORM 0x20 /* Output Data Format */

912

#define nOUT_FORM 0x0

913

#define UDS_MOD 0x40 /* Resampling Mode */

914

#define nUDS_MOD 0x0

915

#define TC_EN 0x80 /* Transparent Color Enable */

916

#define nTC_EN 0x0

917

#define IMG_STAT 0x300 /* Image FIFO Status */

918

#define OVR_STAT 0xc00 /* Overlay FIFO Status */

919

#define WM_LVL 0x3000 /* FIFO Watermark Level */

920

921

/* Bit masks for PIXC_AHSTART */

922

923

#define A_HSTART 0xfff /* Horizontal Start Coordinates */

924

925

/* Bit masks for PIXC_AHEND */

926

927

#define A_HEND 0xfff /* Horizontal End Coordinates */

928

929

/* Bit masks for PIXC_AVSTART */

930

931

#define A_VSTART 0x3ff /* Vertical Start Coordinates */

932

933

/* Bit masks for PIXC_AVEND */

934

935

#define A_VEND 0x3ff /* Vertical End Coordinates */

936

937

/* Bit masks for PIXC_ATRANSP */

938

939

#define A_TRANSP 0xf /* Transparency Value */

940

941

/* Bit masks for PIXC_BHSTART */

942

943

#define B_HSTART 0xfff /* Horizontal Start Coordinates */

944

945

/* Bit masks for PIXC_BHEND */

946

947

#define B_HEND 0xfff /* Horizontal End Coordinates */

948

949

/* Bit masks for PIXC_BVSTART */

950

951

#define B_VSTART 0x3ff /* Vertical Start Coordinates */

952

953

/* Bit masks for PIXC_BVEND */

954

955

#define B_VEND 0x3ff /* Vertical End Coordinates */

956

957

/* Bit masks for PIXC_BTRANSP */

958

959

#define B_TRANSP 0xf /* Transparency Value */

960

961

/* Bit masks for PIXC_INTRSTAT */

962

963

#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */

964

#define nOVR_INT_EN 0x0

965

#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */

966

#define nFRM_INT_EN 0x0

967

#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */

968

#define nOVR_INT_STAT 0x0

969

#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */

970

#define nFRM_INT_STAT 0x0

971

972

/* Bit masks for PIXC_RYCON */

973

974

#define A11 0x3ff /* A11 in the Coefficient Matrix */

975

#define A12 0xffc00 /* A12 in the Coefficient Matrix */

976

#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */

977

#define RY_MULT4 0x40000000 /* Multiply Row by 4 */

978

#define nRY_MULT4 0x0

979

980

/* Bit masks for PIXC_GUCON */

981

982

#define A21 0x3ff /* A21 in the Coefficient Matrix */

983

#define A22 0xffc00 /* A22 in the Coefficient Matrix */

984

#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */

985

#define GU_MULT4 0x40000000 /* Multiply Row by 4 */

986

#define nGU_MULT4 0x0

987

988

/* Bit masks for PIXC_BVCON */

989

990

#define A31 0x3ff /* A31 in the Coefficient Matrix */

991

#define A32 0xffc00 /* A32 in the Coefficient Matrix */

992

#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */

993

#define BV_MULT4 0x40000000 /* Multiply Row by 4 */

994

#define nBV_MULT4 0x0

995

996

/* Bit masks for PIXC_CCBIAS */

997

998

#define A14 0x3ff /* A14 in the Bias Vector */

999

#define A24 0xffc00 /* A24 in the Bias Vector */

1000

#define A34 0x3ff00000 /* A34 in the Bias Vector */

1001

1002

/* Bit masks for PIXC_TC */

1003

1004

#define RY_TRANS 0xff /* Transparent Color - R/Y Component */

1005

#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */

1006

#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */

1007

1008

/* Bit masks for HOST_CONTROL */

1009

1010

#define HOST_EN 0x1 /* Host Enable */

1011

#define nHOST_EN 0x0

1012

#define HOST_END 0x2 /* Host Endianess */

1013

#define nHOST_END 0x0

1014

#define DATA_SIZE 0x4 /* Data Size */

1015

#define nDATA_SIZE 0x0

1016

#define HOST_RST 0x8 /* Host Reset */

1017

#define nHOST_RST 0x0

1018

#define HRDY_OVR 0x20 /* Host Ready Override */

1019

#define nHRDY_OVR 0x0

1020

#define INT_MODE 0x40 /* Interrupt Mode */

1021

#define nINT_MODE 0x0

1022

#define BT_EN 0x80 /* Bus Timeout Enable */

1023

#define nBT_EN 0x0

1024

#define EHW 0x100 /* Enable Host Write */

1025

#define nEHW 0x0

1026

#define EHR 0x200 /* Enable Host Read */

1027

#define nEHR 0x0

1028

#define BDR 0x400 /* Burst DMA Requests */

1029

#define nBDR 0x0

1030

1031

/* Bit masks for HOST_STATUS */

1032

1033

#define READY 0x1 /* DMA Ready */

1034

#define nREADY 0x0

1035

#define FIFOFULL 0x2 /* FIFO Full */

1036

#define nFIFOFULL 0x0

1037

#define FIFOEMPTY 0x4 /* FIFO Empty */

1038

#define nFIFOEMPTY 0x0

1039

#define COMPLETE 0x8 /* DMA Complete */

1040

#define nCOMPLETE 0x0

1041

#define HSHK 0x10 /* Host Handshake */

1042

#define nHSHK 0x0

1043

#define TIMEOUT 0x20 /* Host Timeout */

1044

#define nTIMEOUT 0x0

1045

#define HIRQ 0x40 /* Host Interrupt Request */

1046

#define nHIRQ 0x0

1047

#define ALLOW_CNFG 0x80 /* Allow New Configuration */

1048

#define nALLOW_CNFG 0x0

1049

#define DMA_DIR 0x100 /* DMA Direction */

1050

#define nDMA_DIR 0x0

1051

#define BTE 0x200 /* Bus Timeout Enabled */

1052

#define nBTE 0x0

1053

1054

/* Bit masks for HOST_TIMEOUT */

1055

1056

#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */

1057

1058

/* Bit masks for KPAD_CTL */

1059

1060

#define KPAD_EN 0x1 /* Keypad Enable */

1061

#define nKPAD_EN 0x0

1062

#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */

1063

#define KPAD_ROWEN 0x1c00 /* Row Enable Width */

1064

#define KPAD_COLEN 0xe000 /* Column Enable Width */

1065

1066

/* Bit masks for KPAD_PRESCALE */

1067

1068

#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */

1069

1070

/* Bit masks for KPAD_MSEL */

1071

1072

#define DBON_SCALE 0xff /* Debounce Scale Value */

1073

#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */

1074

1075

/* Bit masks for KPAD_ROWCOL */

1076

1077

#define KPAD_ROW 0xff /* Rows Pressed */

1078

#define KPAD_COL 0xff00 /* Columns Pressed */

1079

1080

/* Bit masks for KPAD_STAT */

1081

1082

#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */

1083

#define nKPAD_IRQ 0x0

1084

#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */

1085

#define KPAD_PRESSED 0x8 /* Key press current status */

1086

#define nKPAD_PRESSED 0x0

1087

1088

/* Bit masks for KPAD_SOFTEVAL */

1089

1090

#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */

1091

#define nKPAD_SOFTEVAL_E 0x0

1092

1093

/* Bit masks for SDH_COMMAND */

1094

1095

#define CMD_IDX 0x3f /* Command Index */

1096

#define CMD_RSP 0x40 /* Response */

1097

#define nCMD_RSP 0x0

1098

#define CMD_L_RSP 0x80 /* Long Response */

1099

#define nCMD_L_RSP 0x0

1100

#define CMD_INT_E 0x100 /* Command Interrupt */

1101

#define nCMD_INT_E 0x0

1102

#define CMD_PEND_E 0x200 /* Command Pending */

1103

#define nCMD_PEND_E 0x0

1104

#define CMD_E 0x400 /* Command Enable */

1105

#define nCMD_E 0x0

1106

1107

/* Bit masks for SDH_PWR_CTL */

1108

1109

#define PWR_ON 0x3 /* Power On */

1110

#if 0

1111

#define TBD 0x3c /* TBD */

1112

#endif

1113

#define SD_CMD_OD 0x40 /* Open Drain Output */

1114

#define nSD_CMD_OD 0x0

1115

#define ROD_CTL 0x80 /* Rod Control */

1116

#define nROD_CTL 0x0

1117

1118

/* Bit masks for SDH_CLK_CTL */

1119

1120

#define CLKDIV 0xff /* MC_CLK Divisor */

1121

#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */

1122

#define nCLK_E 0x0

1123

#define PWR_SV_E 0x200 /* Power Save Enable */

1124

#define nPWR_SV_E 0x0

1125

#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */

1126

#define nCLKDIV_BYPASS 0x0

1127

#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */

1128

#define nWIDE_BUS 0x0

1129

1130

/* Bit masks for SDH_RESP_CMD */

1131

1132

#define RESP_CMD 0x3f /* Response Command */

1133

1134

/* Bit masks for SDH_DATA_CTL */

1135

1136

#define DTX_E 0x1 /* Data Transfer Enable */

1137

#define nDTX_E 0x0

1138

#define DTX_DIR 0x2 /* Data Transfer Direction */

1139

#define nDTX_DIR 0x0

1140

#define DTX_MODE 0x4 /* Data Transfer Mode */

1141

#define nDTX_MODE 0x0

1142

#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */

1143

#define nDTX_DMA_E 0x0

1144

#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */

1145

1146

/* Bit masks for SDH_STATUS */

1147

1148

#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */

1149

#define nCMD_CRC_FAIL 0x0

1150

#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */

1151

#define nDAT_CRC_FAIL 0x0

1152

#define CMD_TIMEOUT 0x4 /* CMD Time Out */

1153

#define nCMD_TIMEOUT 0x0

1154

#define DAT_TIMEOUT 0x8 /* Data Time Out */

1155

#define nDAT_TIMEOUT 0x0

1156

#define TX_UNDERRUN 0x10 /* Transmit Underrun */

1157

#define nTX_UNDERRUN 0x0

1158

#define RX_OVERRUN 0x20 /* Receive Overrun */

1159

#define nRX_OVERRUN 0x0

1160

#define CMD_RESP_END 0x40 /* CMD Response End */

1161

#define nCMD_RESP_END 0x0

1162

#define CMD_SENT 0x80 /* CMD Sent */

1163

#define nCMD_SENT 0x0

1164

#define DAT_END 0x100 /* Data End */

1165

#define nDAT_END 0x0

1166

#define START_BIT_ERR 0x200 /* Start Bit Error */

1167

#define nSTART_BIT_ERR 0x0

1168

#define DAT_BLK_END 0x400 /* Data Block End */

1169

#define nDAT_BLK_END 0x0

1170

#define CMD_ACT 0x800 /* CMD Active */

1171

#define nCMD_ACT 0x0

1172

#define TX_ACT 0x1000 /* Transmit Active */

1173

#define nTX_ACT 0x0

1174

#define RX_ACT 0x2000 /* Receive Active */

1175

#define nRX_ACT 0x0

1176

#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */

1177

#define nTX_FIFO_STAT 0x0

1178

#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */

1179

#define nRX_FIFO_STAT 0x0

1180

#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */

1181

#define nTX_FIFO_FULL 0x0

1182

#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */

1183

#define nRX_FIFO_FULL 0x0

1184

#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */

1185

#define nTX_FIFO_ZERO 0x0

1186

#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */

1187

#define nRX_DAT_ZERO 0x0

1188

#define TX_DAT_RDY 0x100000 /* Transmit Data Available */

1189

#define nTX_DAT_RDY 0x0

1190

#define RX_FIFO_RDY 0x200000 /* Receive Data Available */

1191

#define nRX_FIFO_RDY 0x0

1192

1193

/* Bit masks for SDH_STATUS_CLR */

1194

1195

#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */

1196

#define nCMD_CRC_FAIL_STAT 0x0

1197

#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */

1198

#define nDAT_CRC_FAIL_STAT 0x0

1199

#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */

1200

#define nCMD_TIMEOUT_STAT 0x0

1201

#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */

1202

#define nDAT_TIMEOUT_STAT 0x0

1203

#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */

1204

#define nTX_UNDERRUN_STAT 0x0

1205

#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */

1206

#define nRX_OVERRUN_STAT 0x0

1207

#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */

1208

#define nCMD_RESP_END_STAT 0x0

1209

#define CMD_SENT_STAT 0x80 /* CMD Sent Status */

1210

#define nCMD_SENT_STAT 0x0

1211

#define DAT_END_STAT 0x100 /* Data End Status */

1212

#define nDAT_END_STAT 0x0

1213

#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */

1214

#define nSTART_BIT_ERR_STAT 0x0

1215

#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */

1216

#define nDAT_BLK_END_STAT 0x0

1217

1218

/* Bit masks for SDH_MASK0 */

1219

1220

#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */

1221

#define nCMD_CRC_FAIL_MASK 0x0

1222

#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */

1223

#define nDAT_CRC_FAIL_MASK 0x0

1224

#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */

1225

#define nCMD_TIMEOUT_MASK 0x0

1226

#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */

1227

#define nDAT_TIMEOUT_MASK 0x0

1228

#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */

1229

#define nTX_UNDERRUN_MASK 0x0

1230

#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */

1231

#define nRX_OVERRUN_MASK 0x0

1232

#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */

1233

#define nCMD_RESP_END_MASK 0x0

1234

#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */

1235

#define nCMD_SENT_MASK 0x0

1236

#define DAT_END_MASK 0x100 /* Data End Mask */

1237

#define nDAT_END_MASK 0x0

1238

#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */

1239

#define nSTART_BIT_ERR_MASK 0x0

1240

#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */

1241

#define nDAT_BLK_END_MASK 0x0

1242

#define CMD_ACT_MASK 0x800 /* CMD Active Mask */

1243

#define nCMD_ACT_MASK 0x0

1244

#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */

1245

#define nTX_ACT_MASK 0x0

1246

#define RX_ACT_MASK 0x2000 /* Receive Active Mask */

1247

#define nRX_ACT_MASK 0x0

1248

#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */

1249

#define nTX_FIFO_STAT_MASK 0x0

1250

#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */

1251

#define nRX_FIFO_STAT_MASK 0x0

1252

#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */

1253

#define nTX_FIFO_FULL_MASK 0x0

1254

#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */

1255

#define nRX_FIFO_FULL_MASK 0x0

1256

#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */

1257

#define nTX_FIFO_ZERO_MASK 0x0

1258

#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */

1259

#define nRX_DAT_ZERO_MASK 0x0

1260

#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */

1261

#define nTX_DAT_RDY_MASK 0x0

1262

#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */

1263

#define nRX_FIFO_RDY_MASK 0x0

1264

1265

/* Bit masks for SDH_FIFO_CNT */

1266

1267

#define FIFO_COUNT 0x7fff /* FIFO Count */

1268

1269

/* Bit masks for SDH_E_STATUS */

1270

1271

#define SDIO_INT_DET 0x2 /* SDIO Int Detected */

1272

#define nSDIO_INT_DET 0x0

1273

#define SD_CARD_DET 0x10 /* SD Card Detect */

1274

#define nSD_CARD_DET 0x0

1275

1276

/* Bit masks for SDH_E_MASK */

1277

1278

#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */

1279

#define nSDIO_MSK 0x0

1280

#define SCD_MSK 0x40 /* Mask Card Detect */

1281

#define nSCD_MSK 0x0

1282

1283

/* Bit masks for SDH_CFG */

1284

1285

#define CLKS_EN 0x1 /* Clocks Enable */

1286

#define nCLKS_EN 0x0

1287

#define SD4E 0x4 /* SDIO 4-Bit Enable */

1288

#define nSD4E 0x0

1289

#define MWE 0x8 /* Moving Window Enable */

1290

#define nMWE 0x0

1291

#define SD_RST 0x10 /* SDMMC Reset */

1292

#define nSD_RST 0x0

1293

#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */

1294

#define nPUP_SDDAT 0x0

1295

#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */

1296

#define nPUP_SDDAT3 0x0

1297

#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */

1298

#define nPD_SDDAT3 0x0

1299

1300

/* Bit masks for SDH_RD_WAIT_EN */

1301

1302

#define RWR 0x1 /* Read Wait Request */

1303

#define nRWR 0x0

1304

1305

/* Bit masks for ATAPI_CONTROL */

1306

1307

#define PIO_START 0x1 /* Start PIO/Reg Op */

1308

#define nPIO_START 0x0

1309

#define MULTI_START 0x2 /* Start Multi-DMA Op */

1310

#define nMULTI_START 0x0

1311

#define ULTRA_START 0x4 /* Start Ultra-DMA Op */

1312

#define nULTRA_START 0x0

1313

#define XFER_DIR 0x8 /* Transfer Direction */

1314

#define nXFER_DIR 0x0

1315

#define IORDY_EN 0x10 /* IORDY Enable */

1316

#define nIORDY_EN 0x0

1317

#define FIFO_FLUSH 0x20 /* Flush FIFOs */

1318

#define nFIFO_FLUSH 0x0

1319

#define SOFT_RST 0x40 /* Soft Reset */

1320

#define nSOFT_RST 0x0

1321

#define DEV_RST 0x80 /* Device Reset */

1322

#define nDEV_RST 0x0

1323

#define TFRCNT_RST 0x100 /* Trans Count Reset */

1324

#define nTFRCNT_RST 0x0

1325

#define END_ON_TERM 0x200 /* End/Terminate Select */

1326

#define nEND_ON_TERM 0x0

1327

#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */

1328

#define nPIO_USE_DMA 0x0

1329

#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */

1330

1331

/* Bit masks for ATAPI_STATUS */

1332

1333

#define PIO_XFER_ON 0x1 /* PIO transfer in progress */

1334

#define nPIO_XFER_ON 0x0

1335

#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */

1336

#define nMULTI_XFER_ON 0x0

1337

#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */

1338

#define nULTRA_XFER_ON 0x0

1339

#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */

1340

1341

/* Bit masks for ATAPI_DEV_ADDR */

1342

1343

#define DEV_ADDR 0x1f /* Device Address */

1344

1345

/* Bit masks for ATAPI_INT_MASK */

1346

1347

#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */

1348

#define nATAPI_DEV_INT_MASK 0x0

1349

#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */

1350

#define nPIO_DONE_MASK 0x0

1351

#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */

1352

#define nMULTI_DONE_MASK 0x0

1353

#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */

1354

#define nUDMAIN_DONE_MASK 0x0

1355

#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */

1356

#define nUDMAOUT_DONE_MASK 0x0

1357

#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */

1358

#define nHOST_TERM_XFER_MASK 0x0

1359

#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */

1360

#define nMULTI_TERM_MASK 0x0

1361

#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */

1362

#define nUDMAIN_TERM_MASK 0x0

1363

#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */

1364

#define nUDMAOUT_TERM_MASK 0x0

1365

1366

/* Bit masks for ATAPI_INT_STATUS */

1367

1368

#define ATAPI_DEV_INT 0x1 /* Device interrupt status */

1369

#define nATAPI_DEV_INT 0x0

1370

#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */

1371

#define nPIO_DONE_INT 0x0

1372

#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */

1373

#define nMULTI_DONE_INT 0x0

1374

#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */

1375

#define nUDMAIN_DONE_INT 0x0

1376

#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */

1377

#define nUDMAOUT_DONE_INT 0x0

1378

#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */

1379

#define nHOST_TERM_XFER_INT 0x0

1380

#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */

1381

#define nMULTI_TERM_INT 0x0

1382

#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */

1383

#define nUDMAIN_TERM_INT 0x0

1384

#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */

1385

#define nUDMAOUT_TERM_INT 0x0

1386

1387

/* Bit masks for ATAPI_LINE_STATUS */

1388

1389

#define ATAPI_INTR 0x1 /* Device interrupt to host line status */

1390

#define nATAPI_INTR 0x0

1391

#define ATAPI_DASP 0x2 /* Device dasp to host line status */

1392

#define nATAPI_DASP 0x0

1393

#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */

1394

#define nATAPI_CS0N 0x0

1395

#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */

1396

#define nATAPI_CS1N 0x0

1397

#define ATAPI_ADDR 0x70 /* ATAPI address line status */

1398

#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */

1399

#define nATAPI_DMAREQ 0x0

1400

#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */

1401

#define nATAPI_DMAACKN 0x0

1402

#define ATAPI_DIOWN 0x200 /* ATAPI write line status */

1403

#define nATAPI_DIOWN 0x0

1404

#define ATAPI_DIORN 0x400 /* ATAPI read line status */

1405

#define nATAPI_DIORN 0x0

1406

#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */

1407

#define nATAPI_IORDY 0x0

1408

1409

/* Bit masks for ATAPI_SM_STATE */

1410

1411

#define PIO_CSTATE 0xf /* PIO mode state machine current state */

1412

#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */

1413

#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */

1414

#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */

1415

1416

/* Bit masks for ATAPI_TERMINATE */

1417

1418

#define ATAPI_HOST_TERM 0x1 /* Host terminationation */

1419

#define nATAPI_HOST_TERM 0x0

1420

1421

/* Bit masks for ATAPI_REG_TIM_0 */

1422

1423

#define T2_REG 0xff /* End of cycle time for register access transfers */

1424

#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */

1425

1426

/* Bit masks for ATAPI_PIO_TIM_0 */

1427

1428

#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */

1429

#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */

1430

#define T4_REG 0xf000 /* DIOW data hold */

1431

1432

/* Bit masks for ATAPI_PIO_TIM_1 */

1433

1434

#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */

1435

1436

/* Bit masks for ATAPI_MULTI_TIM_0 */

1437

1438

#define TD 0xff /* DIOR/DIOW asserted pulsewidth */

1439

#define TM 0xff00 /* Time from address valid to DIOR/DIOW */

1440

1441

/* Bit masks for ATAPI_MULTI_TIM_1 */

1442

1443

#define TKW 0xff /* Selects DIOW negated pulsewidth */

1444

#define TKR 0xff00 /* Selects DIOR negated pulsewidth */

1445

1446

/* Bit masks for ATAPI_MULTI_TIM_2 */

1447

1448

#define TH 0xff /* Selects DIOW data hold */

1449

#define TEOC 0xff00 /* Selects end of cycle for DMA */

1450

1451

/* Bit masks for ATAPI_ULTRA_TIM_0 */

1452

1453

#define TACK 0xff /* Selects setup and hold times for TACK */

1454

#define TENV 0xff00 /* Selects envelope time */

1455

1456

/* Bit masks for ATAPI_ULTRA_TIM_1 */

1457

1458

#define TDVS 0xff /* Selects data valid setup time */

1459

#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */

1460

1461

/* Bit masks for ATAPI_ULTRA_TIM_2 */

1462

1463

#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */

1464

#define TMLI 0xff00 /* Selects interlock time */

1465

1466

/* Bit masks for ATAPI_ULTRA_TIM_3 */

1467

1468

#define TZAH 0xff /* Selects minimum delay required for output */

1469

#define READY_PAUSE 0xff00 /* Selects ready to pause */

1470

1471

/* Bit masks for TIMER_ENABLE1 */

1472

1473

#define TIMEN8 0x1 /* Timer 8 Enable */

1474

#define nTIMEN8 0x0

1475

#define TIMEN9 0x2 /* Timer 9 Enable */

1476

#define nTIMEN9 0x0

1477

#define TIMEN10 0x4 /* Timer 10 Enable */

1478

#define nTIMEN10 0x0

1479

1480

/* Bit masks for TIMER_DISABLE1 */

1481

1482

#define TIMDIS8 0x1 /* Timer 8 Disable */

1483

#define nTIMDIS8 0x0

1484

#define TIMDIS9 0x2 /* Timer 9 Disable */

1485

#define nTIMDIS9 0x0

1486

#define TIMDIS10 0x4 /* Timer 10 Disable */

1487

#define nTIMDIS10 0x0

1488

1489

/* Bit masks for TIMER_STATUS1 */

1490

1491

#define TIMIL8 0x1 /* Timer 8 Interrupt */

1492

#define nTIMIL8 0x0

1493

#define TIMIL9 0x2 /* Timer 9 Interrupt */

1494

#define nTIMIL9 0x0

1495

#define TIMIL10 0x4 /* Timer 10 Interrupt */

1496

#define nTIMIL10 0x0

1497

#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */

1498

#define nTOVF_ERR8 0x0

1499

#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */

1500

#define nTOVF_ERR9 0x0

1501

#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */

1502

#define nTOVF_ERR10 0x0

1503

#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */

1504

#define nTRUN8 0x0

1505

#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */

1506

#define nTRUN9 0x0

1507

#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */

1508

#define nTRUN10 0x0

1509

1510

/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */

1511

1512

/* Bit masks for USB_FADDR */

1513

1514

#define FUNCTION_ADDRESS 0x7f /* Function address */

1515

1516

/* Bit masks for USB_POWER */

1517

1518

#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */

1519

#define nENABLE_SUSPENDM 0x0

1520

#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */

1521

#define nSUSPEND_MODE 0x0

1522

#define RESUME_MODE 0x4 /* DMA Mode */

1523

#define nRESUME_MODE 0x0

1524

#define RESET 0x8 /* Reset indicator */

1525

#define nRESET 0x0

1526

#define HS_MODE 0x10 /* High Speed mode indicator */

1527

#define nHS_MODE 0x0

1528

#define HS_ENABLE 0x20 /* high Speed Enable */

1529

#define nHS_ENABLE 0x0

1530

#define SOFT_CONN 0x40 /* Soft connect */

1531

#define nSOFT_CONN 0x0

1532

#define ISO_UPDATE 0x80 /* Isochronous update */

1533

#define nISO_UPDATE 0x0

1534

1535

/* Bit masks for USB_INTRTX */

1536

1537

#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */

1538

#define nEP0_TX 0x0

1539

#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */

1540

#define nEP1_TX 0x0

1541

#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */

1542

#define nEP2_TX 0x0

1543

#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */

1544

#define nEP3_TX 0x0

1545

#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */

1546

#define nEP4_TX 0x0

1547

#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */

1548

#define nEP5_TX 0x0

1549

#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */

1550

#define nEP6_TX 0x0

1551

#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */

1552

#define nEP7_TX 0x0

1553

1554

/* Bit masks for USB_INTRRX */

1555

1556

#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */

1557

#define nEP1_RX 0x0

1558

#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */

1559

#define nEP2_RX 0x0

1560

#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */

1561

#define nEP3_RX 0x0

1562

#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */

1563

#define nEP4_RX 0x0

1564

#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */

1565

#define nEP5_RX 0x0

1566

#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */

1567

#define nEP6_RX 0x0

1568

#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */

1569

#define nEP7_RX 0x0

1570

1571

/* Bit masks for USB_INTRTXE */

1572

1573

#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */

1574

#define nEP0_TX_E 0x0

1575

#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */

1576

#define nEP1_TX_E 0x0

1577

#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */

1578

#define nEP2_TX_E 0x0

1579

#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */

1580

#define nEP3_TX_E 0x0

1581

#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */

1582

#define nEP4_TX_E 0x0

1583

#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */

1584

#define nEP5_TX_E 0x0

1585

#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */

1586

#define nEP6_TX_E 0x0

1587

#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */

1588

#define nEP7_TX_E 0x0

1589

1590

/* Bit masks for USB_INTRRXE */

1591

1592

#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */

1593

#define nEP1_RX_E 0x0

1594

#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */

1595

#define nEP2_RX_E 0x0

1596

#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */

1597

#define nEP3_RX_E 0x0

1598

#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */

1599

#define nEP4_RX_E 0x0

1600

#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */

1601

#define nEP5_RX_E 0x0

1602

#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */

1603

#define nEP6_RX_E 0x0

1604

#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */

1605

#define nEP7_RX_E 0x0

1606

1607

/* Bit masks for USB_INTRUSB */

1608

1609

#define SUSPEND_B 0x1 /* Suspend indicator */

1610

#define nSUSPEND_B 0x0

1611

#define RESUME_B 0x2 /* Resume indicator */

1612

#define nRESUME_B 0x0

1613

#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */

1614

#define nRESET_OR_BABLE_B 0x0

1615

#define SOF_B 0x8 /* Start of frame */

1616

#define nSOF_B 0x0

1617

#define CONN_B 0x10 /* Connection indicator */

1618

#define nCONN_B 0x0

1619

#define DISCON_B 0x20 /* Disconnect indicator */

1620

#define nDISCON_B 0x0

1621

#define SESSION_REQ_B 0x40 /* Session Request */

1622

#define nSESSION_REQ_B 0x0

1623

#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */

1624

#define nVBUS_ERROR_B 0x0

1625

1626

/* Bit masks for USB_INTRUSBE */

1627

1628

#define SUSPEND_BE 0x1 /* Suspend indicator int enable */

1629

#define nSUSPEND_BE 0x0

1630

#define RESUME_BE 0x2 /* Resume indicator int enable */

1631

#define nRESUME_BE 0x0

1632

#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */

1633

#define nRESET_OR_BABLE_BE 0x0

1634

#define SOF_BE 0x8 /* Start of frame int enable */

1635

#define nSOF_BE 0x0

1636

#define CONN_BE 0x10 /* Connection indicator int enable */

1637

#define nCONN_BE 0x0

1638

#define DISCON_BE 0x20 /* Disconnect indicator int enable */

1639

#define nDISCON_BE 0x0

1640

#define SESSION_REQ_BE 0x40 /* Session Request int enable */

1641

#define nSESSION_REQ_BE 0x0

1642

#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */

1643

#define nVBUS_ERROR_BE 0x0

1644

1645

/* Bit masks for USB_FRAME */

1646

1647

#define FRAME_NUMBER 0x7ff /* Frame number */

1648

1649

/* Bit masks for USB_INDEX */

1650

1651

#define SELECTED_ENDPOINT 0xf /* selected endpoint */

1652

1653

/* Bit masks for USB_GLOBAL_CTL */

1654

1655

#define GLOBAL_ENA 0x1 /* enables USB module */

1656

#define nGLOBAL_ENA 0x0

1657

#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */

1658

#define nEP1_TX_ENA 0x0

1659

#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */

1660

#define nEP2_TX_ENA 0x0

1661

#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */

1662

#define nEP3_TX_ENA 0x0

1663

#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */

1664

#define nEP4_TX_ENA 0x0

1665

#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */

1666

#define nEP5_TX_ENA 0x0

1667

#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */

1668

#define nEP6_TX_ENA 0x0

1669

#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */

1670

#define nEP7_TX_ENA 0x0

1671

#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */

1672

#define nEP1_RX_ENA 0x0

1673

#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */

1674

#define nEP2_RX_ENA 0x0

1675

#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */

1676

#define nEP3_RX_ENA 0x0

1677

#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */

1678

#define nEP4_RX_ENA 0x0

1679

#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */

1680

#define nEP5_RX_ENA 0x0

1681

#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */

1682

#define nEP6_RX_ENA 0x0

1683

#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */

1684

#define nEP7_RX_ENA 0x0

1685

1686

/* Bit masks for USB_OTG_DEV_CTL */

1687

1688

#define SESSION 0x1 /* session indicator */

1689

#define nSESSION 0x0

1690

#define HOST_REQ 0x2 /* Host negotiation request */

1691

#define nHOST_REQ 0x0

1692

#define HOST_MODE 0x4 /* indicates USBDRC is a host */

1693

#define nHOST_MODE 0x0

1694

#define VBUS0 0x8 /* Vbus level indicator[0] */

1695

#define nVBUS0 0x0

1696

#define VBUS1 0x10 /* Vbus level indicator[1] */

1697

#define nVBUS1 0x0

1698

#define LSDEV 0x20 /* Low-speed indicator */

1699

#define nLSDEV 0x0

1700

#define FSDEV 0x40 /* Full or High-speed indicator */

1701

#define nFSDEV 0x0

1702

#define B_DEVICE 0x80 /* A' or 'B' device indicator */

1703

#define nB_DEVICE 0x0

1704

1705

/* Bit masks for USB_OTG_VBUS_IRQ */

1706

1707

#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */

1708

#define nDRIVE_VBUS_ON 0x0

1709

#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */

1710

#define nDRIVE_VBUS_OFF 0x0

1711

#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */

1712

#define nCHRG_VBUS_START 0x0

1713

#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */

1714

#define nCHRG_VBUS_END 0x0

1715

#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */

1716

#define nDISCHRG_VBUS_START 0x0

1717

#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */

1718

#define nDISCHRG_VBUS_END 0x0

1719

1720

/* Bit masks for USB_OTG_VBUS_MASK */

1721

1722

#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */

1723

#define nDRIVE_VBUS_ON_ENA 0x0

1724

#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */

1725

#define nDRIVE_VBUS_OFF_ENA 0x0

1726

#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */

1727

#define nCHRG_VBUS_START_ENA 0x0

1728

#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */

1729

#define nCHRG_VBUS_END_ENA 0x0

1730

#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */

1731

#define nDISCHRG_VBUS_START_ENA 0x0

1732

#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */

1733

#define nDISCHRG_VBUS_END_ENA 0x0

1734

1735

/* Bit masks for USB_CSR0 */

1736

1737

#define RXPKTRDY 0x1 /* data packet receive indicator */

1738

#define nRXPKTRDY 0x0

1739

#define TXPKTRDY 0x2 /* data packet in FIFO indicator */

1740

#define nTXPKTRDY 0x0

1741

#define STALL_SENT 0x4 /* STALL handshake sent */

1742

#define nSTALL_SENT 0x0

1743

#define DATAEND 0x8 /* Data end indicator */

1744

#define nDATAEND 0x0

1745

#define SETUPEND 0x10 /* Setup end */

1746

#define nSETUPEND 0x0

1747

#define SENDSTALL 0x20 /* Send STALL handshake */

1748

#define nSENDSTALL 0x0

1749

#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */

1750

#define nSERVICED_RXPKTRDY 0x0

1751

#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */

1752

#define nSERVICED_SETUPEND 0x0

1753

#define FLUSHFIFO 0x100 /* flush endpoint FIFO */

1754

#define nFLUSHFIFO 0x0

1755

#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */

1756

#define nSTALL_RECEIVED_H 0x0

1757

#define SETUPPKT_H 0x8 /* send Setup token host mode */

1758

#define nSETUPPKT_H 0x0

1759

#define ERROR_H 0x10 /* timeout error indicator host mode */

1760

#define nERROR_H 0x0

1761

#define REQPKT_H 0x20 /* Request an IN transaction host mode */

1762

#define nREQPKT_H 0x0

1763

#define STATUSPKT_H 0x40 /* Status stage transaction host mode */

1764

#define nSTATUSPKT_H 0x0

1765

#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */

1766

#define nNAK_TIMEOUT_H 0x0

1767

1768

/* Bit masks for USB_COUNT0 */

1769

1770

#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */

1771

1772

/* Bit masks for USB_NAKLIMIT0 */

1773

1774

#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */

1775

1776

/* Bit masks for USB_TX_MAX_PACKET */

1777

1778

#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */

1779

1780

/* Bit masks for USB_RX_MAX_PACKET */

1781

1782

#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */

1783

1784

/* Bit masks for USB_TXCSR */

1785

1786

#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */

1787

#define nTXPKTRDY_T 0x0

1788

#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */

1789

#define nFIFO_NOT_EMPTY_T 0x0

1790

#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */

1791

#define nUNDERRUN_T 0x0

1792

#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */

1793

#define nFLUSHFIFO_T 0x0

1794

#define STALL_SEND_T 0x10 /* issue a Stall handshake */

1795

#define nSTALL_SEND_T 0x0

1796

#define STALL_SENT_T 0x20 /* Stall handshake transmitted */

1797

#define nSTALL_SENT_T 0x0

1798

#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */

1799

#define nCLEAR_DATATOGGLE_T 0x0

1800

#define INCOMPTX_T 0x80 /* indicates that a large packet is split */

1801

#define nINCOMPTX_T 0x0

1802

#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */

1803

#define nDMAREQMODE_T 0x0

1804

#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */

1805

#define nFORCE_DATATOGGLE_T 0x0

1806

#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */

1807

#define nDMAREQ_ENA_T 0x0

1808

#define ISO_T 0x4000 /* enable Isochronous transfers */

1809

#define nISO_T 0x0

1810

#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */

1811

#define nAUTOSET_T 0x0

1812

#define ERROR_TH 0x4 /* error condition host mode */

1813

#define nERROR_TH 0x0

1814

#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */

1815

#define nSTALL_RECEIVED_TH 0x0

1816

#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */

1817

#define nNAK_TIMEOUT_TH 0x0

1818

1819

/* Bit masks for USB_TXCOUNT */

1820

1821

#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */

1822

1823

/* Bit masks for USB_RXCSR */

1824

1825

#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */

1826

#define nRXPKTRDY_R 0x0

1827

#define FIFO_FULL_R 0x2 /* FIFO not empty */

1828

#define nFIFO_FULL_R 0x0

1829

#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */

1830

#define nOVERRUN_R 0x0

1831

#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */

1832

#define nDATAERROR_R 0x0

1833

#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */

1834

#define nFLUSHFIFO_R 0x0

1835

#define STALL_SEND_R 0x20 /* issue a Stall handshake */

1836

#define nSTALL_SEND_R 0x0

1837

#define STALL_SENT_R 0x40 /* Stall handshake transmitted */

1838

#define nSTALL_SENT_R 0x0

1839

#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */

1840

#define nCLEAR_DATATOGGLE_R 0x0

1841

#define INCOMPRX_R 0x100 /* indicates that a large packet is split */

1842

#define nINCOMPRX_R 0x0

1843

#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */

1844

#define nDMAREQMODE_R 0x0

1845

#define DISNYET_R 0x1000 /* disable Nyet handshakes */

1846

#define nDISNYET_R 0x0

1847

#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */

1848

#define nDMAREQ_ENA_R 0x0

1849

#define ISO_R 0x4000 /* enable Isochronous transfers */

1850

#define nISO_R 0x0

1851

#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */

1852

#define nAUTOCLEAR_R 0x0

1853

#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */

1854

#define nERROR_RH 0x0

1855

#define REQPKT_RH 0x20 /* request an IN transaction host mode */

1856

#define nREQPKT_RH 0x0

1857

#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */

1858

#define nSTALL_RECEIVED_RH 0x0

1859

#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */

1860

#define nINCOMPRX_RH 0x0

1861

#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */

1862

#define nDMAREQMODE_RH 0x0

1863

#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */

1864

#define nAUTOREQ_RH 0x0

1865

1866

/* Bit masks for USB_RXCOUNT */

1867

1868

#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */

1869

1870

/* Bit masks for USB_TXTYPE */

1871

1872

#define TARGET_EP_NO_T 0xf /* EP number */

1873

#define PROTOCOL_T 0xc /* transfer type */

1874

1875

/* Bit masks for USB_TXINTERVAL */

1876

1877

#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */

1878

1879

/* Bit masks for USB_RXTYPE */

1880

1881

#define TARGET_EP_NO_R 0xf /* EP number */

1882

#define PROTOCOL_R 0xc /* transfer type */

1883

1884

/* Bit masks for USB_RXINTERVAL */

1885

1886

#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */

1887

1888

/* Bit masks for USB_DMA_INTERRUPT */

1889

1890

#define DMA0_INT 0x1 /* DMA0 pending interrupt */

1891

#define nDMA0_INT 0x0

1892

#define DMA1_INT 0x2 /* DMA1 pending interrupt */

1893

#define nDMA1_INT 0x0

1894

#define DMA2_INT 0x4 /* DMA2 pending interrupt */

1895

#define nDMA2_INT 0x0

1896

#define DMA3_INT 0x8 /* DMA3 pending interrupt */

1897

#define nDMA3_INT 0x0

1898

#define DMA4_INT 0x10 /* DMA4 pending interrupt */

1899

#define nDMA4_INT 0x0

1900

#define DMA5_INT 0x20 /* DMA5 pending interrupt */

1901

#define nDMA5_INT 0x0

1902

#define DMA6_INT 0x40 /* DMA6 pending interrupt */

1903

#define nDMA6_INT 0x0

1904

#define DMA7_INT 0x80 /* DMA7 pending interrupt */

1905

#define nDMA7_INT 0x0

1906

1907

/* Bit masks for USB_DMAxCONTROL */

1908

1909

#define DMA_ENA 0x1 /* DMA enable */

1910

#define nDMA_ENA 0x0

1911

#define DIRECTION 0x2 /* direction of DMA transfer */

1912

#define nDIRECTION 0x0

1913

#define MODE 0x4 /* DMA Bus error */

1914

#define nMODE 0x0

1915

#define INT_ENA 0x8 /* Interrupt enable */

1916

#define nINT_ENA 0x0

1917

#define EPNUM 0xf0 /* EP number */

1918

#define BUSERROR 0x100 /* DMA Bus error */

1919

#define nBUSERROR 0x0

1920

1921

/* Bit masks for USB_DMAxADDRHIGH */

1922

1923

#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */

1924

1925

/* Bit masks for USB_DMAxADDRLOW */

1926

1927

#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */

1928

1929

/* Bit masks for USB_DMAxCOUNTHIGH */

1930

1931

#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */

1932

1933

/* Bit masks for USB_DMAxCOUNTLOW */

1934

1935

#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */

1936

1937

/* Bit masks for HMDMAx_CONTROL */

1938

1939

#define HMDMAEN 0x1 /* Handshake MDMA Enable */

1940

#define nHMDMAEN 0x0

1941

#define REP 0x2 /* Handshake MDMA Request Polarity */

1942

#define nREP 0x0

1943

#define UTE 0x8 /* Urgency Threshold Enable */

1944

#define nUTE 0x0

1945

#define OIE 0x10 /* Overflow Interrupt Enable */

1946

#define nOIE 0x0

1947

#define BDIE 0x20 /* Block Done Interrupt Enable */

1948

#define nBDIE 0x0

1949

#define MBDI 0x40 /* Mask Block Done Interrupt */

1950

#define nMBDI 0x0

1951

#define DRQ 0x300 /* Handshake MDMA Request Type */

1952

#define RBC 0x1000 /* Force Reload of BCOUNT */

1953

#define nRBC 0x0

1954

#define PS 0x2000 /* Pin Status */

1955

#define nPS 0x0

1956

#define OI 0x4000 /* Overflow Interrupt Generated */

1957

#define nOI 0x0

1958

#define BDI 0x8000 /* Block Done Interrupt Generated */

1959

#define nBDI 0x0

1960

1961

/* ******************************************* */

1962

/* MULTI BIT MACRO ENUMERATIONS */

1963

/* ******************************************* */

1964

1965

1966

#endif /* _DEF_BF548_H */