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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* linux/drivers/mtd/nand/s3c2410.c
2 *
Ben Dooks7e74a502008-05-20 17:32:27 +01003 * Copyright © 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
Ben Dooksfdf2fd52005-02-18 14:46:15 +00005 * Ben Dooks <ben@simtec.co.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
Ben Dooks7e74a502008-05-20 17:32:27 +01007 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
Sachin Kamat92aeb5d2012-07-16 16:02:23 +053024#define pr_fmt(fmt) "nand-s3c2410: " fmt
25
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
27#define DEBUG
28#endif
29
30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
Sachin Kamatd2a89be2012-07-16 16:02:24 +053035#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/ioport.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010037#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <linux/delay.h>
39#include <linux/err.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080040#include <linux/slab.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000041#include <linux/clk.h>
Ben Dooks30821fe2008-07-15 11:58:31 +010042#include <linux/cpufreq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
44#include <linux/mtd/mtd.h>
45#include <linux/mtd/nand.h>
46#include <linux/mtd/nand_ecc.h>
47#include <linux/mtd/partitions.h>
48
Ben Dooks7926b5a2008-10-30 10:14:35 +000049#include <plat/regs-nand.h>
50#include <plat/nand.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Linus Torvalds1da177e2005-04-16 15:20:36 -070052/* new oob placement block for use with hardware ecc generation
53 */
54
Thomas Gleixner5bd34c02006-05-27 22:16:10 +020055static struct nand_ecclayout nand_hw_eccoob = {
David Woodhousee0c7d762006-05-13 18:07:53 +010056 .eccbytes = 3,
57 .eccpos = {0, 1, 2},
58 .oobfree = {{8, 8}}
Linus Torvalds1da177e2005-04-16 15:20:36 -070059};
60
61/* controller and mtd information */
62
63struct s3c2410_nand_info;
64
Ben Dooks3db72152009-05-30 17:18:15 +010065/**
66 * struct s3c2410_nand_mtd - driver MTD structure
67 * @mtd: The MTD instance to pass to the MTD layer.
68 * @chip: The NAND chip information.
69 * @set: The platform information supplied for this set of NAND chips.
70 * @info: Link back to the hardware information.
71 * @scan_res: The result from calling nand_scan_ident().
72*/
Linus Torvalds1da177e2005-04-16 15:20:36 -070073struct s3c2410_nand_mtd {
74 struct mtd_info mtd;
75 struct nand_chip chip;
76 struct s3c2410_nand_set *set;
77 struct s3c2410_nand_info *info;
78 int scan_res;
79};
80
Ben Dooks2c06a082006-06-27 14:35:46 +010081enum s3c_cpu_type {
82 TYPE_S3C2410,
83 TYPE_S3C2412,
84 TYPE_S3C2440,
85};
86
Jiri Pinkavaac497c12011-04-13 11:59:30 +020087enum s3c_nand_clk_state {
88 CLOCK_DISABLE = 0,
89 CLOCK_ENABLE,
90 CLOCK_SUSPEND,
91};
92
Linus Torvalds1da177e2005-04-16 15:20:36 -070093/* overview of the s3c2410 nand state */
94
Ben Dooks3db72152009-05-30 17:18:15 +010095/**
96 * struct s3c2410_nand_info - NAND controller state.
97 * @mtds: An array of MTD instances on this controoler.
98 * @platform: The platform data for this board.
99 * @device: The platform device we bound to.
Ben Dooks3db72152009-05-30 17:18:15 +0100100 * @clk: The clock resource for this controller.
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530101 * @regs: The area mapped for the hardware registers.
Ben Dooks3db72152009-05-30 17:18:15 +0100102 * @sel_reg: Pointer to the register controlling the NAND selection.
103 * @sel_bit: The bit in @sel_reg to select the NAND chip.
104 * @mtd_count: The number of MTDs created from this controller.
105 * @save_sel: The contents of @sel_reg to be saved over suspend.
106 * @clk_rate: The clock rate from @clk.
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200107 * @clk_state: The current clock state.
Ben Dooks3db72152009-05-30 17:18:15 +0100108 * @cpu_type: The exact type of this controller.
109 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110struct s3c2410_nand_info {
111 /* mtd info */
112 struct nand_hw_control controller;
113 struct s3c2410_nand_mtd *mtds;
114 struct s3c2410_platform_nand *platform;
115
116 /* device info */
117 struct device *device;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 struct clk *clk;
Ben Dooksfdf2fd52005-02-18 14:46:15 +0000119 void __iomem *regs;
Ben Dooks2c06a082006-06-27 14:35:46 +0100120 void __iomem *sel_reg;
121 int sel_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 int mtd_count;
Ben Dooks09160832008-04-15 11:36:18 +0100123 unsigned long save_sel;
Ben Dooks30821fe2008-07-15 11:58:31 +0100124 unsigned long clk_rate;
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200125 enum s3c_nand_clk_state clk_state;
Ben Dooks03680b12007-11-19 23:28:07 +0000126
Ben Dooks2c06a082006-06-27 14:35:46 +0100127 enum s3c_cpu_type cpu_type;
Ben Dooks30821fe2008-07-15 11:58:31 +0100128
129#ifdef CONFIG_CPU_FREQ
130 struct notifier_block freq_transition;
131#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132};
133
134/* conversion functions */
135
136static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
137{
138 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
139}
140
141static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
142{
143 return s3c2410_nand_mtd_toours(mtd)->info;
144}
145
Russell King3ae5eae2005-11-09 22:32:44 +0000146static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147{
Russell King3ae5eae2005-11-09 22:32:44 +0000148 return platform_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149}
150
Russell King3ae5eae2005-11-09 22:32:44 +0000151static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152{
Russell King3ae5eae2005-11-09 22:32:44 +0000153 return dev->dev.platform_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154}
155
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200156static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100157{
Sachin Kamata68c5ec2012-07-16 16:02:25 +0530158#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
159 return 1;
160#else
161 return 0;
162#endif
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100163}
164
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200165/**
166 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
167 * @info: The controller instance.
168 * @new_state: State to which clock should be set.
169 */
170static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
171 enum s3c_nand_clk_state new_state)
172{
173 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
174 return;
175
176 if (info->clk_state == CLOCK_ENABLE) {
177 if (new_state != CLOCK_ENABLE)
178 clk_disable(info->clk);
179 } else {
180 if (new_state == CLOCK_ENABLE)
181 clk_enable(info->clk);
182 }
183
184 info->clk_state = new_state;
185}
186
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187/* timing calculations */
188
Ben Dookscfd320f2005-10-20 22:22:58 +0100189#define NS_IN_KHZ 1000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
Ben Dooks3db72152009-05-30 17:18:15 +0100191/**
192 * s3c_nand_calc_rate - calculate timing data.
193 * @wanted: The cycle time in nanoseconds.
194 * @clk: The clock rate in kHz.
195 * @max: The maximum divider value.
196 *
197 * Calculate the timing value from the given parameters.
198 */
Ben Dooks2c06a082006-06-27 14:35:46 +0100199static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200{
201 int result;
202
Ben Dooks947391c2009-05-30 18:34:16 +0100203 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
205 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
206
207 if (result > max) {
Sachin Kamat92aeb5d2012-07-16 16:02:23 +0530208 pr_err("%d ns is too big for current clock rate %ld\n",
209 wanted, clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 return -1;
211 }
212
213 if (result < 1)
214 result = 1;
215
216 return result;
217}
218
Sachin Kamat54cd0202012-07-16 16:02:26 +0530219#define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220
221/* controller setup */
222
Ben Dooks3db72152009-05-30 17:18:15 +0100223/**
224 * s3c2410_nand_setrate - setup controller timing information.
225 * @info: The controller instance.
226 *
227 * Given the information supplied by the platform, calculate and set
228 * the necessary timing registers in the hardware to generate the
229 * necessary timing cycles to the hardware.
230 */
Ben Dooks30821fe2008-07-15 11:58:31 +0100231static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232{
Ben Dooks30821fe2008-07-15 11:58:31 +0100233 struct s3c2410_platform_nand *plat = info->platform;
Ben Dooks2c06a082006-06-27 14:35:46 +0100234 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
Ben Dookscfd320f2005-10-20 22:22:58 +0100235 int tacls, twrph0, twrph1;
Ben Dooks30821fe2008-07-15 11:58:31 +0100236 unsigned long clkrate = clk_get_rate(info->clk);
Nelson Castillo2612e522009-05-10 15:41:54 -0500237 unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
Ben Dooks30821fe2008-07-15 11:58:31 +0100238 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
240 /* calculate the timing information for the controller */
241
Ben Dooks30821fe2008-07-15 11:58:31 +0100242 info->clk_rate = clkrate;
Ben Dookscfd320f2005-10-20 22:22:58 +0100243 clkrate /= 1000; /* turn clock into kHz for ease of use */
244
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 if (plat != NULL) {
Ben Dooks2c06a082006-06-27 14:35:46 +0100246 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
247 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
248 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249 } else {
250 /* default timings */
Ben Dooks2c06a082006-06-27 14:35:46 +0100251 tacls = tacls_max;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252 twrph0 = 8;
253 twrph1 = 8;
254 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000255
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
Ben Dooks99974c62006-06-21 15:43:05 +0100257 dev_err(info->device, "cannot get suitable timings\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 return -EINVAL;
259 }
260
Ben Dooks99974c62006-06-21 15:43:05 +0100261 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
Sachin Kamat54cd0202012-07-16 16:02:26 +0530262 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
263 twrph1, to_ns(twrph1, clkrate));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
Ben Dooks30821fe2008-07-15 11:58:31 +0100265 switch (info->cpu_type) {
266 case TYPE_S3C2410:
267 mask = (S3C2410_NFCONF_TACLS(3) |
268 S3C2410_NFCONF_TWRPH0(7) |
269 S3C2410_NFCONF_TWRPH1(7));
270 set = S3C2410_NFCONF_EN;
271 set |= S3C2410_NFCONF_TACLS(tacls - 1);
272 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
273 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
274 break;
275
276 case TYPE_S3C2440:
277 case TYPE_S3C2412:
Peter Korsgaarda755a382009-06-03 13:46:54 +0200278 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
279 S3C2440_NFCONF_TWRPH0(7) |
280 S3C2440_NFCONF_TWRPH1(7));
Ben Dooks30821fe2008-07-15 11:58:31 +0100281
282 set = S3C2440_NFCONF_TACLS(tacls - 1);
283 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
284 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
285 break;
286
287 default:
Ben Dooks30821fe2008-07-15 11:58:31 +0100288 BUG();
289 }
290
Ben Dooks30821fe2008-07-15 11:58:31 +0100291 local_irq_save(flags);
292
293 cfg = readl(info->regs + S3C2410_NFCONF);
294 cfg &= ~mask;
295 cfg |= set;
296 writel(cfg, info->regs + S3C2410_NFCONF);
297
298 local_irq_restore(flags);
299
Andy Greenae7304e2009-05-10 15:42:02 -0500300 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
301
Ben Dooks30821fe2008-07-15 11:58:31 +0100302 return 0;
303}
304
Ben Dooks3db72152009-05-30 17:18:15 +0100305/**
306 * s3c2410_nand_inithw - basic hardware initialisation
307 * @info: The hardware state.
308 *
309 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
310 * to setup the hardware access speeds and set the controller to be enabled.
311*/
Ben Dooks30821fe2008-07-15 11:58:31 +0100312static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
313{
314 int ret;
315
316 ret = s3c2410_nand_setrate(info);
317 if (ret < 0)
318 return ret;
319
Sachin Kamat54cd0202012-07-16 16:02:26 +0530320 switch (info->cpu_type) {
321 case TYPE_S3C2410:
Ben Dooks30821fe2008-07-15 11:58:31 +0100322 default:
Ben Dooks2c06a082006-06-27 14:35:46 +0100323 break;
324
Sachin Kamat54cd0202012-07-16 16:02:26 +0530325 case TYPE_S3C2440:
326 case TYPE_S3C2412:
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100327 /* enable the controller and de-assert nFCE */
328
Ben Dooks2c06a082006-06-27 14:35:46 +0100329 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100330 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 return 0;
333}
334
Ben Dooks3db72152009-05-30 17:18:15 +0100335/**
336 * s3c2410_nand_select_chip - select the given nand chip
337 * @mtd: The MTD instance for this chip.
338 * @chip: The chip number.
339 *
340 * This is called by the MTD layer to either select a given chip for the
341 * @mtd instance, or to indicate that the access has finished and the
342 * chip can be de-selected.
343 *
344 * The routine ensures that the nFCE line is correctly setup, and any
345 * platform specific selection code is called to route nFCE to the specific
346 * chip.
347 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
349{
350 struct s3c2410_nand_info *info;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000351 struct s3c2410_nand_mtd *nmtd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 struct nand_chip *this = mtd->priv;
353 unsigned long cur;
354
355 nmtd = this->priv;
356 info = nmtd->info;
357
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200358 if (chip != -1)
359 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100360
Ben Dooks2c06a082006-06-27 14:35:46 +0100361 cur = readl(info->sel_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362
363 if (chip == -1) {
Ben Dooks2c06a082006-06-27 14:35:46 +0100364 cur |= info->sel_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 } else {
Ben Dooksfb8d82a2005-07-06 21:05:10 +0100366 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
Ben Dooks99974c62006-06-21 15:43:05 +0100367 dev_err(info->device, "invalid chip %d\n", chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368 return;
369 }
370
371 if (info->platform != NULL) {
372 if (info->platform->select_chip != NULL)
David Woodhousee0c7d762006-05-13 18:07:53 +0100373 (info->platform->select_chip) (nmtd->set, chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 }
375
Ben Dooks2c06a082006-06-27 14:35:46 +0100376 cur &= ~info->sel_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 }
378
Ben Dooks2c06a082006-06-27 14:35:46 +0100379 writel(cur, info->sel_reg);
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100380
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200381 if (chip == -1)
382 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383}
384
Ben Dooksad3b5fb2006-06-19 09:43:23 +0100385/* s3c2410_nand_hwcontrol
Ben Dooksa4f957f2005-06-20 12:48:25 +0100386 *
Ben Dooksad3b5fb2006-06-19 09:43:23 +0100387 * Issue command and address cycles to the chip
Ben Dooksa4f957f2005-06-20 12:48:25 +0100388*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200390static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
David Woodhousef9068872006-06-10 00:53:16 +0100391 unsigned int ctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392{
393 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
David Woodhousec9ac5972006-11-30 08:17:38 +0000394
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200395 if (cmd == NAND_CMD_NONE)
396 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397
David Woodhousef9068872006-06-10 00:53:16 +0100398 if (ctrl & NAND_CLE)
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200399 writeb(cmd, info->regs + S3C2410_NFCMD);
400 else
401 writeb(cmd, info->regs + S3C2410_NFADDR);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100402}
403
404/* command and control functions */
405
David Woodhousef9068872006-06-10 00:53:16 +0100406static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
407 unsigned int ctrl)
Ben Dooksa4f957f2005-06-20 12:48:25 +0100408{
409 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100410
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200411 if (cmd == NAND_CMD_NONE)
412 return;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100413
David Woodhousef9068872006-06-10 00:53:16 +0100414 if (ctrl & NAND_CLE)
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200415 writeb(cmd, info->regs + S3C2440_NFCMD);
416 else
417 writeb(cmd, info->regs + S3C2440_NFADDR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418}
419
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420/* s3c2410_nand_devready()
421 *
422 * returns 0 if the nand is busy, 1 if it is ready
423*/
424
425static int s3c2410_nand_devready(struct mtd_info *mtd)
426{
427 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
429}
430
Ben Dooks2c06a082006-06-27 14:35:46 +0100431static int s3c2440_nand_devready(struct mtd_info *mtd)
432{
433 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
434 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
435}
436
437static int s3c2412_nand_devready(struct mtd_info *mtd)
438{
439 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
440 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
441}
442
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443/* ECC handling functions */
444
Sachin Kamat19da4152012-08-21 14:24:10 +0530445#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
Ben Dooks2c06a082006-06-27 14:35:46 +0100446static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
447 u_char *read_ecc, u_char *calc_ecc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448{
Ben Dooksa2593242007-02-02 16:59:33 +0000449 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
450 unsigned int diff0, diff1, diff2;
451 unsigned int bit, byte;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452
Ben Dooksa2593242007-02-02 16:59:33 +0000453 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454
Ben Dooksa2593242007-02-02 16:59:33 +0000455 diff0 = read_ecc[0] ^ calc_ecc[0];
456 diff1 = read_ecc[1] ^ calc_ecc[1];
457 diff2 = read_ecc[2] ^ calc_ecc[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458
Andy Shevchenko13e85972012-08-02 16:06:47 +0300459 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
460 __func__, 3, read_ecc, 3, calc_ecc,
Ben Dooksa2593242007-02-02 16:59:33 +0000461 diff0, diff1, diff2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462
Ben Dooksa2593242007-02-02 16:59:33 +0000463 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
464 return 0; /* ECC is ok */
465
Ben Dooksc45c6c62008-04-15 11:36:20 +0100466 /* sometimes people do not think about using the ECC, so check
467 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
468 * the error, on the assumption that this is an un-eccd page.
469 */
470 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
471 && info->platform->ignore_unset_ecc)
472 return 0;
473
Ben Dooksa2593242007-02-02 16:59:33 +0000474 /* Can we correct this ECC (ie, one row and column change).
475 * Note, this is similar to the 256 error code on smartmedia */
476
477 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
478 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
479 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
480 /* calculate the bit position of the error */
481
Matt Reimerd0bf3792007-10-18 18:02:43 -0700482 bit = ((diff2 >> 3) & 1) |
483 ((diff2 >> 4) & 2) |
484 ((diff2 >> 5) & 4);
Ben Dooksa2593242007-02-02 16:59:33 +0000485
486 /* calculate the byte position of the error */
487
Matt Reimerd0bf3792007-10-18 18:02:43 -0700488 byte = ((diff2 << 7) & 0x100) |
489 ((diff1 << 0) & 0x80) |
490 ((diff1 << 1) & 0x40) |
491 ((diff1 << 2) & 0x20) |
492 ((diff1 << 3) & 0x10) |
493 ((diff0 >> 4) & 0x08) |
494 ((diff0 >> 3) & 0x04) |
495 ((diff0 >> 2) & 0x02) |
496 ((diff0 >> 1) & 0x01);
Ben Dooksa2593242007-02-02 16:59:33 +0000497
498 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
499 bit, byte);
500
501 dat[byte] ^= (1 << bit);
502 return 1;
503 }
504
505 /* if there is only one bit difference in the ECC, then
506 * one of only a row or column parity has changed, which
507 * means the error is most probably in the ECC itself */
508
509 diff0 |= (diff1 << 8);
510 diff0 |= (diff2 << 16);
511
512 if ((diff0 & ~(1<<fls(diff0))) == 0)
513 return 1;
514
Matt Reimer4fac9f62007-10-18 18:02:44 -0700515 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516}
517
Ben Dooksa4f957f2005-06-20 12:48:25 +0100518/* ECC functions
519 *
520 * These allow the s3c2410 and s3c2440 to use the controller's ECC
521 * generator block to ECC the data as it passes through]
522*/
523
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
525{
526 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
527 unsigned long ctrl;
528
529 ctrl = readl(info->regs + S3C2410_NFCONF);
530 ctrl |= S3C2410_NFCONF_INITECC;
531 writel(ctrl, info->regs + S3C2410_NFCONF);
532}
533
Matthieu CASTET4f659922007-02-13 12:30:38 +0100534static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
535{
536 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
537 unsigned long ctrl;
538
539 ctrl = readl(info->regs + S3C2440_NFCONT);
Sachin Kamatf938bc52012-08-21 10:21:15 +0530540 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
541 info->regs + S3C2440_NFCONT);
Matthieu CASTET4f659922007-02-13 12:30:38 +0100542}
543
Ben Dooksa4f957f2005-06-20 12:48:25 +0100544static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
545{
546 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
547 unsigned long ctrl;
548
549 ctrl = readl(info->regs + S3C2440_NFCONT);
550 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
551}
552
Sachin Kamatf938bc52012-08-21 10:21:15 +0530553static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
554 u_char *ecc_code)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555{
556 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
557
558 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
559 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
560 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
561
Andy Shevchenko13e85972012-08-02 16:06:47 +0300562 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563
564 return 0;
565}
566
Sachin Kamatf938bc52012-08-21 10:21:15 +0530567static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
568 u_char *ecc_code)
Matthieu CASTET4f659922007-02-13 12:30:38 +0100569{
570 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
571 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
572
573 ecc_code[0] = ecc;
574 ecc_code[1] = ecc >> 8;
575 ecc_code[2] = ecc >> 16;
576
Andy Shevchenko13e85972012-08-02 16:06:47 +0300577 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
Matthieu CASTET4f659922007-02-13 12:30:38 +0100578
579 return 0;
580}
581
Sachin Kamatf938bc52012-08-21 10:21:15 +0530582static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
583 u_char *ecc_code)
Ben Dooksa4f957f2005-06-20 12:48:25 +0100584{
585 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
586 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
587
588 ecc_code[0] = ecc;
589 ecc_code[1] = ecc >> 8;
590 ecc_code[2] = ecc >> 16;
591
Ben Dooks71d54f32008-04-15 11:36:19 +0100592 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100593
594 return 0;
595}
Sachin Kamat19da4152012-08-21 14:24:10 +0530596#endif
Ben Dooksa4f957f2005-06-20 12:48:25 +0100597
Ben Dooksa4f957f2005-06-20 12:48:25 +0100598/* over-ride the standard functions for a little more speed. We can
599 * use read/write block to move the data buffers to/from the controller
600*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601
602static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
603{
604 struct nand_chip *this = mtd->priv;
605 readsb(this->IO_ADDR_R, buf, len);
606}
607
Matt Reimerb773bb22007-10-18 17:43:07 -0700608static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
609{
610 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
Ben Dooksdea2aa62009-05-30 18:30:18 +0100611
612 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
613
614 /* cleanup if we've got less than a word to do */
615 if (len & 3) {
616 buf += len & ~3;
617
618 for (; len & 3; len--)
619 *buf++ = readb(info->regs + S3C2440_NFDATA);
620 }
Matt Reimerb773bb22007-10-18 17:43:07 -0700621}
622
Sachin Kamatf938bc52012-08-21 10:21:15 +0530623static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
624 int len)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625{
626 struct nand_chip *this = mtd->priv;
627 writesb(this->IO_ADDR_W, buf, len);
628}
629
Sachin Kamatf938bc52012-08-21 10:21:15 +0530630static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
631 int len)
Matt Reimerb773bb22007-10-18 17:43:07 -0700632{
633 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
Ben Dooksdea2aa62009-05-30 18:30:18 +0100634
635 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
636
637 /* cleanup any fractional write */
638 if (len & 3) {
639 buf += len & ~3;
640
641 for (; len & 3; len--, buf++)
642 writeb(*buf, info->regs + S3C2440_NFDATA);
643 }
Matt Reimerb773bb22007-10-18 17:43:07 -0700644}
645
Ben Dooks30821fe2008-07-15 11:58:31 +0100646/* cpufreq driver support */
647
648#ifdef CONFIG_CPU_FREQ
649
650static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
651 unsigned long val, void *data)
652{
653 struct s3c2410_nand_info *info;
654 unsigned long newclk;
655
656 info = container_of(nb, struct s3c2410_nand_info, freq_transition);
657 newclk = clk_get_rate(info->clk);
658
659 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
660 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
661 s3c2410_nand_setrate(info);
662 }
663
664 return 0;
665}
666
667static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
668{
669 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
670
671 return cpufreq_register_notifier(&info->freq_transition,
672 CPUFREQ_TRANSITION_NOTIFIER);
673}
674
Sachin Kamatf938bc52012-08-21 10:21:15 +0530675static inline void
676s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
Ben Dooks30821fe2008-07-15 11:58:31 +0100677{
678 cpufreq_unregister_notifier(&info->freq_transition,
679 CPUFREQ_TRANSITION_NOTIFIER);
680}
681
682#else
683static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
684{
685 return 0;
686}
687
Sachin Kamatf938bc52012-08-21 10:21:15 +0530688static inline void
689s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
Ben Dooks30821fe2008-07-15 11:58:31 +0100690{
691}
692#endif
693
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694/* device management functions */
695
Ben Dooksec0482e2009-05-30 16:55:29 +0100696static int s3c24xx_nand_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697{
Russell King3ae5eae2005-11-09 22:32:44 +0000698 struct s3c2410_nand_info *info = to_nand_info(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699
Russell King3ae5eae2005-11-09 22:32:44 +0000700 platform_set_drvdata(pdev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000702 if (info == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 return 0;
704
Ben Dooks30821fe2008-07-15 11:58:31 +0100705 s3c2410_nand_cpufreq_deregister(info);
706
707 /* Release all our mtds and their partitions, then go through
708 * freeing the resources used
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709 */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000710
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 if (info->mtds != NULL) {
712 struct s3c2410_nand_mtd *ptr = info->mtds;
713 int mtdno;
714
715 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
716 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
717 nand_release(&ptr->mtd);
718 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 }
720
721 /* free the common resources */
722
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530723 if (!IS_ERR(info->clk))
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200724 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725
726 return 0;
727}
728
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
730 struct s3c2410_nand_mtd *mtd,
731 struct s3c2410_nand_set *set)
732{
Dmitry Eremin-Solenikov599501a2011-06-02 18:01:02 +0400733 if (set)
734 mtd->mtd.name = set->name;
Andy Greened27f022009-05-10 15:42:09 -0500735
Artem Bityutskiy42d7fbe2012-03-09 19:24:26 +0200736 return mtd_device_parse_register(&mtd->mtd, NULL, NULL,
737 set->partitions, set->nr_partitions);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739
Ben Dooks3db72152009-05-30 17:18:15 +0100740/**
741 * s3c2410_nand_init_chip - initialise a single instance of an chip
742 * @info: The base NAND controller the chip is on.
743 * @nmtd: The new controller MTD instance to fill in.
744 * @set: The information passed from the board specific platform data.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 *
Ben Dooks3db72152009-05-30 17:18:15 +0100746 * Initialise the given @nmtd from the information in @info and @set. This
747 * readies the structure for use with the MTD layer functions by ensuring
748 * all pointers are setup and the necessary control routines selected.
749 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
751 struct s3c2410_nand_mtd *nmtd,
752 struct s3c2410_nand_set *set)
753{
754 struct nand_chip *chip = &nmtd->chip;
Ben Dooks2c06a082006-06-27 14:35:46 +0100755 void __iomem *regs = info->regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 chip->write_buf = s3c2410_nand_write_buf;
758 chip->read_buf = s3c2410_nand_read_buf;
759 chip->select_chip = s3c2410_nand_select_chip;
760 chip->chip_delay = 50;
761 chip->priv = nmtd;
Ben Dooks74218fe2009-11-02 18:12:51 +0000762 chip->options = set->options;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 chip->controller = &info->controller;
764
Ben Dooks2c06a082006-06-27 14:35:46 +0100765 switch (info->cpu_type) {
766 case TYPE_S3C2410:
767 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
768 info->sel_reg = regs + S3C2410_NFCONF;
769 info->sel_bit = S3C2410_NFCONF_nFCE;
770 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
771 chip->dev_ready = s3c2410_nand_devready;
772 break;
773
774 case TYPE_S3C2440:
775 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
776 info->sel_reg = regs + S3C2440_NFCONT;
777 info->sel_bit = S3C2440_NFCONT_nFCE;
778 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
779 chip->dev_ready = s3c2440_nand_devready;
Matt Reimerb773bb22007-10-18 17:43:07 -0700780 chip->read_buf = s3c2440_nand_read_buf;
781 chip->write_buf = s3c2440_nand_write_buf;
Ben Dooks2c06a082006-06-27 14:35:46 +0100782 break;
783
784 case TYPE_S3C2412:
785 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
786 info->sel_reg = regs + S3C2440_NFCONT;
787 info->sel_bit = S3C2412_NFCONT_nFCE0;
788 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
789 chip->dev_ready = s3c2412_nand_devready;
790
791 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
792 dev_info(info->device, "System booted from NAND\n");
793
794 break;
Sachin Kamat54cd0202012-07-16 16:02:26 +0530795 }
Ben Dooks2c06a082006-06-27 14:35:46 +0100796
797 chip->IO_ADDR_R = chip->IO_ADDR_W;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100798
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 nmtd->info = info;
800 nmtd->mtd.priv = chip;
David Woodhouse552d9202006-05-14 01:20:46 +0100801 nmtd->mtd.owner = THIS_MODULE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 nmtd->set = set;
803
Sachin Kamata68c5ec2012-07-16 16:02:25 +0530804#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
805 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
806 chip->ecc.correct = s3c2410_nand_correct_data;
807 chip->ecc.mode = NAND_ECC_HW;
808 chip->ecc.strength = 1;
809
810 switch (info->cpu_type) {
811 case TYPE_S3C2410:
812 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200813 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
Sachin Kamata68c5ec2012-07-16 16:02:25 +0530814 break;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100815
Sachin Kamata68c5ec2012-07-16 16:02:25 +0530816 case TYPE_S3C2412:
817 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
818 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
819 break;
Ben Dooks2c06a082006-06-27 14:35:46 +0100820
Sachin Kamata68c5ec2012-07-16 16:02:25 +0530821 case TYPE_S3C2440:
822 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
823 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
824 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 }
Sachin Kamata68c5ec2012-07-16 16:02:25 +0530826#else
827 chip->ecc.mode = NAND_ECC_SOFT;
828#endif
Ben Dooks1c21ab62008-04-15 11:36:21 +0100829
830 if (set->ecc_layout != NULL)
831 chip->ecc.layout = set->ecc_layout;
Ben Dooks37e5ffa2008-04-15 11:36:22 +0100832
833 if (set->disable_ecc)
834 chip->ecc.mode = NAND_ECC_NONE;
Andy Green8c3e8432009-05-10 15:41:25 -0500835
836 switch (chip->ecc.mode) {
837 case NAND_ECC_NONE:
838 dev_info(info->device, "NAND ECC disabled\n");
839 break;
840 case NAND_ECC_SOFT:
841 dev_info(info->device, "NAND soft ECC\n");
842 break;
843 case NAND_ECC_HW:
844 dev_info(info->device, "NAND hardware ECC\n");
845 break;
846 default:
847 dev_info(info->device, "NAND ECC UNKNOWN\n");
848 break;
849 }
Michel Pollet9db41f92009-05-13 16:54:14 +0100850
851 /* If you use u-boot BBT creation code, specifying this flag will
852 * let the kernel fish out the BBT from the NAND, and also skip the
853 * full NAND scan that can take 1/2s or so. Little things... */
Brian Norrisa40f7342011-05-31 16:31:22 -0700854 if (set->flash_bbt) {
Brian Norrisbb9ebd42011-05-31 16:31:23 -0700855 chip->bbt_options |= NAND_BBT_USE_FLASH;
Brian Norrisa40f7342011-05-31 16:31:22 -0700856 chip->options |= NAND_SKIP_BBTSCAN;
857 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858}
859
Ben Dooks3db72152009-05-30 17:18:15 +0100860/**
861 * s3c2410_nand_update_chip - post probe update
862 * @info: The controller instance.
863 * @nmtd: The driver version of the MTD instance.
Ben Dooks71d54f32008-04-15 11:36:19 +0100864 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200865 * This routine is called after the chip probe has successfully completed
Ben Dooks3db72152009-05-30 17:18:15 +0100866 * and the relevant per-chip information updated. This call ensure that
867 * we update the internal state accordingly.
868 *
869 * The internal state is currently limited to the ECC state information.
870*/
Ben Dooks71d54f32008-04-15 11:36:19 +0100871static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
872 struct s3c2410_nand_mtd *nmtd)
873{
874 struct nand_chip *chip = &nmtd->chip;
875
Ben Dooks451d3392008-05-20 17:32:14 +0100876 dev_dbg(info->device, "chip %p => page shift %d\n",
877 chip, chip->page_shift);
Ben Dooks71d54f32008-04-15 11:36:19 +0100878
Andy Green8c3e8432009-05-10 15:41:25 -0500879 if (chip->ecc.mode != NAND_ECC_HW)
880 return;
881
Ben Dooks71d54f32008-04-15 11:36:19 +0100882 /* change the behaviour depending on wether we are using
883 * the large or small page nand device */
884
Andy Green8c3e8432009-05-10 15:41:25 -0500885 if (chip->page_shift > 10) {
886 chip->ecc.size = 256;
887 chip->ecc.bytes = 3;
888 } else {
889 chip->ecc.size = 512;
890 chip->ecc.bytes = 3;
891 chip->ecc.layout = &nand_hw_eccoob;
Ben Dooks71d54f32008-04-15 11:36:19 +0100892 }
893}
894
Ben Dooksec0482e2009-05-30 16:55:29 +0100895/* s3c24xx_nand_probe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 *
897 * called by device layer when it finds a device matching
898 * one our driver can handled. This code checks to see if
899 * it can allocate all necessary resources then calls the
900 * nand layer to look for devices
901*/
Ben Dooksec0482e2009-05-30 16:55:29 +0100902static int s3c24xx_nand_probe(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903{
Russell King3ae5eae2005-11-09 22:32:44 +0000904 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
Sachin Kamat54cd0202012-07-16 16:02:26 +0530905 enum s3c_cpu_type cpu_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906 struct s3c2410_nand_info *info;
907 struct s3c2410_nand_mtd *nmtd;
908 struct s3c2410_nand_set *sets;
909 struct resource *res;
910 int err = 0;
911 int size;
912 int nr_sets;
913 int setno;
914
Ben Dooksec0482e2009-05-30 16:55:29 +0100915 cpu_type = platform_get_device_id(pdev)->driver_data;
916
Russell King3ae5eae2005-11-09 22:32:44 +0000917 pr_debug("s3c2410_nand_probe(%p)\n", pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530919 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 if (info == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000921 dev_err(&pdev->dev, "no memory for flash info\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 err = -ENOMEM;
923 goto exit_error;
924 }
925
Russell King3ae5eae2005-11-09 22:32:44 +0000926 platform_set_drvdata(pdev, info);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927
928 spin_lock_init(&info->controller.lock);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100929 init_waitqueue_head(&info->controller.wq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930
931 /* get the clock source and enable it */
932
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530933 info->clk = devm_clk_get(&pdev->dev, "nand");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 if (IS_ERR(info->clk)) {
Joe Perches898eb712007-10-18 03:06:30 -0700935 dev_err(&pdev->dev, "failed to get clock\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936 err = -ENOENT;
937 goto exit_error;
938 }
939
Jiri Pinkavaac497c12011-04-13 11:59:30 +0200940 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941
942 /* allocate and map the resource */
943
Ben Dooksa4f957f2005-06-20 12:48:25 +0100944 /* currently we assume we have the one resource */
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530945 res = pdev->resource;
H Hartley Sweetenfc161c42009-12-14 16:56:22 -0500946 size = resource_size(res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530948 info->device = &pdev->dev;
949 info->platform = plat;
950 info->cpu_type = cpu_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530952 info->regs = devm_request_and_ioremap(&pdev->dev, res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700953 if (info->regs == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000954 dev_err(&pdev->dev, "cannot reserve register region\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 err = -EIO;
956 goto exit_error;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000957 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958
Russell King3ae5eae2005-11-09 22:32:44 +0000959 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960
961 /* initialise the hardware */
962
Ben Dooks30821fe2008-07-15 11:58:31 +0100963 err = s3c2410_nand_inithw(info);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964 if (err != 0)
965 goto exit_error;
966
967 sets = (plat != NULL) ? plat->sets : NULL;
968 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
969
970 info->mtd_count = nr_sets;
971
972 /* allocate our information */
973
974 size = nr_sets * sizeof(*info->mtds);
Sachin Kamat6f32a3e2012-08-21 14:24:09 +0530975 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 if (info->mtds == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000977 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978 err = -ENOMEM;
979 goto exit_error;
980 }
981
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 /* initialise all possible chips */
983
984 nmtd = info->mtds;
985
986 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
Sachin Kamatf938bc52012-08-21 10:21:15 +0530987 pr_debug("initialising set %d (%p, info %p)\n",
988 setno, nmtd, info);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000989
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 s3c2410_nand_init_chip(info, nmtd, sets);
991
Ben Dooks71d54f32008-04-15 11:36:19 +0100992 nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
David Woodhouse5e81e882010-02-26 18:32:56 +0000993 (sets) ? sets->nr_chips : 1,
994 NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995
996 if (nmtd->scan_res == 0) {
Ben Dooks71d54f32008-04-15 11:36:19 +0100997 s3c2410_nand_update_chip(info, nmtd);
998 nand_scan_tail(&nmtd->mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 s3c2410_nand_add_partition(info, nmtd, sets);
1000 }
1001
1002 if (sets != NULL)
1003 sets++;
1004 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +00001005
Ben Dooks30821fe2008-07-15 11:58:31 +01001006 err = s3c2410_nand_cpufreq_register(info);
1007 if (err < 0) {
1008 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1009 goto exit_error;
1010 }
1011
Jiri Pinkavaac497c12011-04-13 11:59:30 +02001012 if (allow_clk_suspend(info)) {
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001013 dev_info(&pdev->dev, "clock idle support enabled\n");
Jiri Pinkavaac497c12011-04-13 11:59:30 +02001014 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001015 }
1016
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017 pr_debug("initialised ok\n");
1018 return 0;
1019
1020 exit_error:
Ben Dooksec0482e2009-05-30 16:55:29 +01001021 s3c24xx_nand_remove(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022
1023 if (err == 0)
1024 err = -EINVAL;
1025 return err;
1026}
1027
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001028/* PM Support */
1029#ifdef CONFIG_PM
1030
1031static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1032{
1033 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1034
1035 if (info) {
Ben Dooks09160832008-04-15 11:36:18 +01001036 info->save_sel = readl(info->sel_reg);
Ben Dooks03680b12007-11-19 23:28:07 +00001037
1038 /* For the moment, we must ensure nFCE is high during
1039 * the time we are suspended. This really should be
1040 * handled by suspending the MTDs we are using, but
1041 * that is currently not the case. */
1042
Ben Dooks09160832008-04-15 11:36:18 +01001043 writel(info->save_sel | info->sel_bit, info->sel_reg);
Ben Dooks03680b12007-11-19 23:28:07 +00001044
Jiri Pinkavaac497c12011-04-13 11:59:30 +02001045 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001046 }
1047
1048 return 0;
1049}
1050
1051static int s3c24xx_nand_resume(struct platform_device *dev)
1052{
1053 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
Ben Dooks09160832008-04-15 11:36:18 +01001054 unsigned long sel;
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001055
1056 if (info) {
Jiri Pinkavaac497c12011-04-13 11:59:30 +02001057 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
Ben Dooks30821fe2008-07-15 11:58:31 +01001058 s3c2410_nand_inithw(info);
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001059
Ben Dooks03680b12007-11-19 23:28:07 +00001060 /* Restore the state of the nFCE line. */
1061
Ben Dooks09160832008-04-15 11:36:18 +01001062 sel = readl(info->sel_reg);
1063 sel &= ~info->sel_bit;
1064 sel |= info->save_sel & info->sel_bit;
1065 writel(sel, info->sel_reg);
Ben Dooks03680b12007-11-19 23:28:07 +00001066
Jiri Pinkavaac497c12011-04-13 11:59:30 +02001067 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
Ben Dooksd1fef3c2006-06-19 09:29:38 +01001068 }
1069
1070 return 0;
1071}
1072
1073#else
1074#define s3c24xx_nand_suspend NULL
1075#define s3c24xx_nand_resume NULL
1076#endif
1077
Ben Dooksa4f957f2005-06-20 12:48:25 +01001078/* driver device registration */
1079
Ben Dooksec0482e2009-05-30 16:55:29 +01001080static struct platform_device_id s3c24xx_driver_ids[] = {
1081 {
1082 .name = "s3c2410-nand",
1083 .driver_data = TYPE_S3C2410,
1084 }, {
1085 .name = "s3c2440-nand",
1086 .driver_data = TYPE_S3C2440,
1087 }, {
1088 .name = "s3c2412-nand",
1089 .driver_data = TYPE_S3C2412,
Peter Korsgaard9dbc0902009-06-07 06:04:23 -07001090 }, {
1091 .name = "s3c6400-nand",
1092 .driver_data = TYPE_S3C2412, /* compatible with 2412 */
Russell King3ae5eae2005-11-09 22:32:44 +00001093 },
Ben Dooksec0482e2009-05-30 16:55:29 +01001094 { }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095};
1096
Ben Dooksec0482e2009-05-30 16:55:29 +01001097MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
Ben Dooksa4f957f2005-06-20 12:48:25 +01001098
Ben Dooksec0482e2009-05-30 16:55:29 +01001099static struct platform_driver s3c24xx_nand_driver = {
1100 .probe = s3c24xx_nand_probe,
1101 .remove = s3c24xx_nand_remove,
Ben Dooks2c06a082006-06-27 14:35:46 +01001102 .suspend = s3c24xx_nand_suspend,
1103 .resume = s3c24xx_nand_resume,
Ben Dooksec0482e2009-05-30 16:55:29 +01001104 .id_table = s3c24xx_driver_ids,
Ben Dooks2c06a082006-06-27 14:35:46 +01001105 .driver = {
Ben Dooksec0482e2009-05-30 16:55:29 +01001106 .name = "s3c24xx-nand",
Ben Dooks2c06a082006-06-27 14:35:46 +01001107 .owner = THIS_MODULE,
1108 },
1109};
1110
Sachin Kamat056fcab2012-07-16 16:02:22 +05301111module_platform_driver(s3c24xx_nand_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112
1113MODULE_LICENSE("GPL");
1114MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
Ben Dooksa4f957f2005-06-20 12:48:25 +01001115MODULE_DESCRIPTION("S3C24XX MTD NAND driver");