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Maxime Ripardb2ac5d72012-11-12 15:07:50 +01001/*
2 * Allwinner A1X SoCs timer handling.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqreturn.h>
Maxime Ripard137c6b32013-07-16 16:45:37 +020022#include <linux/sched_clock.h>
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010023#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010026
Maxime Ripard04981732013-03-10 17:03:46 +010027#define TIMER_IRQ_EN_REG 0x00
Maxime Ripard40777642013-07-16 16:45:37 +020028#define TIMER_IRQ_EN(val) BIT(val)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010029#define TIMER_IRQ_ST_REG 0x04
Maxime Ripard04981732013-03-10 17:03:46 +010030#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
Maxime Ripard40777642013-07-16 16:45:37 +020031#define TIMER_CTL_ENABLE BIT(0)
Maxime Ripard9eded232013-07-16 16:45:37 +020032#define TIMER_CTL_RELOAD BIT(1)
Maxime Riparda2c49e72013-07-16 16:45:38 +020033#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
34#define TIMER_CTL_CLK_SRC_OSC24M (1)
35#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
Maxime Ripard40777642013-07-16 16:45:37 +020036#define TIMER_CTL_ONESHOT BIT(7)
Maxime Ripardbb008b92013-07-16 16:45:37 +020037#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
38#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010039
Maxime Ripard12e14802013-10-14 21:07:47 +020040#define TIMER_SYNC_TICKS 3
41
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010042static void __iomem *timer_base;
Maxime Ripard7e141832013-07-16 16:45:38 +020043static u32 ticks_per_jiffy;
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010044
Maxime Ripard63d88f12013-07-16 16:45:38 +020045/*
46 * When we disable a timer, we need to wait at least for 2 cycles of
47 * the timer source clock. We will use for that the clocksource timer
48 * that is already setup and runs at the same frequency than the other
49 * timers, and we never will be disabled.
50 */
51static void sun4i_clkevt_sync(void)
52{
53 u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
54
Maxime Ripard12e14802013-10-14 21:07:47 +020055 while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
Maxime Ripard63d88f12013-07-16 16:45:38 +020056 cpu_relax();
57}
58
Maxime Ripard96651a02013-07-16 16:45:38 +020059static void sun4i_clkevt_time_stop(u8 timer)
60{
61 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
63 sun4i_clkevt_sync();
64}
65
66static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
67{
68 writel(delay, timer_base + TIMER_INTVAL_REG(timer));
69}
70
71static void sun4i_clkevt_time_start(u8 timer, bool periodic)
72{
73 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
74
75 if (periodic)
76 val &= ~TIMER_CTL_ONESHOT;
77 else
78 val |= TIMER_CTL_ONESHOT;
79
Maxime Ripard7e141832013-07-16 16:45:38 +020080 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
81 timer_base + TIMER_CTL_REG(timer));
Maxime Ripard96651a02013-07-16 16:45:38 +020082}
83
Viresh Kumar6de6c972015-06-18 16:24:37 +053084static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010085{
Viresh Kumar6de6c972015-06-18 16:24:37 +053086 sun4i_clkevt_time_stop(0);
87 return 0;
88}
89
90static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
91{
92 sun4i_clkevt_time_stop(0);
93 sun4i_clkevt_time_start(0, false);
94 return 0;
95}
96
97static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
98{
99 sun4i_clkevt_time_stop(0);
100 sun4i_clkevt_time_setup(0, ticks_per_jiffy);
101 sun4i_clkevt_time_start(0, true);
102 return 0;
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100103}
104
Maxime Ripard119fd632013-03-24 11:49:25 +0100105static int sun4i_clkevt_next_event(unsigned long evt,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100106 struct clock_event_device *unused)
107{
Maxime Ripard96651a02013-07-16 16:45:38 +0200108 sun4i_clkevt_time_stop(0);
Maxime Ripard12e14802013-10-14 21:07:47 +0200109 sun4i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
Maxime Ripard96651a02013-07-16 16:45:38 +0200110 sun4i_clkevt_time_start(0, false);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100111
112 return 0;
113}
114
Maxime Ripard119fd632013-03-24 11:49:25 +0100115static struct clock_event_device sun4i_clockevent = {
116 .name = "sun4i_tick",
Maxime Ripard5df9aff2013-11-07 12:01:48 +0100117 .rating = 350,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100118 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
Viresh Kumar6de6c972015-06-18 16:24:37 +0530119 .set_state_shutdown = sun4i_clkevt_shutdown,
120 .set_state_periodic = sun4i_clkevt_set_periodic,
121 .set_state_oneshot = sun4i_clkevt_set_oneshot,
122 .tick_resume = sun4i_clkevt_shutdown,
Maxime Ripard119fd632013-03-24 11:49:25 +0100123 .set_next_event = sun4i_clkevt_next_event,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100124};
125
Chen-Yu Tsaib53e7d02016-08-25 14:26:59 +0800126static void sun4i_timer_clear_interrupt(void)
127{
128 writel(TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_ST_REG);
129}
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100130
Maxime Ripard119fd632013-03-24 11:49:25 +0100131static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100132{
133 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
134
Chen-Yu Tsaib53e7d02016-08-25 14:26:59 +0800135 sun4i_timer_clear_interrupt();
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100136 evt->event_handler(evt);
137
138 return IRQ_HANDLED;
139}
140
Maxime Ripard119fd632013-03-24 11:49:25 +0100141static struct irqaction sun4i_timer_irq = {
142 .name = "sun4i_timer0",
Maxime Ripard33536522013-10-14 21:07:48 +0200143 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Maxime Ripard119fd632013-03-24 11:49:25 +0100144 .handler = sun4i_timer_interrupt,
145 .dev_id = &sun4i_clockevent,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100146};
147
Stephen Boyd662e7232013-11-20 00:47:32 +0100148static u64 notrace sun4i_timer_sched_read(void)
Maxime Ripard137c6b32013-07-16 16:45:37 +0200149{
150 return ~readl(timer_base + TIMER_CNTVAL_REG(1));
151}
152
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200153static int __init sun4i_timer_init(struct device_node *node)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100154{
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100155 unsigned long rate = 0;
156 struct clk *clk;
157 int ret, irq;
158 u32 val;
159
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100160 timer_base = of_iomap(node, 0);
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200161 if (!timer_base) {
162 pr_crit("Can't map registers");
163 return -ENXIO;
164 }
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100165
166 irq = irq_of_parse_and_map(node, 0);
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200167 if (irq <= 0) {
168 pr_crit("Can't parse IRQ");
169 return -EINVAL;
170 }
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100171
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100172 clk = of_clk_get(node, 0);
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200173 if (IS_ERR(clk)) {
174 pr_crit("Can't get timer clock");
175 return PTR_ERR(clk);
176 }
177
178 ret = clk_prepare_enable(clk);
179 if (ret) {
180 pr_err("Failed to prepare clock");
181 return ret;
182 }
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100183
184 rate = clk_get_rate(clk);
185
Maxime Ripard137c6b32013-07-16 16:45:37 +0200186 writel(~0, timer_base + TIMER_INTVAL_REG(1));
187 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
188 TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
189 timer_base + TIMER_CTL_REG(1));
190
Hans de Goede37b8b002015-03-30 22:17:10 +0200191 /*
192 * sched_clock_register does not have priorities, and on sun6i and
193 * later there is a better sched_clock registered by arm_arch_timer.c
194 */
195 if (of_machine_is_compatible("allwinner,sun4i-a10") ||
196 of_machine_is_compatible("allwinner,sun5i-a13") ||
197 of_machine_is_compatible("allwinner,sun5i-a10s"))
198 sched_clock_register(sun4i_timer_sched_read, 32, rate);
199
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200200 ret = clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
201 rate, 350, 32, clocksource_mmio_readl_down);
202 if (ret) {
203 pr_err("Failed to register clocksource");
204 return ret;
205 }
Maxime Ripard137c6b32013-07-16 16:45:37 +0200206
Maxime Ripard7e141832013-07-16 16:45:38 +0200207 ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100208
Maxime Ripard7e141832013-07-16 16:45:38 +0200209 writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
Maxime Riparda2c49e72013-07-16 16:45:38 +0200210 timer_base + TIMER_CTL_REG(0));
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100211
Marc Zyngier6db50bb2013-12-02 09:29:35 +0000212 /* Make sure timer is stopped before playing with interrupts */
213 sun4i_clkevt_time_stop(0);
214
Chen-Yu Tsaib53e7d02016-08-25 14:26:59 +0800215 /* clear timer0 interrupt */
216 sun4i_timer_clear_interrupt();
217
Maxime Ripard6bab4a82014-11-18 23:59:33 +0100218 sun4i_clockevent.cpumask = cpu_possible_mask;
219 sun4i_clockevent.irq = irq;
220
221 clockevents_config_and_register(&sun4i_clockevent, rate,
222 TIMER_SYNC_TICKS, 0xffffffff);
223
Maxime Ripard119fd632013-03-24 11:49:25 +0100224 ret = setup_irq(irq, &sun4i_timer_irq);
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200225 if (ret) {
226 pr_err("failed to setup irq %d\n", irq);
227 return ret;
228 }
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100229
230 /* Enable timer0 interrupt */
Maxime Ripard04981732013-03-10 17:03:46 +0100231 val = readl(timer_base + TIMER_IRQ_EN_REG);
232 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
Daniel Lezcanoce5dc742016-06-06 17:59:09 +0200233
234 return ret;
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100235}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200236CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
Maxime Ripard119fd632013-03-24 11:49:25 +0100237 sun4i_timer_init);