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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Standard Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
Kristen Accardi8cf4c192005-08-16 15:16:10 -070026 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
28 */
29#ifndef _SHPCHP_H
30#define _SHPCHP_H
31
32#include <linux/types.h>
33#include <linux/pci.h>
Greg Kroah-Hartman7a54f252006-10-13 20:05:19 -070034#include <linux/pci_hotplug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <linux/delay.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080036#include <linux/sched.h> /* signal_pending(), struct timer_list */
Ingo Molnar6aa4cdd2006-01-13 16:02:15 +010037#include <linux/mutex.h>
Tejun Heoe24dcbe2010-10-18 08:33:02 +020038#include <linux/workqueue.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080039
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#if !defined(MODULE)
41 #define MY_NAME "shpchp"
42#else
43 #define MY_NAME THIS_MODULE->name
44#endif
45
Rusty Russell90ab5ee2012-01-13 09:32:20 +103046extern bool shpchp_poll_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -070047extern int shpchp_poll_time;
Rusty Russell90ab5ee2012-01-13 09:32:20 +103048extern bool shpchp_debug;
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
Kenji Kaneshige8352e042006-12-16 15:25:57 -080050#define dbg(format, arg...) \
Frank Seidel1c35b8e2009-02-06 10:23:36 +010051do { \
52 if (shpchp_debug) \
Bogicevic Sasaff3ce482015-12-27 13:21:11 -080053 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
Frank Seidel1c35b8e2009-02-06 10:23:36 +010054} while (0)
Kenji Kaneshige8352e042006-12-16 15:25:57 -080055#define err(format, arg...) \
Bogicevic Sasaff3ce482015-12-27 13:21:11 -080056 printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
Kenji Kaneshige8352e042006-12-16 15:25:57 -080057#define info(format, arg...) \
Bogicevic Sasaff3ce482015-12-27 13:21:11 -080058 printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
Kenji Kaneshige8352e042006-12-16 15:25:57 -080059#define warn(format, arg...) \
Bogicevic Sasaff3ce482015-12-27 13:21:11 -080060 printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
Taku Izumif98ca312008-10-23 11:52:12 +090062#define ctrl_dbg(ctrl, format, arg...) \
63 do { \
64 if (shpchp_debug) \
Frank Seidel1c35b8e2009-02-06 10:23:36 +010065 dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \
Taku Izumif98ca312008-10-23 11:52:12 +090066 format, ## arg); \
67 } while (0)
68#define ctrl_err(ctrl, format, arg...) \
69 dev_err(&ctrl->pci_dev->dev, format, ## arg)
70#define ctrl_info(ctrl, format, arg...) \
71 dev_info(&ctrl->pci_dev->dev, format, ## arg)
72#define ctrl_warn(ctrl, format, arg...) \
73 dev_warn(&ctrl->pci_dev->dev, format, ## arg)
74
75
Kenji Kaneshigebbe779d2006-01-26 10:04:56 +090076#define SLOT_NAME_SIZE 10
Linus Torvalds1da177e2005-04-16 15:20:36 -070077struct slot {
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 u8 bus;
79 u8 device;
rajesh.shah@intel.com2178bfa2005-10-13 12:05:41 -070080 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 u32 number;
82 u8 is_a_board;
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 u8 state;
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 u8 presence_save;
rajesh.shah@intel.com2178bfa2005-10-13 12:05:41 -070085 u8 pwr_save;
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 struct controller *ctrl;
Julia Lawallbd790082015-12-23 21:35:35 +010087 const struct hpc_ops *hpc_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 struct hotplug_slot *hotplug_slot;
89 struct list_head slot_list;
David Howellsc4028952006-11-22 14:57:56 +000090 struct delayed_work work; /* work for button event */
Kenji Kaneshigea246fa42006-02-21 15:45:48 -080091 struct mutex lock;
Bjorn Helgaasf652e7d2013-01-11 12:21:15 -070092 struct workqueue_struct *wq;
Alex Chiang66f17052008-10-20 17:41:53 -060093 u8 hp_slot;
Linus Torvalds1da177e2005-04-16 15:20:36 -070094};
95
Linus Torvalds1da177e2005-04-16 15:20:36 -070096struct event_info {
97 u32 event_type;
Kenji Kaneshigef7391f52006-02-21 15:45:45 -080098 struct slot *p_slot;
99 struct work_struct work;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100};
101
102struct controller {
Ingo Molnar6aa4cdd2006-01-13 16:02:15 +0100103 struct mutex crit_sect; /* critical section mutex */
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +0900104 struct mutex cmd_lock; /* command lock */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 int num_slots; /* Number of slots on ctlr */
106 int slot_num_inc; /* 1 or -1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 struct pci_dev *pci_dev;
Kenji Kaneshige5b1a9602006-01-26 09:57:40 +0900108 struct list_head slot_list;
Julia Lawallbd790082015-12-23 21:35:35 +0100109 const struct hpc_ops *hpc_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 wait_queue_head_t queue; /* sleep & wake process */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 u8 slot_device_offset;
Keck, David53044f32006-01-16 15:22:36 -0600112 u32 pcix_misc2_reg; /* for amd pogo errata */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 u32 first_slot; /* First physical slot number */
Kenji Kaneshige04559862005-11-24 11:36:59 +0900114 u32 cap_offset;
115 unsigned long mmio_base;
116 unsigned long mmio_size;
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800117 void __iomem *creg;
118 struct timer_list poll_timer;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119};
120
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121/* Define AMD SHPC ID */
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800122#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
Keck, David53044f32006-01-16 15:22:36 -0600123#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
124
Stefan Assmann45e829e2009-12-03 06:49:24 -0500125/* AMD PCI-X bridge registers */
Keck, David53044f32006-01-16 15:22:36 -0600126#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
127#define PCIX_MISCII_OFFSET 0x48
128#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
129
130/* AMD PCIX_MISCII masks and offsets */
131#define PERRNONFATALENABLE_MASK 0x00040000
132#define PERRFATALENABLE_MASK 0x00080000
133#define PERRFLOODENABLE_MASK 0x00100000
134#define SERRNONFATALENABLE_MASK 0x00200000
135#define SERRFATALENABLE_MASK 0x00400000
136
137/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
138#define PERR_OBSERVED_MASK 0x00000001
139
140/* AMD PCIX_MEM_BASE_LIMIT masks */
141#define RSE_MASK 0x40000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142
143#define INT_BUTTON_IGNORE 0
144#define INT_PRESENCE_ON 1
145#define INT_PRESENCE_OFF 2
146#define INT_SWITCH_CLOSE 3
147#define INT_SWITCH_OPEN 4
148#define INT_POWER_FAULT 5
149#define INT_POWER_FAULT_CLEAR 6
150#define INT_BUTTON_PRESS 7
151#define INT_BUTTON_RELEASE 8
152#define INT_BUTTON_CANCEL 9
153
154#define STATIC_STATE 0
155#define BLINKINGON_STATE 1
156#define BLINKINGOFF_STATE 2
157#define POWERON_STATE 3
158#define POWEROFF_STATE 4
159
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160/* Error messages */
161#define INTERLOCK_OPEN 0x00000002
162#define ADD_NOT_SUPPORTED 0x00000003
163#define CARD_FUNCTIONING 0x00000005
164#define ADAPTER_NOT_SAME 0x00000006
165#define NO_ADAPTER_PRESENT 0x00000009
166#define NOT_ENOUGH_RESOURCES 0x0000000B
167#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
168#define WRONG_BUS_FREQUENCY 0x0000000D
169#define POWER_FAILURE 0x0000000E
170
Bjorn Helgaasf39d5b72013-04-12 12:02:59 -0600171int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
172void shpchp_remove_ctrl_files(struct controller *ctrl);
173int shpchp_sysfs_enable_slot(struct slot *slot);
174int shpchp_sysfs_disable_slot(struct slot *slot);
175u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
176u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
177u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
178u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
179int shpchp_configure_device(struct slot *p_slot);
180int shpchp_unconfigure_device(struct slot *p_slot);
181void cleanup_slots(struct controller *ctrl);
182void shpchp_queue_pushbutton_work(struct work_struct *work);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400183int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
Kristen Accardi783c49f2006-03-03 10:16:05 -0800184
Alex Chiang66f17052008-10-20 17:41:53 -0600185static inline const char *slot_name(struct slot *slot)
186{
187 return hotplug_slot_name(slot->hotplug_slot);
188}
189
Kristen Accardi783c49f2006-03-03 10:16:05 -0800190#ifdef CONFIG_ACPI
Kenji Kaneshigeac9c0522008-05-28 15:01:03 +0900191#include <linux/pci-acpi.h>
Kenji Kaneshigeac9c0522008-05-28 15:01:03 +0900192static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
193{
Bjorn Helgaas7dab9ef2013-09-05 15:07:39 -0600194 u32 flags = OSC_PCI_SHPC_NATIVE_HP_CONTROL;
Kenji Kaneshigeac9c0522008-05-28 15:01:03 +0900195 return acpi_get_hp_hw_control_from_firmware(dev, flags);
196}
Kristen Accardi783c49f2006-03-03 10:16:05 -0800197#else
Kenji Kaneshigeac9c0522008-05-28 15:01:03 +0900198#define get_hp_hw_control_from_firmware(dev) (0)
Kristen Accardi783c49f2006-03-03 10:16:05 -0800199#endif
200
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201struct ctrl_reg {
202 volatile u32 base_offset;
203 volatile u32 slot_avail1;
204 volatile u32 slot_avail2;
205 volatile u32 slot_config;
206 volatile u16 sec_bus_config;
207 volatile u8 msi_ctrl;
208 volatile u8 prog_interface;
209 volatile u16 cmd;
210 volatile u16 cmd_status;
211 volatile u32 intr_loc;
212 volatile u32 serr_loc;
213 volatile u32 serr_intr_enable;
214 volatile u32 slot1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215} __attribute__ ((packed));
216
217/* offsets to the controller registers based on the above structure layout */
218enum ctrl_offsets {
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700219 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
220 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800221 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700222 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800223 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
224 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700225 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800226 CMD = offsetof(struct ctrl_reg, cmd),
227 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
228 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
229 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
230 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
231 SLOT1 = offsetof(struct ctrl_reg, slot1),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800234static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800235{
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800236 return hotplug_slot->private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237}
238
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800239static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240{
Kenji Kaneshige5b1a9602006-01-26 09:57:40 +0900241 struct slot *slot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242
Kenji Kaneshige5b1a9602006-01-26 09:57:40 +0900243 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
244 if (slot->device == device)
245 return slot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 }
247
Taku Izumibe7bce22008-10-23 11:54:39 +0900248 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
Kenji Kaneshige5b1a9602006-01-26 09:57:40 +0900249 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250}
251
Keck, David53044f32006-01-16 15:22:36 -0600252static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
253{
254 u32 pcix_misc2_temp;
255
256 /* save MiscII register */
257 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
258
259 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
260
261 /* clear SERR/PERR enable bits */
262 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
263 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
264 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
265 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
266 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
267 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
268}
269
270static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
271{
272 u32 pcix_misc2_temp;
273 u32 pcix_bridge_errors_reg;
274 u32 pcix_mem_base_reg;
275 u8 perr_set;
276 u8 rse_set;
277
278 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
279 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
280 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
281 if (perr_set) {
Taku Izumif98ca312008-10-23 11:52:12 +0900282 ctrl_dbg(p_slot->ctrl,
Taku Izumibe7bce22008-10-23 11:54:39 +0900283 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
284 perr_set);
Keck, David53044f32006-01-16 15:22:36 -0600285
286 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
287 }
288
289 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
290 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
291 rse_set = pcix_mem_base_reg & RSE_MASK;
292 if (rse_set) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900293 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
Keck, David53044f32006-01-16 15:22:36 -0600294
295 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
296 }
297 /* restore MiscII register */
Bogicevic Sasaff3ce482015-12-27 13:21:11 -0800298 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
Keck, David53044f32006-01-16 15:22:36 -0600299
300 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
301 pcix_misc2_temp |= SERRFATALENABLE_MASK;
302 else
303 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
304
305 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
306 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
307 else
308 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
309
310 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
311 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
312 else
313 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
314
315 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
316 pcix_misc2_temp |= PERRFATALENABLE_MASK;
317 else
318 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
319
320 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
321 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
322 else
323 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
324 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
325}
326
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327struct hpc_ops {
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800328 int (*power_on_slot)(struct slot *slot);
329 int (*slot_enable)(struct slot *slot);
330 int (*slot_disable)(struct slot *slot);
331 int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
332 int (*get_power_status)(struct slot *slot, u8 *status);
333 int (*get_attention_status)(struct slot *slot, u8 *status);
334 int (*set_attention_status)(struct slot *slot, u8 status);
335 int (*get_latch_status)(struct slot *slot, u8 *status);
336 int (*get_adapter_status)(struct slot *slot, u8 *status);
Kenji Kaneshige8352e042006-12-16 15:25:57 -0800337 int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
338 int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
339 int (*get_prog_int)(struct slot *slot, u8 *prog_int);
340 int (*query_power_fault)(struct slot *slot);
341 void (*green_led_on)(struct slot *slot);
342 void (*green_led_off)(struct slot *slot);
343 void (*green_led_blink)(struct slot *slot);
344 void (*release_ctlr)(struct controller *ctrl);
345 int (*check_cmd_status)(struct controller *ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346};
347
348#endif /* _SHPCHP_H */