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gerrit-public.fairphone.software / kernel / msm-4.19 / 1aa8f0cb19e59a0def9925d401d628c1846c3270 / . / arch / arm / mach-omap2 / cm3xxx.c
blob: 55b046a719dc653275eb7421b735f876b3dc81cd [file] [log] [blame]
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]1/*
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]2 * OMAP3xxx CM module functions
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]3 *
4 * Copyright (C) 2009 Nokia Corporation
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]5 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]6 * Paul Walmsley
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]7 * Rajendra Nayak <rnayak@ti.com>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]15#include <linux/types.h>
16#include <linux/delay.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]21#include "prm2xxx_3xxx.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]22#include "cm.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]23#include "cm3xxx.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]24#include "cm-regbits-34xx.h"
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]25#include "clockdomain.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]26
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]27static const u8 omap3xxx_cm_idlest_offs[] = {
28 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]29};
30
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]31/*
32 *
33 */
34
35static void _write_clktrctrl(u8 c, s16 module, u32 mask)
36{
37 u32 v;
38
39 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
40 v &= ~mask;
41 v |= c << __ffs(mask);
42 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
43}
44
Tero Kristof2650d62014-10-27 08:39:24 -0700[diff] [blame]45static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]46{
47 u32 v;
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]48
49 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
50 v &= mask;
51 v >>= __ffs(mask);
52
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]53 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]54}
55
Tero Kristof2650d62014-10-27 08:39:24 -0700[diff] [blame]56static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]57{
58 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
59}
60
Tero Kristof2650d62014-10-27 08:39:24 -0700[diff] [blame]61static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]62{
63 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
64}
65
Tero Kristof2650d62014-10-27 08:39:24 -0700[diff] [blame]66static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]67{
68 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
69}
70
Tero Kristof2650d62014-10-27 08:39:24 -0700[diff] [blame]71static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]72{
73 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
74}
75
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700[diff] [blame]76/*
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]77 *
78 */
79
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]80/**
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]81 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
Tero Kristo021b6ff2014-10-27 08:39:23 -0700[diff] [blame]82 * @part: PRCM partition, ignored for OMAP3
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]83 * @prcm_mod: PRCM module offset
84 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
85 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
86 *
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]87 * Wait for the PRCM to indicate that the module identified by
88 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
89 * success or -EBUSY if the module doesn't enable in time.
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]90 */
Tero Kristo021b6ff2014-10-27 08:39:23 -0700[diff] [blame]91static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
92 u8 idlest_shift)
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]93{
94 int ena = 0, i = 0;
95 u8 cm_idlest_reg;
96 u32 mask;
97
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]98 if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]99 return -EINVAL;
100
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]101 cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]102
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]103 mask = 1 << idlest_shift;
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]104 ena = 0;
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]105
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]106 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
107 mask) == ena), MAX_MODULE_READY_TIME, i);
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]108
109 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
110}
111
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]112/**
113 * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
114 * @idlest_reg: CM_IDLEST* virtual address
115 * @prcm_inst: pointer to an s16 to return the PRCM instance offset
116 * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
117 *
118 * XXX This function is only needed until absolute register addresses are
119 * removed from the OMAP struct clk records.
120 */
Tero Kristo6c0afb52017-02-09 11:24:37 +0200[diff] [blame]121static int omap3xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
Tero Kristo2196a9b2014-10-27 08:39:24 -0700[diff] [blame]122 s16 *prcm_inst,
123 u8 *idlest_reg_id)
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]124{
125 unsigned long offs;
126 u8 idlest_offs;
127 int i;
128
Tero Kristo6c0afb52017-02-09 11:24:37 +0200[diff] [blame]129 idlest_offs = idlest_reg->offset & 0xff;
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]130 for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
131 if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
132 *idlest_reg_id = i + 1;
133 break;
134 }
135 }
136
137 if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
138 return -EINVAL;
139
Tero Kristo6c0afb52017-02-09 11:24:37 +0200[diff] [blame]140 offs = idlest_reg->offset;
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]141 offs &= 0xff00;
142 *prcm_inst = offs;
143
144 return 0;
145}
146
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]147/* Clockdomain low-level operations */
148
149static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
150 struct clockdomain *clkdm2)
151{
152 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
153 clkdm1->pwrdm.ptr->prcm_offs,
154 OMAP3430_CM_SLEEPDEP);
155 return 0;
156}
157
158static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
159 struct clockdomain *clkdm2)
160{
161 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
162 clkdm1->pwrdm.ptr->prcm_offs,
163 OMAP3430_CM_SLEEPDEP);
164 return 0;
165}
166
167static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
168 struct clockdomain *clkdm2)
169{
170 return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
171 OMAP3430_CM_SLEEPDEP,
172 (1 << clkdm2->dep_bit));
173}
174
175static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
176{
177 struct clkdm_dep *cd;
178 u32 mask = 0;
179
180 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
181 if (!cd->clkdm)
182 continue; /* only happens if data is erroneous */
183
184 mask |= 1 << cd->clkdm->dep_bit;
Paul Walmsley92493872013-01-26 00:58:17 -0700[diff] [blame]185 cd->sleepdep_usecount = 0;
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]186 }
187 omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
188 OMAP3430_CM_SLEEPDEP);
189 return 0;
190}
191
192static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
193{
194 omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
195 clkdm->clktrctrl_mask);
196 return 0;
197}
198
199static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
200{
201 omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
202 clkdm->clktrctrl_mask);
203 return 0;
204}
205
206static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
207{
Paul Walmsley92493872013-01-26 00:58:17 -0700[diff] [blame]208 if (clkdm->usecount > 0)
Paul Walmsley65958fb2013-01-26 00:58:17 -0700[diff] [blame]209 clkdm_add_autodeps(clkdm);
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]210
211 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
212 clkdm->clktrctrl_mask);
213}
214
215static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
216{
217 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
218 clkdm->clktrctrl_mask);
219
Paul Walmsley92493872013-01-26 00:58:17 -0700[diff] [blame]220 if (clkdm->usecount > 0)
Paul Walmsley65958fb2013-01-26 00:58:17 -0700[diff] [blame]221 clkdm_del_autodeps(clkdm);
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]222}
223
224static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
225{
226 bool hwsup = false;
227
228 if (!clkdm->clktrctrl_mask)
229 return 0;
230
231 /*
232 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
233 * more details on the unpleasant problem this is working
234 * around
235 */
236 if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
237 (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
238 omap3xxx_clkdm_wakeup(clkdm);
239 return 0;
240 }
241
242 hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
243 clkdm->clktrctrl_mask);
244
245 if (hwsup) {
246 /* Disable HW transitions when we are changing deps */
247 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
248 clkdm->clktrctrl_mask);
Paul Walmsley65958fb2013-01-26 00:58:17 -0700[diff] [blame]249 clkdm_add_autodeps(clkdm);
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]250 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
251 clkdm->clktrctrl_mask);
252 } else {
253 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
254 omap3xxx_clkdm_wakeup(clkdm);
255 }
256
257 return 0;
258}
259
260static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
261{
262 bool hwsup = false;
263
264 if (!clkdm->clktrctrl_mask)
265 return 0;
266
267 /*
268 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
269 * more details on the unpleasant problem this is working
270 * around
271 */
272 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
273 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
274 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
275 clkdm->clktrctrl_mask);
276 return 0;
277 }
278
279 hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
280 clkdm->clktrctrl_mask);
281
282 if (hwsup) {
283 /* Disable HW transitions when we are changing deps */
284 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
285 clkdm->clktrctrl_mask);
Paul Walmsley65958fb2013-01-26 00:58:17 -0700[diff] [blame]286 clkdm_del_autodeps(clkdm);
Paul Walmsley4bd52592012-10-21 01:01:11 -0600[diff] [blame]287 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
288 clkdm->clktrctrl_mask);
289 } else {
290 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
291 omap3xxx_clkdm_sleep(clkdm);
292 }
293
294 return 0;
295}
296
297struct clkdm_ops omap3_clkdm_operations = {
298 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
299 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
300 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
301 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
302 .clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep,
303 .clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep,
304 .clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep,
305 .clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps,
306 .clkdm_sleep = omap3xxx_clkdm_sleep,
307 .clkdm_wakeup = omap3xxx_clkdm_wakeup,
308 .clkdm_allow_idle = omap3xxx_clkdm_allow_idle,
309 .clkdm_deny_idle = omap3xxx_clkdm_deny_idle,
310 .clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
311 .clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
312};
313
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]314/*
315 * Context save/restore code - OMAP3 only
316 */
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]317struct omap3_cm_regs {
318 u32 iva2_cm_clksel1;
319 u32 iva2_cm_clksel2;
320 u32 cm_sysconfig;
321 u32 sgx_cm_clksel;
322 u32 dss_cm_clksel;
323 u32 cam_cm_clksel;
324 u32 per_cm_clksel;
325 u32 emu_cm_clksel;
326 u32 emu_cm_clkstctrl;
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]327 u32 pll_cm_autoidle;
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]328 u32 pll_cm_autoidle2;
329 u32 pll_cm_clksel4;
330 u32 pll_cm_clksel5;
331 u32 pll_cm_clken2;
332 u32 cm_polctrl;
333 u32 iva2_cm_fclken;
334 u32 iva2_cm_clken_pll;
335 u32 core_cm_fclken1;
336 u32 core_cm_fclken3;
337 u32 sgx_cm_fclken;
338 u32 wkup_cm_fclken;
339 u32 dss_cm_fclken;
340 u32 cam_cm_fclken;
341 u32 per_cm_fclken;
342 u32 usbhost_cm_fclken;
343 u32 core_cm_iclken1;
344 u32 core_cm_iclken2;
345 u32 core_cm_iclken3;
346 u32 sgx_cm_iclken;
347 u32 wkup_cm_iclken;
348 u32 dss_cm_iclken;
349 u32 cam_cm_iclken;
350 u32 per_cm_iclken;
351 u32 usbhost_cm_iclken;
352 u32 iva2_cm_autoidle2;
353 u32 mpu_cm_autoidle2;
354 u32 iva2_cm_clkstctrl;
355 u32 mpu_cm_clkstctrl;
356 u32 core_cm_clkstctrl;
357 u32 sgx_cm_clkstctrl;
358 u32 dss_cm_clkstctrl;
359 u32 cam_cm_clkstctrl;
360 u32 per_cm_clkstctrl;
361 u32 neon_cm_clkstctrl;
362 u32 usbhost_cm_clkstctrl;
363 u32 core_cm_autoidle1;
364 u32 core_cm_autoidle2;
365 u32 core_cm_autoidle3;
366 u32 wkup_cm_autoidle;
367 u32 dss_cm_autoidle;
368 u32 cam_cm_autoidle;
369 u32 per_cm_autoidle;
370 u32 usbhost_cm_autoidle;
371 u32 sgx_cm_sleepdep;
372 u32 dss_cm_sleepdep;
373 u32 cam_cm_sleepdep;
374 u32 per_cm_sleepdep;
375 u32 usbhost_cm_sleepdep;
376 u32 cm_clkout_ctrl;
377};
378
379static struct omap3_cm_regs cm_context;
380
381void omap3_cm_save_context(void)
382{
383 cm_context.iva2_cm_clksel1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]384 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]385 cm_context.iva2_cm_clksel2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]386 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
Tero Kristob21be7b2014-03-04 18:19:01 +0200[diff] [blame]387 cm_context.cm_sysconfig =
388 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]389 cm_context.sgx_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]390 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]391 cm_context.dss_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]392 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]393 cm_context.cam_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]394 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]395 cm_context.per_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]396 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]397 cm_context.emu_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]398 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]399 cm_context.emu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]400 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]401 /*
402 * As per erratum i671, ROM code does not respect the PER DPLL
403 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
404 * In this case, even though this register has been saved in
405 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
406 * by ourselves. So, we need to save it anyway.
407 */
408 cm_context.pll_cm_autoidle =
409 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]410 cm_context.pll_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]411 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]412 cm_context.pll_cm_clksel4 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]413 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]414 cm_context.pll_cm_clksel5 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]415 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]416 cm_context.pll_cm_clken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]417 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
Tero Kristob21be7b2014-03-04 18:19:01 +0200[diff] [blame]418 cm_context.cm_polctrl =
419 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]420 cm_context.iva2_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]421 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
422 cm_context.iva2_cm_clken_pll =
423 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]424 cm_context.core_cm_fclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]425 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]426 cm_context.core_cm_fclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]427 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]428 cm_context.sgx_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]429 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]430 cm_context.wkup_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]431 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]432 cm_context.dss_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]433 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]434 cm_context.cam_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]435 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]436 cm_context.per_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]437 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]438 cm_context.usbhost_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]439 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]440 cm_context.core_cm_iclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]441 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]442 cm_context.core_cm_iclken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]443 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]444 cm_context.core_cm_iclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]445 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]446 cm_context.sgx_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]447 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]448 cm_context.wkup_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]449 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]450 cm_context.dss_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]451 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]452 cm_context.cam_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]453 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]454 cm_context.per_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]455 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]456 cm_context.usbhost_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]457 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]458 cm_context.iva2_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]459 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]460 cm_context.mpu_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]461 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]462 cm_context.iva2_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]463 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]464 cm_context.mpu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]465 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]466 cm_context.core_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]467 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]468 cm_context.sgx_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]469 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]470 cm_context.dss_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]471 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]472 cm_context.cam_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]473 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]474 cm_context.per_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]475 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]476 cm_context.neon_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]477 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]478 cm_context.usbhost_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]479 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
480 OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]481 cm_context.core_cm_autoidle1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]482 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]483 cm_context.core_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]484 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]485 cm_context.core_cm_autoidle3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]486 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]487 cm_context.wkup_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]488 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]489 cm_context.dss_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]490 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]491 cm_context.cam_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]492 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]493 cm_context.per_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]494 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]495 cm_context.usbhost_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]496 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]497 cm_context.sgx_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]498 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
499 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]500 cm_context.dss_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]501 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]502 cm_context.cam_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]503 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]504 cm_context.per_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]505 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]506 cm_context.usbhost_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]507 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
508 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]509 cm_context.cm_clkout_ctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]510 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
511 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]512}
513
514void omap3_cm_restore_context(void)
515{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]516 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
517 CM_CLKSEL1);
518 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
519 CM_CLKSEL2);
Tero Kristob21be7b2014-03-04 18:19:01 +0200[diff] [blame]520 omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
521 OMAP3430_CM_SYSCONFIG);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]522 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
523 CM_CLKSEL);
524 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
525 CM_CLKSEL);
526 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
527 CM_CLKSEL);
528 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
529 CM_CLKSEL);
530 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
531 CM_CLKSEL1);
532 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
533 OMAP2_CM_CLKSTCTRL);
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]534 /*
535 * As per erratum i671, ROM code does not respect the PER DPLL
536 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
537 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
538 */
539 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
540 CM_AUTOIDLE);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]541 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
542 CM_AUTOIDLE2);
543 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
544 OMAP3430ES2_CM_CLKSEL4);
545 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
546 OMAP3430ES2_CM_CLKSEL5);
547 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
548 OMAP3430ES2_CM_CLKEN2);
Tero Kristob21be7b2014-03-04 18:19:01 +0200[diff] [blame]549 omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
550 OMAP3430_CM_POLCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]551 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
552 CM_FCLKEN);
553 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
554 OMAP3430_CM_CLKEN_PLL);
555 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
556 CM_FCLKEN1);
557 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
558 OMAP3430ES2_CM_FCLKEN3);
559 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
560 CM_FCLKEN);
561 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
562 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
563 CM_FCLKEN);
564 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
565 CM_FCLKEN);
566 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
567 CM_FCLKEN);
568 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
569 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
570 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
571 CM_ICLKEN1);
572 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
573 CM_ICLKEN2);
574 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
575 CM_ICLKEN3);
576 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
577 CM_ICLKEN);
578 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
579 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
580 CM_ICLKEN);
581 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
582 CM_ICLKEN);
583 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
584 CM_ICLKEN);
585 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
586 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
587 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
588 CM_AUTOIDLE2);
589 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
590 CM_AUTOIDLE2);
591 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
592 OMAP2_CM_CLKSTCTRL);
593 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
594 OMAP2_CM_CLKSTCTRL);
595 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
596 OMAP2_CM_CLKSTCTRL);
597 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
598 OMAP2_CM_CLKSTCTRL);
599 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
600 OMAP2_CM_CLKSTCTRL);
601 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
602 OMAP2_CM_CLKSTCTRL);
603 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
604 OMAP2_CM_CLKSTCTRL);
605 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
606 OMAP2_CM_CLKSTCTRL);
607 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
608 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
609 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
610 CM_AUTOIDLE1);
611 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
612 CM_AUTOIDLE2);
613 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
614 CM_AUTOIDLE3);
615 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
616 CM_AUTOIDLE);
617 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
618 CM_AUTOIDLE);
619 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
620 CM_AUTOIDLE);
621 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
622 CM_AUTOIDLE);
623 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
624 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
625 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
626 OMAP3430_CM_SLEEPDEP);
627 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
628 OMAP3430_CM_SLEEPDEP);
629 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
630 OMAP3430_CM_SLEEPDEP);
631 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
632 OMAP3430_CM_SLEEPDEP);
633 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
634 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
635 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
636 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]637}
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]638
Tero Kristoc6a2d832013-10-11 19:15:34 +0300[diff] [blame]639void omap3_cm_save_scratchpad_contents(u32 *ptr)
640{
641 *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
642 *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
643 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
644
645 /*
646 * As per erratum i671, ROM code does not respect the PER DPLL
647 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
Andrea Gelmini3c4d4c22016-05-21 13:50:07 +0200[diff] [blame]648 * Then, in any case, clear these bits to avoid extra latencies.
Tero Kristoc6a2d832013-10-11 19:15:34 +0300[diff] [blame]649 */
650 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
651 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
652 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
653 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
654 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
655 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
656 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
657 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
658 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
659}
660
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]661/*
662 *
663 */
664
665static struct cm_ll_data omap3xxx_cm_ll_data = {
666 .split_idlest_reg = &omap3xxx_cm_split_idlest_reg,
667 .wait_module_ready = &omap3xxx_cm_wait_module_ready,
668};
669
Tero Kristo425dc8b2014-11-21 15:51:37 +0200[diff] [blame]670int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]671{
Tero Kristo5970ca22014-11-11 16:51:52 +0200[diff] [blame]672 omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]673 return cm_register(&omap3xxx_cm_ll_data);
674}
675
676static void __exit omap3xxx_cm_exit(void)
677{
Tero Kristo7af13632014-03-04 18:19:03 +0200[diff] [blame]678 cm_unregister(&omap3xxx_cm_ll_data);
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]679}
680__exitcall(omap3xxx_cm_exit);