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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
Thiemo Seufer115f2a42006-07-09 01:47:06 +01008 * Copyright (C) 2004,2005,2006 by Thiemo Seufer
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00009 * Copyright (C) 2005 Maciej W. Rozycki
Ralf Baechle41c594a2006-04-05 09:45:45 +010010 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 *
12 * ... and the days got worse and worse and now you see
13 * I've gone completly out of my mind.
14 *
15 * They're coming to take me a away haha
16 * they're coming to take me a away hoho hihi haha
17 * to the funny farm where code is beautiful all the time ...
18 *
19 * (Condolences to Napoleon XIV)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 */
21
22#include <stdarg.h>
23
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/mm.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/string.h>
28#include <linux/init.h>
29
30#include <asm/pgtable.h>
31#include <asm/cacheflush.h>
32#include <asm/mmu_context.h>
33#include <asm/inst.h>
34#include <asm/elf.h>
35#include <asm/smp.h>
36#include <asm/war.h>
37
David Rientjese8b6d402007-05-10 22:51:05 -070038static __init int __maybe_unused r45k_bvahwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039{
40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0;
42}
43
David Rientjese8b6d402007-05-10 22:51:05 -070044static __init int __maybe_unused r4k_250MHZhwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070045{
46 /* XXX: We should probe for the presence of this bug, but we don't. */
47 return 0;
48}
49
David Rientjese8b6d402007-05-10 22:51:05 -070050static __init int __maybe_unused bcm1250_m3_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051{
52 return BCM1250_M3_WAR;
53}
54
David Rientjese8b6d402007-05-10 22:51:05 -070055static __init int __maybe_unused r10000_llsc_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070056{
57 return R10000_LLSC_WAR;
58}
59
60/*
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +010061 * Found by experiment: At least some revisions of the 4kc throw under
62 * some circumstances a machine check exception, triggered by invalid
63 * values in the index register. Delaying the tlbp instruction until
64 * after the next branch, plus adding an additional nop in front of
65 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
66 * why; it's not an issue caused by the core RTL.
67 *
68 */
69static __init int __attribute__((unused)) m4kc_tlbp_war(void)
70{
71 return (current_cpu_data.processor_id & 0xffff00) ==
72 (PRID_COMP_MIPS | PRID_IMP_4KC);
73}
74
75/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 * A little micro-assembler, intended for TLB refill handler
77 * synthesizing. It is intentionally kept simple, does only support
78 * a subset of instructions, and does not try to hide pipeline effects
79 * like branch delay slots.
80 */
81
82enum fields
83{
84 RS = 0x001,
85 RT = 0x002,
86 RD = 0x004,
87 RE = 0x008,
88 SIMM = 0x010,
89 UIMM = 0x020,
90 BIMM = 0x040,
91 JIMM = 0x080,
92 FUNC = 0x100,
Ralf Baechle41c594a2006-04-05 09:45:45 +010093 SET = 0x200
Linus Torvalds1da177e2005-04-16 15:20:36 -070094};
95
Thiemo Seufer603c3382007-09-05 12:11:22 +010096#define OP_MASK 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -070097#define OP_SH 26
98#define RS_MASK 0x1f
99#define RS_SH 21
100#define RT_MASK 0x1f
101#define RT_SH 16
102#define RD_MASK 0x1f
103#define RD_SH 11
104#define RE_MASK 0x1f
105#define RE_SH 6
106#define IMM_MASK 0xffff
107#define IMM_SH 0
108#define JIMM_MASK 0x3ffffff
109#define JIMM_SH 0
Thiemo Seufer603c3382007-09-05 12:11:22 +0100110#define FUNC_MASK 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111#define FUNC_SH 0
Ralf Baechle41c594a2006-04-05 09:45:45 +0100112#define SET_MASK 0x7
113#define SET_SH 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115enum opcode {
116 insn_invalid,
117 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
118 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
119 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
Ralf Baechle242954b2006-10-24 02:29:01 +0100120 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
122 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
123 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
124 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
125 insn_tlbwr, insn_xor, insn_xori
126};
127
128struct insn {
129 enum opcode opcode;
130 u32 match;
131 enum fields fields;
132};
133
134/* This macro sets the non-variable bits of an instruction. */
135#define M(a, b, c, d, e, f) \
136 ((a) << OP_SH \
137 | (b) << RS_SH \
138 | (c) << RT_SH \
139 | (d) << RD_SH \
140 | (e) << RE_SH \
141 | (f) << FUNC_SH)
142
143static __initdata struct insn insn_table[] = {
144 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
145 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
146 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
147 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
148 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
149 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
150 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
151 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
152 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
153 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
154 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
155 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
156 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
Ralf Baechle41c594a2006-04-05 09:45:45 +0100157 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET},
158 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
160 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
161 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
162 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
Ralf Baechle242954b2006-10-24 02:29:01 +0100163 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
165 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
166 { insn_j, M(j_op,0,0,0,0,0), JIMM },
167 { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
168 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
169 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
170 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
171 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
172 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
173 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
Ralf Baechle41c594a2006-04-05 09:45:45 +0100174 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET},
175 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
177 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
178 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
179 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
180 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
181 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
182 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
183 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
184 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
185 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
186 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
187 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
188 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
189 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
190 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
191 { insn_invalid, 0, 0 }
192};
193
194#undef M
195
196static __init u32 build_rs(u32 arg)
197{
198 if (arg & ~RS_MASK)
199 printk(KERN_WARNING "TLB synthesizer field overflow\n");
200
201 return (arg & RS_MASK) << RS_SH;
202}
203
204static __init u32 build_rt(u32 arg)
205{
206 if (arg & ~RT_MASK)
207 printk(KERN_WARNING "TLB synthesizer field overflow\n");
208
209 return (arg & RT_MASK) << RT_SH;
210}
211
212static __init u32 build_rd(u32 arg)
213{
214 if (arg & ~RD_MASK)
215 printk(KERN_WARNING "TLB synthesizer field overflow\n");
216
217 return (arg & RD_MASK) << RD_SH;
218}
219
220static __init u32 build_re(u32 arg)
221{
222 if (arg & ~RE_MASK)
223 printk(KERN_WARNING "TLB synthesizer field overflow\n");
224
225 return (arg & RE_MASK) << RE_SH;
226}
227
228static __init u32 build_simm(s32 arg)
229{
230 if (arg > 0x7fff || arg < -0x8000)
231 printk(KERN_WARNING "TLB synthesizer field overflow\n");
232
233 return arg & 0xffff;
234}
235
236static __init u32 build_uimm(u32 arg)
237{
238 if (arg & ~IMM_MASK)
239 printk(KERN_WARNING "TLB synthesizer field overflow\n");
240
241 return arg & IMM_MASK;
242}
243
244static __init u32 build_bimm(s32 arg)
245{
246 if (arg > 0x1ffff || arg < -0x20000)
247 printk(KERN_WARNING "TLB synthesizer field overflow\n");
248
249 if (arg & 0x3)
250 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n");
251
252 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
253}
254
255static __init u32 build_jimm(u32 arg)
256{
257 if (arg & ~((JIMM_MASK) << 2))
258 printk(KERN_WARNING "TLB synthesizer field overflow\n");
259
260 return (arg >> 2) & JIMM_MASK;
261}
262
263static __init u32 build_func(u32 arg)
264{
265 if (arg & ~FUNC_MASK)
266 printk(KERN_WARNING "TLB synthesizer field overflow\n");
267
268 return arg & FUNC_MASK;
269}
270
Ralf Baechle41c594a2006-04-05 09:45:45 +0100271static __init u32 build_set(u32 arg)
272{
273 if (arg & ~SET_MASK)
274 printk(KERN_WARNING "TLB synthesizer field overflow\n");
275
276 return arg & SET_MASK;
277}
278
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279/*
280 * The order of opcode arguments is implicitly left to right,
281 * starting with RS and ending with FUNC or IMM.
282 */
283static void __init build_insn(u32 **buf, enum opcode opc, ...)
284{
285 struct insn *ip = NULL;
286 unsigned int i;
287 va_list ap;
288 u32 op;
289
290 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
291 if (insn_table[i].opcode == opc) {
292 ip = &insn_table[i];
293 break;
294 }
295
296 if (!ip)
297 panic("Unsupported TLB synthesizer instruction %d", opc);
298
299 op = ip->match;
300 va_start(ap, opc);
301 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32));
302 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32));
303 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32));
304 if (ip->fields & RE) op |= build_re(va_arg(ap, u32));
305 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32));
306 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32));
307 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32));
308 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32));
309 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32));
Ralf Baechle41c594a2006-04-05 09:45:45 +0100310 if (ip->fields & SET) op |= build_set(va_arg(ap, u32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 va_end(ap);
312
313 **buf = op;
314 (*buf)++;
315}
316
317#define I_u1u2u3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000318 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 unsigned int b, unsigned int c) \
320 { \
321 build_insn(buf, insn##op, a, b, c); \
322 }
323
324#define I_u2u1u3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000325 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 unsigned int b, unsigned int c) \
327 { \
328 build_insn(buf, insn##op, b, a, c); \
329 }
330
331#define I_u3u1u2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000332 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 unsigned int b, unsigned int c) \
334 { \
335 build_insn(buf, insn##op, b, c, a); \
336 }
337
338#define I_u1u2s3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000339 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 unsigned int b, signed int c) \
341 { \
342 build_insn(buf, insn##op, a, b, c); \
343 }
344
345#define I_u2s3u1(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000346 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 signed int b, unsigned int c) \
348 { \
349 build_insn(buf, insn##op, c, a, b); \
350 }
351
352#define I_u2u1s3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000353 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354 unsigned int b, signed int c) \
355 { \
356 build_insn(buf, insn##op, b, a, c); \
357 }
358
359#define I_u1u2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000360 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 unsigned int b) \
362 { \
363 build_insn(buf, insn##op, a, b); \
364 }
365
366#define I_u1s2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000367 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368 signed int b) \
369 { \
370 build_insn(buf, insn##op, a, b); \
371 }
372
373#define I_u1(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000374 static inline void __init i##op(u32 **buf, unsigned int a) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 { \
376 build_insn(buf, insn##op, a); \
377 }
378
379#define I_0(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000380 static inline void __init i##op(u32 **buf) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 { \
382 build_insn(buf, insn##op); \
383 }
384
385I_u2u1s3(_addiu);
386I_u3u1u2(_addu);
387I_u2u1u3(_andi);
388I_u3u1u2(_and);
389I_u1u2s3(_beq);
390I_u1u2s3(_beql);
391I_u1s2(_bgez);
392I_u1s2(_bgezl);
393I_u1s2(_bltz);
394I_u1s2(_bltzl);
395I_u1u2s3(_bne);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100396I_u1u2u3(_dmfc0);
397I_u1u2u3(_dmtc0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398I_u2u1s3(_daddiu);
399I_u3u1u2(_daddu);
400I_u2u1u3(_dsll);
401I_u2u1u3(_dsll32);
402I_u2u1u3(_dsra);
403I_u2u1u3(_dsrl);
Ralf Baechle242954b2006-10-24 02:29:01 +0100404I_u2u1u3(_dsrl32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405I_u3u1u2(_dsubu);
406I_0(_eret);
407I_u1(_j);
408I_u1(_jal);
409I_u1(_jr);
410I_u2s3u1(_ld);
411I_u2s3u1(_ll);
412I_u2s3u1(_lld);
413I_u1s2(_lui);
414I_u2s3u1(_lw);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100415I_u1u2u3(_mfc0);
416I_u1u2u3(_mtc0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417I_u2u1u3(_ori);
418I_0(_rfe);
419I_u2s3u1(_sc);
420I_u2s3u1(_scd);
421I_u2s3u1(_sd);
422I_u2u1u3(_sll);
423I_u2u1u3(_sra);
424I_u2u1u3(_srl);
425I_u3u1u2(_subu);
426I_u2s3u1(_sw);
427I_0(_tlbp);
428I_0(_tlbwi);
429I_0(_tlbwr);
430I_u3u1u2(_xor)
431I_u2u1u3(_xori);
432
433/*
434 * handling labels
435 */
436
437enum label_id {
438 label_invalid,
439 label_second_part,
440 label_leave,
Atsushi Nemoto656be922006-10-26 00:08:31 +0900441#ifdef MODULE_START
442 label_module_alloc,
443#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 label_vmalloc,
445 label_vmalloc_done,
446 label_tlbw_hazard,
447 label_split,
448 label_nopage_tlbl,
449 label_nopage_tlbs,
450 label_nopage_tlbm,
451 label_smp_pgtable_change,
452 label_r3000_write_probe_fail,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453};
454
455struct label {
456 u32 *addr;
457 enum label_id lab;
458};
459
460static __init void build_label(struct label **lab, u32 *addr,
461 enum label_id l)
462{
463 (*lab)->addr = addr;
464 (*lab)->lab = l;
465 (*lab)++;
466}
467
468#define L_LA(lb) \
469 static inline void l##lb(struct label **lab, u32 *addr) \
470 { \
471 build_label(lab, addr, label##lb); \
472 }
473
474L_LA(_second_part)
475L_LA(_leave)
Atsushi Nemoto656be922006-10-26 00:08:31 +0900476#ifdef MODULE_START
477L_LA(_module_alloc)
478#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479L_LA(_vmalloc)
480L_LA(_vmalloc_done)
481L_LA(_tlbw_hazard)
482L_LA(_split)
483L_LA(_nopage_tlbl)
484L_LA(_nopage_tlbs)
485L_LA(_nopage_tlbm)
486L_LA(_smp_pgtable_change)
487L_LA(_r3000_write_probe_fail)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489/* convenience macros for instructions */
Ralf Baechle875d43e2005-09-03 15:56:16 -0700490#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
492# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
493# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
494# define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
495# define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100496# define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd)
497# define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498# define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
499# define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
500# define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
501# define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
502# define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
503#else
504# define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
505# define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
506# define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
507# define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
508# define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100509# define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd)
510# define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511# define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
512# define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
513# define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
514# define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
515# define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
516#endif
517
518#define i_b(buf, off) i_beq(buf, 0, 0, off)
519#define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
520#define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
521#define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
522#define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
523#define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
524#define i_nop(buf) i_sll(buf, 0, 0, 0)
525#define i_ssnop(buf) i_sll(buf, 0, 0, 1)
526#define i_ehb(buf) i_sll(buf, 0, 0, 3)
527
Ralf Baechle875d43e2005-09-03 15:56:16 -0700528#ifdef CONFIG_64BIT
David Rientjese8b6d402007-05-10 22:51:05 -0700529static __init int __maybe_unused in_compat_space_p(long addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530{
531 /* Is this address in 32bit compat space? */
Ralf Baechle3ef33e62005-07-08 20:10:17 +0000532 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533}
534
David Rientjese8b6d402007-05-10 22:51:05 -0700535static __init int __maybe_unused rel_highest(long val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536{
537 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
538}
539
David Rientjese8b6d402007-05-10 22:51:05 -0700540static __init int __maybe_unused rel_higher(long val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541{
542 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
543}
544#endif
545
546static __init int rel_hi(long val)
547{
548 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
549}
550
551static __init int rel_lo(long val)
552{
553 return ((val & 0xffff) ^ 0x8000) - 0x8000;
554}
555
556static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
557{
Yoichi Yuasa766160c2005-09-03 15:56:22 -0700558#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 if (!in_compat_space_p(addr)) {
560 i_lui(buf, rs, rel_highest(addr));
561 if (rel_higher(addr))
562 i_daddiu(buf, rs, rs, rel_higher(addr));
563 if (rel_hi(addr)) {
564 i_dsll(buf, rs, rs, 16);
565 i_daddiu(buf, rs, rs, rel_hi(addr));
566 i_dsll(buf, rs, rs, 16);
567 } else
568 i_dsll32(buf, rs, rs, 0);
569 } else
570#endif
571 i_lui(buf, rs, rel_hi(addr));
572}
573
David Rientjese8b6d402007-05-10 22:51:05 -0700574static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
575 long addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576{
577 i_LA_mostly(buf, rs, addr);
578 if (rel_lo(addr))
579 i_ADDIU(buf, rs, rs, rel_lo(addr));
580}
581
582/*
583 * handle relocations
584 */
585
586struct reloc {
587 u32 *addr;
588 unsigned int type;
589 enum label_id lab;
590};
591
592static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
593 enum label_id l)
594{
595 (*rel)->addr = addr;
596 (*rel)->type = R_MIPS_PC16;
597 (*rel)->lab = l;
598 (*rel)++;
599}
600
601static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
602{
603 long laddr = (long)lab->addr;
604 long raddr = (long)rel->addr;
605
606 switch (rel->type) {
607 case R_MIPS_PC16:
608 *rel->addr |= build_bimm(laddr - (raddr + 4));
609 break;
610
611 default:
612 panic("Unsupported TLB synthesizer relocation %d",
613 rel->type);
614 }
615}
616
617static __init void resolve_relocs(struct reloc *rel, struct label *lab)
618{
619 struct label *l;
620
621 for (; rel->lab != label_invalid; rel++)
622 for (l = lab; l->lab != label_invalid; l++)
623 if (rel->lab == l->lab)
624 __resolve_relocs(rel, l);
625}
626
627static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
628 long off)
629{
630 for (; rel->lab != label_invalid; rel++)
631 if (rel->addr >= first && rel->addr < end)
632 rel->addr += off;
633}
634
635static __init void move_labels(struct label *lab, u32 *first, u32 *end,
636 long off)
637{
638 for (; lab->lab != label_invalid; lab++)
639 if (lab->addr >= first && lab->addr < end)
640 lab->addr += off;
641}
642
643static __init void copy_handler(struct reloc *rel, struct label *lab,
644 u32 *first, u32 *end, u32 *target)
645{
646 long off = (long)(target - first);
647
648 memcpy(target, first, (end - first) * sizeof(u32));
649
650 move_relocs(rel, first, end, off);
651 move_labels(lab, first, end, off);
652}
653
David Rientjese8b6d402007-05-10 22:51:05 -0700654static __init int __maybe_unused insn_has_bdelay(struct reloc *rel,
655 u32 *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656{
657 for (; rel->lab != label_invalid; rel++) {
658 if (rel->addr == addr
659 && (rel->type == R_MIPS_PC16
660 || rel->type == R_MIPS_26))
661 return 1;
662 }
663
664 return 0;
665}
666
667/* convenience functions for labeled branches */
David Rientjese8b6d402007-05-10 22:51:05 -0700668static void __init __maybe_unused
Ralf Baechle1443e482006-03-08 15:37:26 +0000669 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670{
671 r_mips_pc16(r, *p, l);
672 i_bltz(p, reg, 0);
673}
674
David Rientjese8b6d402007-05-10 22:51:05 -0700675static void __init __maybe_unused il_b(u32 **p, struct reloc **r,
676 enum label_id l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677{
678 r_mips_pc16(r, *p, l);
679 i_b(p, 0);
680}
681
Ralf Baechle1443e482006-03-08 15:37:26 +0000682static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 enum label_id l)
684{
685 r_mips_pc16(r, *p, l);
686 i_beqz(p, reg, 0);
687}
688
David Rientjese8b6d402007-05-10 22:51:05 -0700689static void __init __maybe_unused
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
691{
692 r_mips_pc16(r, *p, l);
693 i_beqzl(p, reg, 0);
694}
695
Ralf Baechle1443e482006-03-08 15:37:26 +0000696static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697 enum label_id l)
698{
699 r_mips_pc16(r, *p, l);
700 i_bnez(p, reg, 0);
701}
702
Ralf Baechle1443e482006-03-08 15:37:26 +0000703static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 enum label_id l)
705{
706 r_mips_pc16(r, *p, l);
707 i_bgezl(p, reg, 0);
708}
709
David Rientjese8b6d402007-05-10 22:51:05 -0700710static void __init __maybe_unused
Atsushi Nemoto656be922006-10-26 00:08:31 +0900711il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
712{
713 r_mips_pc16(r, *p, l);
714 i_bgez(p, reg, 0);
715}
716
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717/* The only general purpose registers allowed in TLB handlers. */
718#define K0 26
719#define K1 27
720
721/* Some CP0 registers */
Ralf Baechle41c594a2006-04-05 09:45:45 +0100722#define C0_INDEX 0, 0
723#define C0_ENTRYLO0 2, 0
724#define C0_TCBIND 2, 2
725#define C0_ENTRYLO1 3, 0
726#define C0_CONTEXT 4, 0
727#define C0_BADVADDR 8, 0
728#define C0_ENTRYHI 10, 0
729#define C0_EPC 14, 0
730#define C0_XCONTEXT 20, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731
Ralf Baechle875d43e2005-09-03 15:56:16 -0700732#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
734#else
735# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
736#endif
737
738/* The worst case length of the handler is around 18 instructions for
739 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
740 * Maximum space available is 32 instructions for R3000 and 64
741 * instructions for R4000.
742 *
743 * We deliberately chose a buffer size of 128, so we won't scribble
744 * over anything important on overflow before we panic.
745 */
746static __initdata u32 tlb_handler[128];
747
748/* simply assume worst case size for labels and relocs */
749static __initdata struct label labels[128];
750static __initdata struct reloc relocs[128];
751
752/*
753 * The R3000 TLB handler is simple.
754 */
755static void __init build_r3000_tlb_refill_handler(void)
756{
757 long pgdc = (long)pgd_current;
758 u32 *p;
Thiemo Seufer115f2a42006-07-09 01:47:06 +0100759 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760
761 memset(tlb_handler, 0, sizeof(tlb_handler));
762 p = tlb_handler;
763
764 i_mfc0(&p, K0, C0_BADVADDR);
765 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */
766 i_lw(&p, K1, rel_lo(pgdc), K1);
767 i_srl(&p, K0, K0, 22); /* load delay */
768 i_sll(&p, K0, K0, 2);
769 i_addu(&p, K1, K1, K0);
770 i_mfc0(&p, K0, C0_CONTEXT);
771 i_lw(&p, K1, 0, K1); /* cp0 delay */
772 i_andi(&p, K0, K0, 0xffc); /* load delay */
773 i_addu(&p, K1, K1, K0);
774 i_lw(&p, K0, 0, K1);
775 i_nop(&p); /* load delay */
776 i_mtc0(&p, K0, C0_ENTRYLO0);
777 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
778 i_tlbwr(&p); /* cp0 delay */
779 i_jr(&p, K1);
780 i_rfe(&p); /* branch delay */
781
782 if (p > tlb_handler + 32)
783 panic("TLB refill handler space exceeded");
784
Thiemo Seufer115f2a42006-07-09 01:47:06 +0100785 pr_info("Synthesized TLB refill handler (%u instructions).\n",
786 (unsigned int)(p - tlb_handler));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787
Thiemo Seufer115f2a42006-07-09 01:47:06 +0100788 pr_debug("\t.set push\n");
789 pr_debug("\t.set noreorder\n");
790 for (i = 0; i < (p - tlb_handler); i++)
791 pr_debug("\t.word 0x%08x\n", tlb_handler[i]);
792 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793
Ralf Baechle91b05e62006-03-29 18:53:00 +0100794 memcpy((void *)ebase, tlb_handler, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795}
796
797/*
798 * The R4000 TLB handler is much more complicated. We have two
799 * consecutive handler areas with 32 instructions space each.
800 * Since they aren't used at the same time, we can overflow in the
801 * other one.To keep things simple, we first assume linear space,
802 * then we relocate it to the final handler layout as needed.
803 */
804static __initdata u32 final_handler[64];
805
806/*
807 * Hazards
808 *
809 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
810 * 2. A timing hazard exists for the TLBP instruction.
811 *
812 * stalling_instruction
813 * TLBP
814 *
815 * The JTLB is being read for the TLBP throughout the stall generated by the
816 * previous instruction. This is not really correct as the stalling instruction
817 * can modify the address used to access the JTLB. The failure symptom is that
818 * the TLBP instruction will use an address created for the stalling instruction
819 * and not the address held in C0_ENHI and thus report the wrong results.
820 *
821 * The software work-around is to not allow the instruction preceding the TLBP
822 * to stall - make it an NOP or some other instruction guaranteed not to stall.
823 *
824 * Errata 2 will not be fixed. This errata is also on the R5000.
825 *
826 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
827 */
David Rientjese8b6d402007-05-10 22:51:05 -0700828static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829{
830 switch (current_cpu_data.cputype) {
Thiemo Seuferf5b4d952005-09-09 17:11:50 +0000831 /* Found by experiment: R4600 v2.0 needs this, too. */
832 case CPU_R4600:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 case CPU_R5000:
834 case CPU_R5000A:
835 case CPU_NEVADA:
836 i_nop(p);
837 i_tlbp(p);
838 break;
839
840 default:
841 i_tlbp(p);
842 break;
843 }
844}
845
846/*
847 * Write random or indexed TLB entry, and care about the hazards from
848 * the preceeding mtc0 and for the following eret.
849 */
850enum tlb_write_entry { tlb_random, tlb_indexed };
851
852static __init void build_tlb_write_entry(u32 **p, struct label **l,
853 struct reloc **r,
854 enum tlb_write_entry wmode)
855{
856 void(*tlbw)(u32 **) = NULL;
857
858 switch (wmode) {
859 case tlb_random: tlbw = i_tlbwr; break;
860 case tlb_indexed: tlbw = i_tlbwi; break;
861 }
862
863 switch (current_cpu_data.cputype) {
864 case CPU_R4000PC:
865 case CPU_R4000SC:
866 case CPU_R4000MC:
867 case CPU_R4400PC:
868 case CPU_R4400SC:
869 case CPU_R4400MC:
870 /*
871 * This branch uses up a mtc0 hazard nop slot and saves
872 * two nops after the tlbw instruction.
873 */
874 il_bgezl(p, r, 0, label_tlbw_hazard);
875 tlbw(p);
876 l_tlbw_hazard(l, *p);
877 i_nop(p);
878 break;
879
880 case CPU_R4600:
881 case CPU_R4700:
882 case CPU_R5000:
883 case CPU_R5000A:
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000884 i_nop(p);
885 tlbw(p);
886 i_nop(p);
887 break;
888
889 case CPU_R4300:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 case CPU_5KC:
891 case CPU_TX49XX:
892 case CPU_AU1000:
893 case CPU_AU1100:
894 case CPU_AU1500:
895 case CPU_AU1550:
Pete Popove3ad1c22005-03-01 06:33:16 +0000896 case CPU_AU1200:
Pete Popovbdf21b12005-07-14 17:47:57 +0000897 case CPU_PR4450:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 i_nop(p);
899 tlbw(p);
900 break;
901
902 case CPU_R10000:
903 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400904 case CPU_R14000:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 case CPU_4KC:
906 case CPU_SB1:
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700907 case CPU_SB1A:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908 case CPU_4KSC:
909 case CPU_20KC:
910 case CPU_25KF:
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200911 case CPU_BCM3302:
912 case CPU_BCM4710:
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800913 case CPU_LOONGSON2:
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +0100914 if (m4kc_tlbp_war())
915 i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 tlbw(p);
917 break;
918
919 case CPU_NEVADA:
920 i_nop(p); /* QED specifies 2 nops hazard */
921 /*
922 * This branch uses up a mtc0 hazard nop slot and saves
923 * a nop after the tlbw instruction.
924 */
925 il_bgezl(p, r, 0, label_tlbw_hazard);
926 tlbw(p);
927 l_tlbw_hazard(l, *p);
928 break;
929
930 case CPU_RM7000:
931 i_nop(p);
932 i_nop(p);
933 i_nop(p);
934 i_nop(p);
935 tlbw(p);
936 break;
937
938 case CPU_4KEC:
939 case CPU_24K:
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000940 case CPU_34K:
Chris Dearmanc6209532006-05-02 14:08:46 +0100941 case CPU_74K:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 i_ehb(p);
943 tlbw(p);
944 break;
945
946 case CPU_RM9000:
947 /*
948 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
949 * use of the JTLB for instructions should not occur for 4
950 * cpu cycles and use for data translations should not occur
951 * for 3 cpu cycles.
952 */
953 i_ssnop(p);
954 i_ssnop(p);
955 i_ssnop(p);
956 i_ssnop(p);
957 tlbw(p);
958 i_ssnop(p);
959 i_ssnop(p);
960 i_ssnop(p);
961 i_ssnop(p);
962 break;
963
964 case CPU_VR4111:
965 case CPU_VR4121:
966 case CPU_VR4122:
967 case CPU_VR4181:
968 case CPU_VR4181A:
969 i_nop(p);
970 i_nop(p);
971 tlbw(p);
972 i_nop(p);
973 i_nop(p);
974 break;
975
976 case CPU_VR4131:
977 case CPU_VR4133:
Ralf Baechle7623deb2005-08-29 16:49:55 +0000978 case CPU_R5432:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979 i_nop(p);
980 i_nop(p);
981 tlbw(p);
982 break;
983
984 default:
985 panic("No TLB refill handler yet (CPU type: %d)",
986 current_cpu_data.cputype);
987 break;
988 }
989}
990
Ralf Baechle875d43e2005-09-03 15:56:16 -0700991#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992/*
993 * TMP and PTR are scratch.
994 * TMP will be clobbered, PTR will hold the pmd entry.
995 */
996static __init void
997build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
998 unsigned int tmp, unsigned int ptr)
999{
1000 long pgdc = (long)pgd_current;
1001
1002 /*
1003 * The vmalloc handling is not in the hotpath.
1004 */
1005 i_dmfc0(p, tmp, C0_BADVADDR);
Atsushi Nemoto656be922006-10-26 00:08:31 +09001006#ifdef MODULE_START
1007 il_bltz(p, r, tmp, label_module_alloc);
1008#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 il_bltz(p, r, tmp, label_vmalloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +09001010#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011 /* No i_nop needed here, since the next insn doesn't touch TMP. */
1012
1013#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +01001014# ifdef CONFIG_MIPS_MT_SMTC
1015 /*
1016 * SMTC uses TCBind value as "CPU" index
1017 */
1018 i_mfc0(p, ptr, C0_TCBIND);
1019 i_dsrl(p, ptr, ptr, 19);
1020# else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 /*
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +00001022 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023 * stored in CONTEXT.
1024 */
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +00001025 i_dmfc0(p, ptr, C0_CONTEXT);
1026 i_dsrl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001027#endif
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +00001028 i_LA_mostly(p, tmp, pgdc);
1029 i_daddu(p, ptr, ptr, tmp);
1030 i_dmfc0(p, tmp, C0_BADVADDR);
1031 i_ld(p, ptr, rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032#else
1033 i_LA_mostly(p, ptr, pgdc);
1034 i_ld(p, ptr, rel_lo(pgdc), ptr);
1035#endif
1036
1037 l_vmalloc_done(l, *p);
Ralf Baechle242954b2006-10-24 02:29:01 +01001038
1039 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
1040 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
1041 else
1042 i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
1043
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
1045 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
1046 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1047 i_ld(p, ptr, 0, ptr); /* get pmd pointer */
1048 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
1049 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
1050 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
1051}
1052
1053/*
1054 * BVADDR is the faulting address, PTR is scratch.
1055 * PTR will hold the pgd for vmalloc.
1056 */
1057static __init void
1058build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1059 unsigned int bvaddr, unsigned int ptr)
1060{
1061 long swpd = (long)swapper_pg_dir;
1062
Atsushi Nemoto656be922006-10-26 00:08:31 +09001063#ifdef MODULE_START
1064 long modd = (long)module_pg_dir;
1065
1066 l_module_alloc(l, *p);
1067 /*
1068 * Assumption:
1069 * VMALLOC_START >= 0xc000000000000000UL
1070 * MODULE_START >= 0xe000000000000000UL
1071 */
1072 i_SLL(p, ptr, bvaddr, 2);
1073 il_bgez(p, r, ptr, label_vmalloc);
1074
1075 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) {
1076 i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */
1077 } else {
1078 /* unlikely configuration */
1079 i_nop(p); /* delay slot */
1080 i_LA(p, ptr, MODULE_START);
1081 }
1082 i_dsubu(p, bvaddr, bvaddr, ptr);
1083
1084 if (in_compat_space_p(modd) && !rel_lo(modd)) {
1085 il_b(p, r, label_vmalloc_done);
1086 i_lui(p, ptr, rel_hi(modd));
1087 } else {
1088 i_LA_mostly(p, ptr, modd);
1089 il_b(p, r, label_vmalloc_done);
1090 i_daddiu(p, ptr, ptr, rel_lo(modd));
1091 }
1092
1093 l_vmalloc(l, *p);
1094 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) &&
1095 MODULE_START << 32 == VMALLOC_START)
1096 i_dsll32(p, ptr, ptr, 0); /* typical case */
1097 else
1098 i_LA(p, ptr, VMALLOC_START);
1099#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 l_vmalloc(l, *p);
1101 i_LA(p, ptr, VMALLOC_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +09001102#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 i_dsubu(p, bvaddr, bvaddr, ptr);
1104
1105 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
1106 il_b(p, r, label_vmalloc_done);
1107 i_lui(p, ptr, rel_hi(swpd));
1108 } else {
1109 i_LA_mostly(p, ptr, swpd);
1110 il_b(p, r, label_vmalloc_done);
1111 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1112 }
1113}
1114
Ralf Baechle875d43e2005-09-03 15:56:16 -07001115#else /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116
1117/*
1118 * TMP and PTR are scratch.
1119 * TMP will be clobbered, PTR will hold the pgd entry.
1120 */
David Rientjese8b6d402007-05-10 22:51:05 -07001121static __init void __maybe_unused
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1123{
1124 long pgdc = (long)pgd_current;
1125
1126 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1127#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +01001128#ifdef CONFIG_MIPS_MT_SMTC
1129 /*
1130 * SMTC uses TCBind value as "CPU" index
1131 */
1132 i_mfc0(p, ptr, C0_TCBIND);
1133 i_LA_mostly(p, tmp, pgdc);
1134 i_srl(p, ptr, ptr, 19);
1135#else
1136 /*
1137 * smp_processor_id() << 3 is stored in CONTEXT.
1138 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 i_mfc0(p, ptr, C0_CONTEXT);
1140 i_LA_mostly(p, tmp, pgdc);
1141 i_srl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001142#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001143 i_addu(p, ptr, tmp, ptr);
1144#else
1145 i_LA_mostly(p, ptr, pgdc);
1146#endif
1147 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1148 i_lw(p, ptr, rel_lo(pgdc), ptr);
1149 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1150 i_sll(p, tmp, tmp, PGD_T_LOG2);
1151 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1152}
1153
Ralf Baechle875d43e2005-09-03 15:56:16 -07001154#endif /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155
1156static __init void build_adjust_context(u32 **p, unsigned int ctx)
1157{
Ralf Baechle242954b2006-10-24 02:29:01 +01001158 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1160
1161 switch (current_cpu_data.cputype) {
1162 case CPU_VR41XX:
1163 case CPU_VR4111:
1164 case CPU_VR4121:
1165 case CPU_VR4122:
1166 case CPU_VR4131:
1167 case CPU_VR4181:
1168 case CPU_VR4181A:
1169 case CPU_VR4133:
1170 shift += 2;
1171 break;
1172
1173 default:
1174 break;
1175 }
1176
1177 if (shift)
1178 i_SRL(p, ctx, ctx, shift);
1179 i_andi(p, ctx, ctx, mask);
1180}
1181
1182static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1183{
1184 /*
1185 * Bug workaround for the Nevada. It seems as if under certain
1186 * circumstances the move from cp0_context might produce a
1187 * bogus result when the mfc0 instruction and its consumer are
1188 * in a different cacheline or a load instruction, probably any
1189 * memory reference, is between them.
1190 */
1191 switch (current_cpu_data.cputype) {
1192 case CPU_NEVADA:
1193 i_LW(p, ptr, 0, ptr);
1194 GET_CONTEXT(p, tmp); /* get context reg */
1195 break;
1196
1197 default:
1198 GET_CONTEXT(p, tmp); /* get context reg */
1199 i_LW(p, ptr, 0, ptr);
1200 break;
1201 }
1202
1203 build_adjust_context(p, tmp);
1204 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1205}
1206
1207static __init void build_update_entries(u32 **p, unsigned int tmp,
1208 unsigned int ptep)
1209{
1210 /*
1211 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1212 * Kernel is a special case. Only a few CPUs use it.
1213 */
1214#ifdef CONFIG_64BIT_PHYS_ADDR
1215 if (cpu_has_64bits) {
1216 i_ld(p, tmp, 0, ptep); /* get even pte */
1217 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1218 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
1219 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1220 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
1221 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1222 } else {
1223 int pte_off_even = sizeof(pte_t) / 2;
1224 int pte_off_odd = pte_off_even + sizeof(pte_t);
1225
1226 /* The pte entries are pre-shifted */
1227 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1228 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1229 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1230 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1231 }
1232#else
1233 i_LW(p, tmp, 0, ptep); /* get even pte */
1234 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1235 if (r45k_bvahwbug())
1236 build_tlb_probe_entry(p);
1237 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
1238 if (r4k_250MHZhwbug())
1239 i_mtc0(p, 0, C0_ENTRYLO0);
1240 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1241 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
1242 if (r45k_bvahwbug())
1243 i_mfc0(p, tmp, C0_INDEX);
1244 if (r4k_250MHZhwbug())
1245 i_mtc0(p, 0, C0_ENTRYLO1);
1246 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1247#endif
1248}
1249
1250static void __init build_r4000_tlb_refill_handler(void)
1251{
1252 u32 *p = tlb_handler;
1253 struct label *l = labels;
1254 struct reloc *r = relocs;
1255 u32 *f;
1256 unsigned int final_len;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001257 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258
1259 memset(tlb_handler, 0, sizeof(tlb_handler));
1260 memset(labels, 0, sizeof(labels));
1261 memset(relocs, 0, sizeof(relocs));
1262 memset(final_handler, 0, sizeof(final_handler));
1263
1264 /*
1265 * create the plain linear handler
1266 */
1267 if (bcm1250_m3_war()) {
1268 i_MFC0(&p, K0, C0_BADVADDR);
1269 i_MFC0(&p, K1, C0_ENTRYHI);
1270 i_xor(&p, K0, K0, K1);
1271 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1272 il_bnez(&p, &r, K0, label_leave);
1273 /* No need for i_nop */
1274 }
1275
Ralf Baechle875d43e2005-09-03 15:56:16 -07001276#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1278#else
1279 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1280#endif
1281
1282 build_get_ptep(&p, K0, K1);
1283 build_update_entries(&p, K0, K1);
1284 build_tlb_write_entry(&p, &l, &r, tlb_random);
1285 l_leave(&l, p);
1286 i_eret(&p); /* return from trap */
1287
Ralf Baechle875d43e2005-09-03 15:56:16 -07001288#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1290#endif
1291
1292 /*
1293 * Overflow check: For the 64bit handler, we need at least one
1294 * free instruction slot for the wrap-around branch. In worst
1295 * case, if the intended insertion point is a delay slot, we
Matt LaPlante4b3f6862006-10-03 22:21:02 +02001296 * need three, with the second nop'ed and the third being
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297 * unused.
1298 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001299 /* Loongson2 ebase is different than r4k, we have more space */
1300#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001301 if ((p - tlb_handler) > 64)
1302 panic("TLB refill handler space exceeded");
1303#else
1304 if (((p - tlb_handler) > 63)
1305 || (((p - tlb_handler) > 61)
1306 && insn_has_bdelay(relocs, tlb_handler + 29)))
1307 panic("TLB refill handler space exceeded");
1308#endif
1309
1310 /*
1311 * Now fold the handler in the TLB refill handler space.
1312 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001313#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314 f = final_handler;
1315 /* Simplest case, just copy the handler. */
1316 copy_handler(relocs, labels, tlb_handler, p, f);
1317 final_len = p - tlb_handler;
Ralf Baechle875d43e2005-09-03 15:56:16 -07001318#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 f = final_handler + 32;
1320 if ((p - tlb_handler) <= 32) {
1321 /* Just copy the handler. */
1322 copy_handler(relocs, labels, tlb_handler, p, f);
1323 final_len = p - tlb_handler;
1324 } else {
1325 u32 *split = tlb_handler + 30;
1326
1327 /*
1328 * Find the split point.
1329 */
1330 if (insn_has_bdelay(relocs, split - 1))
1331 split--;
1332
1333 /* Copy first part of the handler. */
1334 copy_handler(relocs, labels, tlb_handler, split, f);
1335 f += split - tlb_handler;
1336
1337 /* Insert branch. */
1338 l_split(&l, final_handler);
1339 il_b(&f, &r, label_split);
1340 if (insn_has_bdelay(relocs, split))
1341 i_nop(&f);
1342 else {
1343 copy_handler(relocs, labels, split, split + 1, f);
1344 move_labels(labels, f, f + 1, -1);
1345 f++;
1346 split++;
1347 }
1348
1349 /* Copy the rest of the handler. */
1350 copy_handler(relocs, labels, split, p, final_handler);
1351 final_len = (f - (final_handler + 32)) + (p - split);
1352 }
Ralf Baechle875d43e2005-09-03 15:56:16 -07001353#endif /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
1355 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001356 pr_info("Synthesized TLB refill handler (%u instructions).\n",
1357 final_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001359 f = final_handler;
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001360#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2)
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001361 if (final_len > 32)
1362 final_len = 64;
1363 else
1364 f = final_handler + 32;
Maciej W. Rozycki4c0a2d42005-06-29 10:43:51 +00001365#endif /* CONFIG_64BIT */
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001366 pr_debug("\t.set push\n");
1367 pr_debug("\t.set noreorder\n");
1368 for (i = 0; i < final_len; i++)
1369 pr_debug("\t.word 0x%08x\n", f[i]);
1370 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371
Ralf Baechle91b05e62006-03-29 18:53:00 +01001372 memcpy((void *)ebase, final_handler, 0x100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373}
1374
1375/*
1376 * TLB load/store/modify handlers.
1377 *
1378 * Only the fastpath gets synthesized at runtime, the slowpath for
1379 * do_page_fault remains normal asm.
1380 */
1381extern void tlb_do_page_fault_0(void);
1382extern void tlb_do_page_fault_1(void);
1383
1384#define __tlb_handler_align \
1385 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1386
1387/*
1388 * 128 instructions for the fastpath handler is generous and should
1389 * never be exceeded.
1390 */
1391#define FASTPATH_SIZE 128
1392
1393u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
1394u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1395u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1396
1397static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001398iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399{
1400#ifdef CONFIG_SMP
1401# ifdef CONFIG_64BIT_PHYS_ADDR
1402 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001403 i_lld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404 else
1405# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001406 i_LL(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407#else
1408# ifdef CONFIG_64BIT_PHYS_ADDR
1409 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001410 i_ld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411 else
1412# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001413 i_LW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414#endif
1415}
1416
1417static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001418iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
1419 unsigned int mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001421#ifdef CONFIG_64BIT_PHYS_ADDR
1422 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1423#endif
1424
1425 i_ori(p, pte, pte, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426#ifdef CONFIG_SMP
1427# ifdef CONFIG_64BIT_PHYS_ADDR
1428 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001429 i_scd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430 else
1431# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001432 i_SC(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433
1434 if (r10000_llsc_war())
1435 il_beqzl(p, r, pte, label_smp_pgtable_change);
1436 else
1437 il_beqz(p, r, pte, label_smp_pgtable_change);
1438
1439# ifdef CONFIG_64BIT_PHYS_ADDR
1440 if (!cpu_has_64bits) {
1441 /* no i_nop needed */
1442 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001443 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1445 il_beqz(p, r, pte, label_smp_pgtable_change);
1446 /* no i_nop needed */
1447 i_lw(p, pte, 0, ptr);
1448 } else
1449 i_nop(p);
1450# else
1451 i_nop(p);
1452# endif
1453#else
1454# ifdef CONFIG_64BIT_PHYS_ADDR
1455 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001456 i_sd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 else
1458# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001459 i_SW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460
1461# ifdef CONFIG_64BIT_PHYS_ADDR
1462 if (!cpu_has_64bits) {
1463 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001464 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1466 i_lw(p, pte, 0, ptr);
1467 }
1468# endif
1469#endif
1470}
1471
1472/*
1473 * Check if PTE is present, if not then jump to LABEL. PTR points to
1474 * the page table where this PTE is located, PTE will be re-loaded
1475 * with it's original value.
1476 */
1477static void __init
1478build_pte_present(u32 **p, struct label **l, struct reloc **r,
1479 unsigned int pte, unsigned int ptr, enum label_id lid)
1480{
1481 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1482 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1483 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001484 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001485}
1486
1487/* Make PTE valid, store result in PTR. */
1488static void __init
1489build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1490 unsigned int ptr)
1491{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001492 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1493
1494 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495}
1496
1497/*
1498 * Check if PTE can be written to, if not branch to LABEL. Regardless
1499 * restore PTE with value from PTR when done.
1500 */
1501static void __init
1502build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1503 unsigned int pte, unsigned int ptr, enum label_id lid)
1504{
1505 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1506 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1507 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001508 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509}
1510
1511/* Make PTE writable, update software status bits as well, then store
1512 * at PTR.
1513 */
1514static void __init
1515build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1516 unsigned int ptr)
1517{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001518 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1519 | _PAGE_DIRTY);
1520
1521 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522}
1523
1524/*
1525 * Check if PTE can be modified, if not branch to LABEL. Regardless
1526 * restore PTE with value from PTR when done.
1527 */
1528static void __init
1529build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1530 unsigned int pte, unsigned int ptr, enum label_id lid)
1531{
1532 i_andi(p, pte, pte, _PAGE_WRITE);
1533 il_beqz(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001534 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535}
1536
1537/*
1538 * R3000 style TLB load/store/modify handlers.
1539 */
1540
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001541/*
1542 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1543 * Then it returns.
1544 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545static void __init
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001546build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547{
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001548 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1549 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1550 i_tlbwi(p);
1551 i_jr(p, tmp);
1552 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553}
1554
1555/*
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001556 * This places the pte into ENTRYLO0 and writes it with tlbwi
1557 * or tlbwr as appropriate. This is because the index register
1558 * may have the probe fail bit set as a result of a trap on a
1559 * kseg2 access, i.e. without refill. Then it returns.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560 */
1561static void __init
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001562build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
1563 unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564{
1565 i_mfc0(p, tmp, C0_INDEX);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001566 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1567 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1568 i_mfc0(p, tmp, C0_EPC); /* branch delay */
1569 i_tlbwi(p); /* cp0 delay */
1570 i_jr(p, tmp);
1571 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001572 l_r3000_write_probe_fail(l, *p);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001573 i_tlbwr(p); /* cp0 delay */
1574 i_jr(p, tmp);
1575 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576}
1577
1578static void __init
1579build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1580 unsigned int ptr)
1581{
1582 long pgdc = (long)pgd_current;
1583
1584 i_mfc0(p, pte, C0_BADVADDR);
1585 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */
1586 i_lw(p, ptr, rel_lo(pgdc), ptr);
1587 i_srl(p, pte, pte, 22); /* load delay */
1588 i_sll(p, pte, pte, 2);
1589 i_addu(p, ptr, ptr, pte);
1590 i_mfc0(p, pte, C0_CONTEXT);
1591 i_lw(p, ptr, 0, ptr); /* cp0 delay */
1592 i_andi(p, pte, pte, 0xffc); /* load delay */
1593 i_addu(p, ptr, ptr, pte);
1594 i_lw(p, pte, 0, ptr);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001595 i_tlbp(p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596}
1597
1598static void __init build_r3000_tlb_load_handler(void)
1599{
1600 u32 *p = handle_tlbl;
1601 struct label *l = labels;
1602 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001603 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604
1605 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1606 memset(labels, 0, sizeof(labels));
1607 memset(relocs, 0, sizeof(relocs));
1608
1609 build_r3000_tlbchange_handler_head(&p, K0, K1);
1610 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001611 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612 build_make_valid(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001613 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614
1615 l_nopage_tlbl(&l, p);
1616 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1617 i_nop(&p);
1618
1619 if ((p - handle_tlbl) > FASTPATH_SIZE)
1620 panic("TLB load handler fastpath space exceeded");
1621
1622 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001623 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n",
1624 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001626 pr_debug("\t.set push\n");
1627 pr_debug("\t.set noreorder\n");
1628 for (i = 0; i < (p - handle_tlbl); i++)
1629 pr_debug("\t.word 0x%08x\n", handle_tlbl[i]);
1630 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631}
1632
1633static void __init build_r3000_tlb_store_handler(void)
1634{
1635 u32 *p = handle_tlbs;
1636 struct label *l = labels;
1637 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001638 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001639
1640 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1641 memset(labels, 0, sizeof(labels));
1642 memset(relocs, 0, sizeof(relocs));
1643
1644 build_r3000_tlbchange_handler_head(&p, K0, K1);
1645 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001646 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001648 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649
1650 l_nopage_tlbs(&l, p);
1651 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1652 i_nop(&p);
1653
1654 if ((p - handle_tlbs) > FASTPATH_SIZE)
1655 panic("TLB store handler fastpath space exceeded");
1656
1657 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001658 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n",
1659 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001660
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001661 pr_debug("\t.set push\n");
1662 pr_debug("\t.set noreorder\n");
1663 for (i = 0; i < (p - handle_tlbs); i++)
1664 pr_debug("\t.word 0x%08x\n", handle_tlbs[i]);
1665 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666}
1667
1668static void __init build_r3000_tlb_modify_handler(void)
1669{
1670 u32 *p = handle_tlbm;
1671 struct label *l = labels;
1672 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001673 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674
1675 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1676 memset(labels, 0, sizeof(labels));
1677 memset(relocs, 0, sizeof(relocs));
1678
1679 build_r3000_tlbchange_handler_head(&p, K0, K1);
1680 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001681 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001683 build_r3000_pte_reload_tlbwi(&p, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684
1685 l_nopage_tlbm(&l, p);
1686 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1687 i_nop(&p);
1688
1689 if ((p - handle_tlbm) > FASTPATH_SIZE)
1690 panic("TLB modify handler fastpath space exceeded");
1691
1692 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001693 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n",
1694 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001696 pr_debug("\t.set push\n");
1697 pr_debug("\t.set noreorder\n");
1698 for (i = 0; i < (p - handle_tlbm); i++)
1699 pr_debug("\t.word 0x%08x\n", handle_tlbm[i]);
1700 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701}
1702
1703/*
1704 * R4000 style TLB load/store/modify handlers.
1705 */
1706static void __init
1707build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1708 struct reloc **r, unsigned int pte,
1709 unsigned int ptr)
1710{
Ralf Baechle875d43e2005-09-03 15:56:16 -07001711#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001712 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1713#else
1714 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1715#endif
1716
1717 i_MFC0(p, pte, C0_BADVADDR);
1718 i_LW(p, ptr, 0, ptr);
1719 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1720 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1721 i_ADDU(p, ptr, ptr, pte);
1722
1723#ifdef CONFIG_SMP
1724 l_smp_pgtable_change(l, *p);
1725# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001726 iPTE_LW(p, l, pte, ptr); /* get even pte */
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001727 if (!m4kc_tlbp_war())
1728 build_tlb_probe_entry(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729}
1730
1731static void __init
1732build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1733 struct reloc **r, unsigned int tmp,
1734 unsigned int ptr)
1735{
1736 i_ori(p, ptr, ptr, sizeof(pte_t));
1737 i_xori(p, ptr, ptr, sizeof(pte_t));
1738 build_update_entries(p, tmp, ptr);
1739 build_tlb_write_entry(p, l, r, tlb_indexed);
1740 l_leave(l, *p);
1741 i_eret(p); /* return from trap */
1742
Ralf Baechle875d43e2005-09-03 15:56:16 -07001743#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1745#endif
1746}
1747
1748static void __init build_r4000_tlb_load_handler(void)
1749{
1750 u32 *p = handle_tlbl;
1751 struct label *l = labels;
1752 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001753 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001754
1755 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1756 memset(labels, 0, sizeof(labels));
1757 memset(relocs, 0, sizeof(relocs));
1758
1759 if (bcm1250_m3_war()) {
1760 i_MFC0(&p, K0, C0_BADVADDR);
1761 i_MFC0(&p, K1, C0_ENTRYHI);
1762 i_xor(&p, K0, K0, K1);
1763 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1764 il_bnez(&p, &r, K0, label_leave);
1765 /* No need for i_nop */
1766 }
1767
1768 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1769 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001770 if (m4kc_tlbp_war())
1771 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772 build_make_valid(&p, &r, K0, K1);
1773 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1774
1775 l_nopage_tlbl(&l, p);
1776 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1777 i_nop(&p);
1778
1779 if ((p - handle_tlbl) > FASTPATH_SIZE)
1780 panic("TLB load handler fastpath space exceeded");
1781
1782 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001783 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n",
1784 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001786 pr_debug("\t.set push\n");
1787 pr_debug("\t.set noreorder\n");
1788 for (i = 0; i < (p - handle_tlbl); i++)
1789 pr_debug("\t.word 0x%08x\n", handle_tlbl[i]);
1790 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791}
1792
1793static void __init build_r4000_tlb_store_handler(void)
1794{
1795 u32 *p = handle_tlbs;
1796 struct label *l = labels;
1797 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001798 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001799
1800 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1801 memset(labels, 0, sizeof(labels));
1802 memset(relocs, 0, sizeof(relocs));
1803
1804 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1805 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001806 if (m4kc_tlbp_war())
1807 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808 build_make_write(&p, &r, K0, K1);
1809 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1810
1811 l_nopage_tlbs(&l, p);
1812 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1813 i_nop(&p);
1814
1815 if ((p - handle_tlbs) > FASTPATH_SIZE)
1816 panic("TLB store handler fastpath space exceeded");
1817
1818 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001819 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n",
1820 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001822 pr_debug("\t.set push\n");
1823 pr_debug("\t.set noreorder\n");
1824 for (i = 0; i < (p - handle_tlbs); i++)
1825 pr_debug("\t.word 0x%08x\n", handle_tlbs[i]);
1826 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001827}
1828
1829static void __init build_r4000_tlb_modify_handler(void)
1830{
1831 u32 *p = handle_tlbm;
1832 struct label *l = labels;
1833 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001834 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835
1836 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1837 memset(labels, 0, sizeof(labels));
1838 memset(relocs, 0, sizeof(relocs));
1839
1840 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1841 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001842 if (m4kc_tlbp_war())
1843 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001844 /* Present and writable bits set, set accessed and dirty bits. */
1845 build_make_write(&p, &r, K0, K1);
1846 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1847
1848 l_nopage_tlbm(&l, p);
1849 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1850 i_nop(&p);
1851
1852 if ((p - handle_tlbm) > FASTPATH_SIZE)
1853 panic("TLB modify handler fastpath space exceeded");
1854
1855 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001856 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n",
1857 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001859 pr_debug("\t.set push\n");
1860 pr_debug("\t.set noreorder\n");
1861 for (i = 0; i < (p - handle_tlbm); i++)
1862 pr_debug("\t.word 0x%08x\n", handle_tlbm[i]);
1863 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864}
1865
1866void __init build_tlb_refill_handler(void)
1867{
1868 /*
1869 * The refill handler is generated per-CPU, multi-node systems
1870 * may have local storage for it. The other handlers are only
1871 * needed once.
1872 */
1873 static int run_once = 0;
1874
1875 switch (current_cpu_data.cputype) {
1876 case CPU_R2000:
1877 case CPU_R3000:
1878 case CPU_R3000A:
1879 case CPU_R3081E:
1880 case CPU_TX3912:
1881 case CPU_TX3922:
1882 case CPU_TX3927:
1883 build_r3000_tlb_refill_handler();
1884 if (!run_once) {
1885 build_r3000_tlb_load_handler();
1886 build_r3000_tlb_store_handler();
1887 build_r3000_tlb_modify_handler();
1888 run_once++;
1889 }
1890 break;
1891
1892 case CPU_R6000:
1893 case CPU_R6000A:
1894 panic("No R6000 TLB refill handler yet");
1895 break;
1896
1897 case CPU_R8000:
1898 panic("No R8000 TLB refill handler yet");
1899 break;
1900
1901 default:
1902 build_r4000_tlb_refill_handler();
1903 if (!run_once) {
1904 build_r4000_tlb_load_handler();
1905 build_r4000_tlb_store_handler();
1906 build_r4000_tlb_modify_handler();
1907 run_once++;
1908 }
1909 }
1910}
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001911
1912void __init flush_tlb_handlers(void)
1913{
1914 flush_icache_range((unsigned long)handle_tlbl,
1915 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1916 flush_icache_range((unsigned long)handle_tlbs,
1917 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1918 flush_icache_range((unsigned long)handle_tlbm,
1919 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1920}