blob: 3377e66de9eb350892f2c6bf9007c583b23672e3 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/tty.h>
24
25#ifdef CONFIG_MTD
26#include <linux/mtd/partitions.h>
27#include <linux/mtd/physmap.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/map.h>
30#endif
31
32#include <asm/cpu.h>
33#include <asm/bootinfo.h>
34#include <asm/irq.h>
35#include <asm/mips-boards/generic.h>
36#include <asm/mips-boards/prom.h>
37#include <asm/mips-boards/malta.h>
38#include <asm/mips-boards/maltaint.h>
39#include <asm/dma.h>
40#include <asm/time.h>
41#include <asm/traps.h>
42#ifdef CONFIG_VT
43#include <linux/console.h>
44#endif
45
46extern void mips_reboot_setup(void);
47extern void mips_time_init(void);
48extern void mips_timer_setup(struct irqaction *irq);
49extern unsigned long mips_rtc_get_time(void);
50
51#ifdef CONFIG_KGDB
52extern void kgdb_config(void);
53#endif
54
55struct resource standard_io_resources[] = {
56 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
57 { "timer", 0x40, 0x5f, IORESOURCE_BUSY },
58 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
59 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
60 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
61};
62
63#ifdef CONFIG_MTD
64static struct mtd_partition malta_mtd_partitions[] = {
65 {
66 .name = "YAMON",
67 .offset = 0x0,
68 .size = 0x100000,
69 .mask_flags = MTD_WRITEABLE
70 },
71 {
72 .name = "User FS",
73 .offset = 0x100000,
74 .size = 0x2e0000
75 },
76 {
77 .name = "Board Config",
78 .offset = 0x3e0000,
79 .size = 0x020000,
80 .mask_flags = MTD_WRITEABLE
81 }
82};
83
84#define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
85#endif
86
87const char *get_system_type(void)
88{
89 return "MIPS Malta";
90}
91
92#ifdef CONFIG_BLK_DEV_FD
93void __init fd_activate(void)
94{
95 /*
96 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
97 * Controller.
98 * Done by YAMON 2.00 onwards
99 */
100 /* Entering config state. */
101 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
102
103 /* Activate floppy controller. */
104 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
105 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
106 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
107 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
108
109 /* Exit config state. */
110 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
111}
112#endif
113
114static int __init malta_setup(void)
115{
116 unsigned int i;
117
118 /* Request I/O space for devices used on the Malta board. */
119 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
120 request_resource(&ioport_resource, standard_io_resources+i);
121
122 /*
123 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
124 */
125 enable_dma(4);
126
127#ifdef CONFIG_KGDB
128 kgdb_config ();
129#endif
130
131 if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
132 (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
133 (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
134 char *argptr;
135
136 argptr = prom_getcmdline();
137 if (strstr(argptr, "debug")) {
138 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
139 printk ("Enabled Bonito debug mode\n");
140 }
141 else
142 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
143
144#ifdef CONFIG_DMA_COHERENT
145 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
146 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
147 printk("Enabled Bonito CPU coherency\n");
148
149 argptr = prom_getcmdline();
150 if (strstr(argptr, "iobcuncached")) {
151 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
152 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
153 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
154 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
155 printk("Disabled Bonito IOBC coherency\n");
156 }
157 else {
158 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
159 BONITO_PCIMEMBASECFG |=
160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
162 printk("Disabled Bonito IOBC coherency\n");
163 }
164 }
165 else
166 panic("Hardware DMA cache coherency not supported");
167
168#endif
169 }
170#ifdef CONFIG_DMA_COHERENT
171 else {
172 panic("Hardware DMA cache coherency not supported");
173 }
174#endif
175
176#ifdef CONFIG_BLK_DEV_IDE
177 /* Check PCI clock */
178 {
179 int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
180 static const int pciclocks[] __initdata = {
181 33, 20, 25, 30, 12, 16, 37, 10
182 };
183 int pciclock = pciclocks[jmpr];
184 char *argptr = prom_getcmdline();
185
186 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
187 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
188 argptr += strlen(argptr);
189 sprintf (argptr, " idebus=%d", pciclock);
190 if (pciclock < 20 || pciclock > 66)
191 printk ("WARNING: IDE timing calculations will be incorrect\n");
192 }
193 }
194#endif
195#ifdef CONFIG_BLK_DEV_FD
196 fd_activate ();
197#endif
198#ifdef CONFIG_VT
199#if defined(CONFIG_VGA_CONSOLE)
200 screen_info = (struct screen_info) {
201 0, 25, /* orig-x, orig-y */
202 0, /* unused */
203 0, /* orig-video-page */
204 0, /* orig-video-mode */
205 80, /* orig-video-cols */
206 0,0,0, /* ega_ax, ega_bx, ega_cx */
207 25, /* orig-video-lines */
208 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
209 16 /* orig-video-points */
210 };
211#endif
212#endif
213
214#ifdef CONFIG_MTD
215 /*
216 * Support for MTD on Malta. Use the generic physmap driver
217 */
218 physmap_configure(0x1e000000, 0x400000, 4, NULL);
219 physmap_set_partitions(malta_mtd_partitions, number_partitions);
220#endif
221
222 mips_reboot_setup();
223
224 board_time_init = mips_time_init;
225 board_timer_setup = mips_timer_setup;
226 rtc_get_time = mips_rtc_get_time;
227
228 return 0;
229}
230
231early_initcall(malta_setup);