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gerrit-public.fairphone.software / kernel / msm-4.19 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / arch / ppc / platforms / 4xx / ibm405ep.c
blob: 6d44567f4dd215ad6f2554eff26a2d84fc5ca25d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*
2 * arch/ppc/platforms/ibm405ep.c
3 *
4 * Support for IBM PPC 405EP processors.
5 *
6 * Author: SAW (IBM), derived from ibmnp405l.c.
7 * Maintained by MontaVista Software <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#include <linux/config.h>
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/threads.h>
19#include <linux/param.h>
20#include <linux/string.h>
21
22#include <asm/ibm4xx.h>
23#include <asm/ocp.h>
24#include <asm/ppc4xx_pic.h>
25
26#include <platforms/4xx/ibm405ep.h>
27
28static struct ocp_func_mal_data ibm405ep_mal0_def = {
29 .num_tx_chans = 4, /* Number of TX channels */
30 .num_rx_chans = 2, /* Number of RX channels */
31 .txeob_irq = 11, /* TX End Of Buffer IRQ */
32 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
33 .txde_irq = 13, /* TX Descriptor Error IRQ */
34 .rxde_irq = 14, /* RX Descriptor Error IRQ */
35 .serr_irq = 10, /* MAL System Error IRQ */
36};
37OCP_SYSFS_MAL_DATA()
38
39static struct ocp_func_emac_data ibm405ep_emac0_def = {
40 .rgmii_idx = -1, /* No RGMII */
41 .rgmii_mux = -1, /* No RGMII */
42 .zmii_idx = -1, /* ZMII device index */
43 .zmii_mux = 0, /* ZMII input of this EMAC */
44 .mal_idx = 0, /* MAL device index */
45 .mal_rx_chan = 0, /* MAL rx channel number */
46 .mal_tx_chan = 0, /* MAL tx channel number */
47 .wol_irq = 9, /* WOL interrupt number */
48 .mdio_idx = 0, /* MDIO via EMAC0 */
49 .tah_idx = -1, /* No TAH */
50};
51
52static struct ocp_func_emac_data ibm405ep_emac1_def = {
53 .rgmii_idx = -1, /* No RGMII */
54 .rgmii_mux = -1, /* No RGMII */
55 .zmii_idx = -1, /* ZMII device index */
56 .zmii_mux = 0, /* ZMII input of this EMAC */
57 .mal_idx = 0, /* MAL device index */
58 .mal_rx_chan = 1, /* MAL rx channel number */
59 .mal_tx_chan = 2, /* MAL tx channel number */
60 .wol_irq = 9, /* WOL interrupt number */
61 .mdio_idx = 0, /* MDIO via EMAC0 */
62 .tah_idx = -1, /* No TAH */
63};
64OCP_SYSFS_EMAC_DATA()
65
66static struct ocp_func_iic_data ibm405ep_iic0_def = {
67 .fast_mode = 0, /* Use standad mode (100Khz) */
68};
69OCP_SYSFS_IIC_DATA()
70
71struct ocp_def core_ocp[] = {
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_OPB,
74 .index = 0,
75 .paddr = 0xEF600000,
76 .irq = OCP_IRQ_NA,
77 .pm = OCP_CPM_NA,
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_16550,
81 .index = 0,
82 .paddr = UART0_IO_BASE,
83 .irq = UART0_INT,
84 .pm = IBM_CPM_UART0
85 },
86 { .vendor = OCP_VENDOR_IBM,
87 .function = OCP_FUNC_16550,
88 .index = 1,
89 .paddr = UART1_IO_BASE,
90 .irq = UART1_INT,
91 .pm = IBM_CPM_UART1
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .paddr = 0xEF600500,
96 .irq = 2,
97 .pm = IBM_CPM_IIC0,
98 .additions = &ibm405ep_iic0_def,
99 .show = &ocp_show_iic_data
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_GPIO,
103 .paddr = 0xEF600700,
104 .irq = OCP_IRQ_NA,
105 .pm = IBM_CPM_GPIO0
106 },
107 { .vendor = OCP_VENDOR_IBM,
108 .function = OCP_FUNC_MAL,
109 .paddr = OCP_PADDR_NA,
110 .irq = OCP_IRQ_NA,
111 .pm = OCP_CPM_NA,
112 .additions = &ibm405ep_mal0_def,
113 .show = &ocp_show_mal_data
114 },
115 { .vendor = OCP_VENDOR_IBM,
116 .function = OCP_FUNC_EMAC,
117 .index = 0,
118 .paddr = EMAC0_BASE,
119 .irq = 15,
120 .pm = OCP_CPM_NA,
121 .additions = &ibm405ep_emac0_def,
122 .show = &ocp_show_emac_data
123 },
124 { .vendor = OCP_VENDOR_IBM,
125 .function = OCP_FUNC_EMAC,
126 .index = 1,
127 .paddr = 0xEF600900,
128 .irq = 17,
129 .pm = OCP_CPM_NA,
130 .additions = &ibm405ep_emac1_def,
131 .show = &ocp_show_emac_data
132 },
133 { .vendor = OCP_VENDOR_INVALID
134 }
135};
136
137/* Polarity and triggering settings for internal interrupt sources */
138struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
139 { .polarity = 0xffff7f80,
140 .triggering = 0x00000000,
141 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
142 }
143};