| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * linux/drivers/video/retz3fb.h -- Defines and macros for the RetinaZ3 frame |
| 3 | * buffer device |
| 4 | * |
| 5 | * Copyright (C) 1997 Jes Sorensen |
| 6 | * |
| 7 | * History: |
| 8 | * - 22 Jan 97: Initial work |
| 9 | * |
| 10 | * |
| 11 | * This file is subject to the terms and conditions of the GNU General Public |
| 12 | * License. See the file COPYING in the main directory of this archive |
| 13 | * for more details. |
| 14 | */ |
| 15 | |
| 16 | /* |
| 17 | * Macros to read and write to registers. |
| 18 | */ |
| 19 | #define reg_w(regs, reg,dat) (*(regs + reg) = dat) |
| 20 | #define reg_r(regs, reg) (*(regs + reg)) |
| 21 | |
| 22 | /* |
| 23 | * Macro to access the sequencer. |
| 24 | */ |
| 25 | #define seq_w(regs, sreg, sdat) \ |
| 26 | do{ reg_w(regs, SEQ_IDX, sreg); reg_w(regs, SEQ_DATA, sdat); } while(0) |
| 27 | |
| 28 | /* |
| 29 | * Macro to access the CRT controller. |
| 30 | */ |
| 31 | #define crt_w(regs, creg, cdat) \ |
| 32 | do{ reg_w(regs, CRT_IDX, creg); reg_w(regs, CRT_DATA, cdat); } while(0) |
| 33 | |
| 34 | /* |
| 35 | * Macro to access the graphics controller. |
| 36 | */ |
| 37 | #define gfx_w(regs, greg, gdat) \ |
| 38 | do{ reg_w(regs, GFX_IDX, greg); reg_w(regs, GFX_DATA, gdat); } while(0) |
| 39 | |
| 40 | /* |
| 41 | * Macro to access the attribute controller. |
| 42 | */ |
| 43 | #define attr_w(regs, areg, adat) \ |
| 44 | do{ reg_w(regs, ACT_IDX, areg); reg_w(regs, ACT_DATA, adat); } while(0) |
| 45 | |
| 46 | /* |
| 47 | * Macro to access the pll. |
| 48 | */ |
| 49 | #define pll_w(regs, preg, pdat) \ |
| 50 | do{ reg_w(regs, PLL_IDX, preg); \ |
| 51 | reg_w(regs, PLL_DATA, (pdat & 0xff)); \ |
| 52 | reg_w(regs, PLL_DATA, (pdat >> 8));\ |
| 53 | } while(0) |
| 54 | |
| 55 | /* |
| 56 | * Offsets |
| 57 | */ |
| 58 | #define VIDEO_MEM_OFFSET 0x00c00000 |
| 59 | #define ACM_OFFSET 0x00b00000 |
| 60 | |
| 61 | /* |
| 62 | * Accelerator Control Menu |
| 63 | */ |
| 64 | #define ACM_PRIMARY_OFFSET 0x00 |
| 65 | #define ACM_SECONDARY_OFFSET 0x04 |
| 66 | #define ACM_MODE_CONTROL 0x08 |
| 67 | #define ACM_CURSOR_POSITION 0x0c |
| 68 | #define ACM_START_STATUS 0x30 |
| 69 | #define ACM_CONTROL 0x34 |
| 70 | #define ACM_RASTEROP_ROTATION 0x38 |
| 71 | #define ACM_BITMAP_DIMENSION 0x3c |
| 72 | #define ACM_DESTINATION 0x40 |
| 73 | #define ACM_SOURCE 0x44 |
| 74 | #define ACM_PATTERN 0x48 |
| 75 | #define ACM_FOREGROUND 0x4c |
| 76 | #define ACM_BACKGROUND 0x50 |
| 77 | |
| 78 | /* |
| 79 | * Video DAC addresses |
| 80 | */ |
| 81 | #define VDAC_ADDRESS 0x03c8 |
| 82 | #define VDAC_ADDRESS_W 0x03c8 |
| 83 | #define VDAC_ADDRESS_R 0x03c7 |
| 84 | #define VDAC_STATE 0x03c7 |
| 85 | #define VDAC_DATA 0x03c9 |
| 86 | #define VDAC_MASK 0x03c6 |
| 87 | |
| 88 | /* |
| 89 | * Sequencer |
| 90 | */ |
| 91 | #define SEQ_IDX 0x03c4 /* Sequencer Index */ |
| 92 | #define SEQ_DATA 0x03c5 |
| 93 | #define SEQ_RESET 0x00 |
| 94 | #define SEQ_CLOCKING_MODE 0x01 |
| 95 | #define SEQ_MAP_MASK 0x02 |
| 96 | #define SEQ_CHAR_MAP_SELECT 0x03 |
| 97 | #define SEQ_MEMORY_MODE 0x04 |
| 98 | #define SEQ_EXTENDED_ENABLE 0x05 /* NCR extensions */ |
| 99 | #define SEQ_UNKNOWN1 0x06 |
| 100 | #define SEQ_UNKNOWN2 0x07 |
| 101 | #define SEQ_CHIP_ID 0x08 |
| 102 | #define SEQ_UNKNOWN3 0x09 |
| 103 | #define SEQ_CURSOR_COLOR1 0x0a |
| 104 | #define SEQ_CURSOR_COLOR0 0x0b |
| 105 | #define SEQ_CURSOR_CONTROL 0x0c |
| 106 | #define SEQ_CURSOR_X_LOC_HI 0x0d |
| 107 | #define SEQ_CURSOR_X_LOC_LO 0x0e |
| 108 | #define SEQ_CURSOR_Y_LOC_HI 0x0f |
| 109 | #define SEQ_CURSOR_Y_LOC_LO 0x10 |
| 110 | #define SEQ_CURSOR_X_INDEX 0x11 |
| 111 | #define SEQ_CURSOR_Y_INDEX 0x12 |
| 112 | #define SEQ_CURSOR_STORE_HI 0x13 |
| 113 | #define SEQ_CURSOR_STORE_LO 0x14 |
| 114 | #define SEQ_CURSOR_ST_OFF_HI 0x15 |
| 115 | #define SEQ_CURSOR_ST_OFF_LO 0x16 |
| 116 | #define SEQ_CURSOR_PIXELMASK 0x17 |
| 117 | #define SEQ_PRIM_HOST_OFF_HI 0x18 |
| 118 | #define SEQ_PRIM_HOST_OFF_LO 0x19 |
| 119 | #define SEQ_LINEAR_0 0x1a |
| 120 | #define SEQ_LINEAR_1 0x1b |
| 121 | #define SEQ_SEC_HOST_OFF_HI 0x1c |
| 122 | #define SEQ_SEC_HOST_OFF_LO 0x1d |
| 123 | #define SEQ_EXTENDED_MEM_ENA 0x1e |
| 124 | #define SEQ_EXT_CLOCK_MODE 0x1f |
| 125 | #define SEQ_EXT_VIDEO_ADDR 0x20 |
| 126 | #define SEQ_EXT_PIXEL_CNTL 0x21 |
| 127 | #define SEQ_BUS_WIDTH_FEEDB 0x22 |
| 128 | #define SEQ_PERF_SELECT 0x23 |
| 129 | #define SEQ_COLOR_EXP_WFG 0x24 |
| 130 | #define SEQ_COLOR_EXP_WBG 0x25 |
| 131 | #define SEQ_EXT_RW_CONTROL 0x26 |
| 132 | #define SEQ_MISC_FEATURE_SEL 0x27 |
| 133 | #define SEQ_COLOR_KEY_CNTL 0x28 |
| 134 | #define SEQ_COLOR_KEY_MATCH0 0x29 |
| 135 | #define SEQ_COLOR_KEY_MATCH1 0x2a |
| 136 | #define SEQ_COLOR_KEY_MATCH2 0x2b |
| 137 | #define SEQ_UNKNOWN6 0x2c |
| 138 | #define SEQ_CRC_CONTROL 0x2d |
| 139 | #define SEQ_CRC_DATA_LOW 0x2e |
| 140 | #define SEQ_CRC_DATA_HIGH 0x2f |
| 141 | #define SEQ_MEMORY_MAP_CNTL 0x30 |
| 142 | #define SEQ_ACM_APERTURE_1 0x31 |
| 143 | #define SEQ_ACM_APERTURE_2 0x32 |
| 144 | #define SEQ_ACM_APERTURE_3 0x33 |
| 145 | #define SEQ_BIOS_UTILITY_0 0x3e |
| 146 | #define SEQ_BIOS_UTILITY_1 0x3f |
| 147 | |
| 148 | /* |
| 149 | * Graphics Controller |
| 150 | */ |
| 151 | #define GFX_IDX 0x03ce |
| 152 | #define GFX_DATA 0x03cf |
| 153 | #define GFX_SET_RESET 0x00 |
| 154 | #define GFX_ENABLE_SET_RESET 0x01 |
| 155 | #define GFX_COLOR_COMPARE 0x02 |
| 156 | #define GFX_DATA_ROTATE 0x03 |
| 157 | #define GFX_READ_MAP_SELECT 0x04 |
| 158 | #define GFX_GRAPHICS_MODE 0x05 |
| 159 | #define GFX_MISC 0x06 |
| 160 | #define GFX_COLOR_XCARE 0x07 |
| 161 | #define GFX_BITMASK 0x08 |
| 162 | |
| 163 | /* |
| 164 | * CRT Controller |
| 165 | */ |
| 166 | #define CRT_IDX 0x03d4 |
| 167 | #define CRT_DATA 0x03d5 |
| 168 | #define CRT_HOR_TOTAL 0x00 |
| 169 | #define CRT_HOR_DISP_ENA_END 0x01 |
| 170 | #define CRT_START_HOR_BLANK 0x02 |
| 171 | #define CRT_END_HOR_BLANK 0x03 |
| 172 | #define CRT_START_HOR_RETR 0x04 |
| 173 | #define CRT_END_HOR_RETR 0x05 |
| 174 | #define CRT_VER_TOTAL 0x06 |
| 175 | #define CRT_OVERFLOW 0x07 |
| 176 | #define CRT_PRESET_ROW_SCAN 0x08 |
| 177 | #define CRT_MAX_SCAN_LINE 0x09 |
| 178 | #define CRT_CURSOR_START 0x0a |
| 179 | #define CRT_CURSOR_END 0x0b |
| 180 | #define CRT_START_ADDR_HIGH 0x0c |
| 181 | #define CRT_START_ADDR_LOW 0x0d |
| 182 | #define CRT_CURSOR_LOC_HIGH 0x0e |
| 183 | #define CRT_CURSOR_LOC_LOW 0x0f |
| 184 | #define CRT_START_VER_RETR 0x10 |
| 185 | #define CRT_END_VER_RETR 0x11 |
| 186 | #define CRT_VER_DISP_ENA_END 0x12 |
| 187 | #define CRT_OFFSET 0x13 |
| 188 | #define CRT_UNDERLINE_LOC 0x14 |
| 189 | #define CRT_START_VER_BLANK 0x15 |
| 190 | #define CRT_END_VER_BLANK 0x16 |
| 191 | #define CRT_MODE_CONTROL 0x17 |
| 192 | #define CRT_LINE_COMPARE 0x18 |
| 193 | #define CRT_UNKNOWN1 0x19 |
| 194 | #define CRT_UNKNOWN2 0x1a |
| 195 | #define CRT_UNKNOWN3 0x1b |
| 196 | #define CRT_UNKNOWN4 0x1c |
| 197 | #define CRT_UNKNOWN5 0x1d |
| 198 | #define CRT_UNKNOWN6 0x1e |
| 199 | #define CRT_UNKNOWN7 0x1f |
| 200 | #define CRT_UNKNOWN8 0x20 |
| 201 | #define CRT_UNKNOWN9 0x21 |
| 202 | #define CRT_UNKNOWN10 0x22 |
| 203 | #define CRT_UNKNOWN11 0x23 |
| 204 | #define CRT_UNKNOWN12 0x24 |
| 205 | #define CRT_UNKNOWN13 0x25 |
| 206 | #define CRT_UNKNOWN14 0x26 |
| 207 | #define CRT_UNKNOWN15 0x27 |
| 208 | #define CRT_UNKNOWN16 0x28 |
| 209 | #define CRT_UNKNOWN17 0x29 |
| 210 | #define CRT_UNKNOWN18 0x2a |
| 211 | #define CRT_UNKNOWN19 0x2b |
| 212 | #define CRT_UNKNOWN20 0x2c |
| 213 | #define CRT_UNKNOWN21 0x2d |
| 214 | #define CRT_UNKNOWN22 0x2e |
| 215 | #define CRT_UNKNOWN23 0x2f |
| 216 | #define CRT_EXT_HOR_TIMING1 0x30 /* NCR crt extensions */ |
| 217 | #define CRT_EXT_START_ADDR 0x31 |
| 218 | #define CRT_EXT_HOR_TIMING2 0x32 |
| 219 | #define CRT_EXT_VER_TIMING 0x33 |
| 220 | #define CRT_MONITOR_POWER 0x34 |
| 221 | |
| 222 | /* |
| 223 | * General Registers |
| 224 | */ |
| 225 | #define GREG_STATUS0_R 0x03c2 |
| 226 | #define GREG_STATUS1_R 0x03da |
| 227 | #define GREG_MISC_OUTPUT_R 0x03cc |
| 228 | #define GREG_MISC_OUTPUT_W 0x03c2 |
| 229 | #define GREG_FEATURE_CONTROL_R 0x03ca |
| 230 | #define GREG_FEATURE_CONTROL_W 0x03da |
| 231 | #define GREG_POS 0x0102 |
| 232 | |
| 233 | /* |
| 234 | * Attribute Controller |
| 235 | */ |
| 236 | #define ACT_IDX 0x03C0 |
| 237 | #define ACT_ADDRESS_R 0x03C0 |
| 238 | #define ACT_DATA 0x03C0 |
| 239 | #define ACT_ADDRESS_RESET 0x03DA |
| 240 | #define ACT_PALETTE0 0x00 |
| 241 | #define ACT_PALETTE1 0x01 |
| 242 | #define ACT_PALETTE2 0x02 |
| 243 | #define ACT_PALETTE3 0x03 |
| 244 | #define ACT_PALETTE4 0x04 |
| 245 | #define ACT_PALETTE5 0x05 |
| 246 | #define ACT_PALETTE6 0x06 |
| 247 | #define ACT_PALETTE7 0x07 |
| 248 | #define ACT_PALETTE8 0x08 |
| 249 | #define ACT_PALETTE9 0x09 |
| 250 | #define ACT_PALETTE10 0x0A |
| 251 | #define ACT_PALETTE11 0x0B |
| 252 | #define ACT_PALETTE12 0x0C |
| 253 | #define ACT_PALETTE13 0x0D |
| 254 | #define ACT_PALETTE14 0x0E |
| 255 | #define ACT_PALETTE15 0x0F |
| 256 | #define ACT_ATTR_MODE_CNTL 0x10 |
| 257 | #define ACT_OVERSCAN_COLOR 0x11 |
| 258 | #define ACT_COLOR_PLANE_ENA 0x12 |
| 259 | #define ACT_HOR_PEL_PANNING 0x13 |
| 260 | #define ACT_COLOR_SELECT 0x14 |
| 261 | |
| 262 | /* |
| 263 | * PLL |
| 264 | */ |
| 265 | #define PLL_IDX 0x83c8 |
| 266 | #define PLL_DATA 0x83c9 |
| 267 | |
| 268 | /* |
| 269 | * Blitter operations |
| 270 | */ |
| 271 | #define Z3BLTclear 0x00 /* 0 */ |
| 272 | #define Z3BLTand 0x80 /* src AND dst */ |
| 273 | #define Z3BLTandReverse 0x40 /* src AND NOT dst */ |
| 274 | #define Z3BLTcopy 0xc0 /* src */ |
| 275 | #define Z3BLTandInverted 0x20 /* NOT src AND dst */ |
| 276 | #define Z3BLTnoop 0xa0 /* dst */ |
| 277 | #define Z3BLTxor 0x60 /* src XOR dst */ |
| 278 | #define Z3BLTor 0xe0 /* src OR dst */ |
| 279 | #define Z3BLTnor 0x10 /* NOT src AND NOT dst */ |
| 280 | #define Z3BLTequiv 0x90 /* NOT src XOR dst */ |
| 281 | #define Z3BLTinvert 0x50 /* NOT dst */ |
| 282 | #define Z3BLTorReverse 0xd0 /* src OR NOT dst */ |
| 283 | #define Z3BLTcopyInverted 0x30 /* NOT src */ |
| 284 | #define Z3BLTorInverted 0xb0 /* NOT src OR dst */ |
| 285 | #define Z3BLTnand 0x70 /* NOT src OR NOT dst */ |
| 286 | #define Z3BLTset 0xf0 /* 1 */ |