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gerrit-public.fairphone.software / kernel / msm-4.19 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / include / sound / cs46xx.h
blob: 182dd276ee74552f499de0fdaa08e165407658a3 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1#ifndef __SOUND_CS46XX_H
2#define __SOUND_CS46XX_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Cirrus Logic, Inc.
7 * Definitions for Cirrus Logic CS46xx chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include "pcm.h"
27#include "pcm-indirect.h"
28#include "rawmidi.h"
29#include "ac97_codec.h"
30#include "cs46xx_dsp_spos.h"
31
32#ifndef PCI_VENDOR_ID_CIRRUS
33#define PCI_VENDOR_ID_CIRRUS 0x1013
34#endif
35#ifndef PCI_DEVICE_ID_CIRRUS_4610
36#define PCI_DEVICE_ID_CIRRUS_4610 0x6001
37#endif
38#ifndef PCI_DEVICE_ID_CIRRUS_4612
39#define PCI_DEVICE_ID_CIRRUS_4612 0x6003
40#endif
41#ifndef PCI_DEVICE_ID_CIRRUS_4615
42#define PCI_DEVICE_ID_CIRRUS_4615 0x6004
43#endif
44
45/*
46 * Direct registers
47 */
48
49/*
50 * The following define the offsets of the registers accessed via base address
51 * register zero on the CS46xx part.
52 */
53#define BA0_HISR 0x00000000
54#define BA0_HSR0 0x00000004
55#define BA0_HICR 0x00000008
56#define BA0_DMSR 0x00000100
57#define BA0_HSAR 0x00000110
58#define BA0_HDAR 0x00000114
59#define BA0_HDMR 0x00000118
60#define BA0_HDCR 0x0000011C
61#define BA0_PFMC 0x00000200
62#define BA0_PFCV1 0x00000204
63#define BA0_PFCV2 0x00000208
64#define BA0_PCICFG00 0x00000300
65#define BA0_PCICFG04 0x00000304
66#define BA0_PCICFG08 0x00000308
67#define BA0_PCICFG0C 0x0000030C
68#define BA0_PCICFG10 0x00000310
69#define BA0_PCICFG14 0x00000314
70#define BA0_PCICFG18 0x00000318
71#define BA0_PCICFG1C 0x0000031C
72#define BA0_PCICFG20 0x00000320
73#define BA0_PCICFG24 0x00000324
74#define BA0_PCICFG28 0x00000328
75#define BA0_PCICFG2C 0x0000032C
76#define BA0_PCICFG30 0x00000330
77#define BA0_PCICFG34 0x00000334
78#define BA0_PCICFG38 0x00000338
79#define BA0_PCICFG3C 0x0000033C
80#define BA0_CLKCR1 0x00000400
81#define BA0_CLKCR2 0x00000404
82#define BA0_PLLM 0x00000408
83#define BA0_PLLCC 0x0000040C
84#define BA0_FRR 0x00000410
85#define BA0_CFL1 0x00000414
86#define BA0_CFL2 0x00000418
87#define BA0_SERMC1 0x00000420
88#define BA0_SERMC2 0x00000424
89#define BA0_SERC1 0x00000428
90#define BA0_SERC2 0x0000042C
91#define BA0_SERC3 0x00000430
92#define BA0_SERC4 0x00000434
93#define BA0_SERC5 0x00000438
94#define BA0_SERBSP 0x0000043C
95#define BA0_SERBST 0x00000440
96#define BA0_SERBCM 0x00000444
97#define BA0_SERBAD 0x00000448
98#define BA0_SERBCF 0x0000044C
99#define BA0_SERBWP 0x00000450
100#define BA0_SERBRP 0x00000454
101#ifndef NO_CS4612
102#define BA0_ASER_FADDR 0x00000458
103#endif
104#define BA0_ACCTL 0x00000460
105#define BA0_ACSTS 0x00000464
106#define BA0_ACOSV 0x00000468
107#define BA0_ACCAD 0x0000046C
108#define BA0_ACCDA 0x00000470
109#define BA0_ACISV 0x00000474
110#define BA0_ACSAD 0x00000478
111#define BA0_ACSDA 0x0000047C
112#define BA0_JSPT 0x00000480
113#define BA0_JSCTL 0x00000484
114#define BA0_JSC1 0x00000488
115#define BA0_JSC2 0x0000048C
116#define BA0_MIDCR 0x00000490
117#define BA0_MIDSR 0x00000494
118#define BA0_MIDWP 0x00000498
119#define BA0_MIDRP 0x0000049C
120#define BA0_JSIO 0x000004A0
121#ifndef NO_CS4612
122#define BA0_ASER_MASTER 0x000004A4
123#endif
124#define BA0_CFGI 0x000004B0
125#define BA0_SSVID 0x000004B4
126#define BA0_GPIOR 0x000004B8
127#ifndef NO_CS4612
128#define BA0_EGPIODR 0x000004BC
129#define BA0_EGPIOPTR 0x000004C0
130#define BA0_EGPIOTR 0x000004C4
131#define BA0_EGPIOWR 0x000004C8
132#define BA0_EGPIOSR 0x000004CC
133#define BA0_SERC6 0x000004D0
134#define BA0_SERC7 0x000004D4
135#define BA0_SERACC 0x000004D8
136#define BA0_ACCTL2 0x000004E0
137#define BA0_ACSTS2 0x000004E4
138#define BA0_ACOSV2 0x000004E8
139#define BA0_ACCAD2 0x000004EC
140#define BA0_ACCDA2 0x000004F0
141#define BA0_ACISV2 0x000004F4
142#define BA0_ACSAD2 0x000004F8
143#define BA0_ACSDA2 0x000004FC
144#define BA0_IOTAC0 0x00000500
145#define BA0_IOTAC1 0x00000504
146#define BA0_IOTAC2 0x00000508
147#define BA0_IOTAC3 0x0000050C
148#define BA0_IOTAC4 0x00000510
149#define BA0_IOTAC5 0x00000514
150#define BA0_IOTAC6 0x00000518
151#define BA0_IOTAC7 0x0000051C
152#define BA0_IOTAC8 0x00000520
153#define BA0_IOTAC9 0x00000524
154#define BA0_IOTAC10 0x00000528
155#define BA0_IOTAC11 0x0000052C
156#define BA0_IOTFR0 0x00000540
157#define BA0_IOTFR1 0x00000544
158#define BA0_IOTFR2 0x00000548
159#define BA0_IOTFR3 0x0000054C
160#define BA0_IOTFR4 0x00000550
161#define BA0_IOTFR5 0x00000554
162#define BA0_IOTFR6 0x00000558
163#define BA0_IOTFR7 0x0000055C
164#define BA0_IOTFIFO 0x00000580
165#define BA0_IOTRRD 0x00000584
166#define BA0_IOTFP 0x00000588
167#define BA0_IOTCR 0x0000058C
168#define BA0_DPCID 0x00000590
169#define BA0_DPCIA 0x00000594
170#define BA0_DPCIC 0x00000598
171#define BA0_PCPCIR 0x00000600
172#define BA0_PCPCIG 0x00000604
173#define BA0_PCPCIEN 0x00000608
174#define BA0_EPCIPMC 0x00000610
175#endif
176
177/*
178 * The following define the offsets of the registers and memories accessed via
179 * base address register one on the CS46xx part.
180 */
181#define BA1_SP_DMEM0 0x00000000
182#define BA1_SP_DMEM1 0x00010000
183#define BA1_SP_PMEM 0x00020000
184#define BA1_SP_REG 0x00030000
185#define BA1_SPCR 0x00030000
186#define BA1_DREG 0x00030004
187#define BA1_DSRWP 0x00030008
188#define BA1_TWPR 0x0003000C
189#define BA1_SPWR 0x00030010
190#define BA1_SPIR 0x00030014
191#define BA1_FGR1 0x00030020
192#define BA1_SPCS 0x00030028
193#define BA1_SDSR 0x0003002C
194#define BA1_FRMT 0x00030030
195#define BA1_FRCC 0x00030034
196#define BA1_FRSC 0x00030038
197#define BA1_OMNI_MEM 0x000E0000
198
199
200/*
201 * The following defines are for the flags in the host interrupt status
202 * register.
203 */
204#define HISR_VC_MASK 0x0000FFFF
205#define HISR_VC0 0x00000001
206#define HISR_VC1 0x00000002
207#define HISR_VC2 0x00000004
208#define HISR_VC3 0x00000008
209#define HISR_VC4 0x00000010
210#define HISR_VC5 0x00000020
211#define HISR_VC6 0x00000040
212#define HISR_VC7 0x00000080
213#define HISR_VC8 0x00000100
214#define HISR_VC9 0x00000200
215#define HISR_VC10 0x00000400
216#define HISR_VC11 0x00000800
217#define HISR_VC12 0x00001000
218#define HISR_VC13 0x00002000
219#define HISR_VC14 0x00004000
220#define HISR_VC15 0x00008000
221#define HISR_INT0 0x00010000
222#define HISR_INT1 0x00020000
223#define HISR_DMAI 0x00040000
224#define HISR_FROVR 0x00080000
225#define HISR_MIDI 0x00100000
226#ifdef NO_CS4612
227#define HISR_RESERVED 0x0FE00000
228#else
229#define HISR_SBINT 0x00200000
230#define HISR_RESERVED 0x0FC00000
231#endif
232#define HISR_H0P 0x40000000
233#define HISR_INTENA 0x80000000
234
235/*
236 * The following defines are for the flags in the host signal register 0.
237 */
238#define HSR0_VC_MASK 0xFFFFFFFF
239#define HSR0_VC16 0x00000001
240#define HSR0_VC17 0x00000002
241#define HSR0_VC18 0x00000004
242#define HSR0_VC19 0x00000008
243#define HSR0_VC20 0x00000010
244#define HSR0_VC21 0x00000020
245#define HSR0_VC22 0x00000040
246#define HSR0_VC23 0x00000080
247#define HSR0_VC24 0x00000100
248#define HSR0_VC25 0x00000200
249#define HSR0_VC26 0x00000400
250#define HSR0_VC27 0x00000800
251#define HSR0_VC28 0x00001000
252#define HSR0_VC29 0x00002000
253#define HSR0_VC30 0x00004000
254#define HSR0_VC31 0x00008000
255#define HSR0_VC32 0x00010000
256#define HSR0_VC33 0x00020000
257#define HSR0_VC34 0x00040000
258#define HSR0_VC35 0x00080000
259#define HSR0_VC36 0x00100000
260#define HSR0_VC37 0x00200000
261#define HSR0_VC38 0x00400000
262#define HSR0_VC39 0x00800000
263#define HSR0_VC40 0x01000000
264#define HSR0_VC41 0x02000000
265#define HSR0_VC42 0x04000000
266#define HSR0_VC43 0x08000000
267#define HSR0_VC44 0x10000000
268#define HSR0_VC45 0x20000000
269#define HSR0_VC46 0x40000000
270#define HSR0_VC47 0x80000000
271
272/*
273 * The following defines are for the flags in the host interrupt control
274 * register.
275 */
276#define HICR_IEV 0x00000001
277#define HICR_CHGM 0x00000002
278
279/*
280 * The following defines are for the flags in the DMA status register.
281 */
282#define DMSR_HP 0x00000001
283#define DMSR_HR 0x00000002
284#define DMSR_SP 0x00000004
285#define DMSR_SR 0x00000008
286
287/*
288 * The following defines are for the flags in the host DMA source address
289 * register.
290 */
291#define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
292#define HSAR_DSP_ADDR_MASK 0x0000FFFF
293#define HSAR_MEMID_MASK 0x000F0000
294#define HSAR_MEMID_SP_DMEM0 0x00000000
295#define HSAR_MEMID_SP_DMEM1 0x00010000
296#define HSAR_MEMID_SP_PMEM 0x00020000
297#define HSAR_MEMID_SP_DEBUG 0x00030000
298#define HSAR_MEMID_OMNI_MEM 0x000E0000
299#define HSAR_END 0x40000000
300#define HSAR_ERR 0x80000000
301
302/*
303 * The following defines are for the flags in the host DMA destination address
304 * register.
305 */
306#define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
307#define HDAR_DSP_ADDR_MASK 0x0000FFFF
308#define HDAR_MEMID_MASK 0x000F0000
309#define HDAR_MEMID_SP_DMEM0 0x00000000
310#define HDAR_MEMID_SP_DMEM1 0x00010000
311#define HDAR_MEMID_SP_PMEM 0x00020000
312#define HDAR_MEMID_SP_DEBUG 0x00030000
313#define HDAR_MEMID_OMNI_MEM 0x000E0000
314#define HDAR_END 0x40000000
315#define HDAR_ERR 0x80000000
316
317/*
318 * The following defines are for the flags in the host DMA control register.
319 */
320#define HDMR_AC_MASK 0x0000F000
321#define HDMR_AC_8_16 0x00001000
322#define HDMR_AC_M_S 0x00002000
323#define HDMR_AC_B_L 0x00004000
324#define HDMR_AC_S_U 0x00008000
325
326/*
327 * The following defines are for the flags in the host DMA control register.
328 */
329#define HDCR_COUNT_MASK 0x000003FF
330#define HDCR_DONE 0x00004000
331#define HDCR_OPT 0x00008000
332#define HDCR_WBD 0x00400000
333#define HDCR_WBS 0x00800000
334#define HDCR_DMS_MASK 0x07000000
335#define HDCR_DMS_LINEAR 0x00000000
336#define HDCR_DMS_16_DWORDS 0x01000000
337#define HDCR_DMS_32_DWORDS 0x02000000
338#define HDCR_DMS_64_DWORDS 0x03000000
339#define HDCR_DMS_128_DWORDS 0x04000000
340#define HDCR_DMS_256_DWORDS 0x05000000
341#define HDCR_DMS_512_DWORDS 0x06000000
342#define HDCR_DMS_1024_DWORDS 0x07000000
343#define HDCR_DH 0x08000000
344#define HDCR_SMS_MASK 0x70000000
345#define HDCR_SMS_LINEAR 0x00000000
346#define HDCR_SMS_16_DWORDS 0x10000000
347#define HDCR_SMS_32_DWORDS 0x20000000
348#define HDCR_SMS_64_DWORDS 0x30000000
349#define HDCR_SMS_128_DWORDS 0x40000000
350#define HDCR_SMS_256_DWORDS 0x50000000
351#define HDCR_SMS_512_DWORDS 0x60000000
352#define HDCR_SMS_1024_DWORDS 0x70000000
353#define HDCR_SH 0x80000000
354#define HDCR_COUNT_SHIFT 0
355
356/*
357 * The following defines are for the flags in the performance monitor control
358 * register.
359 */
360#define PFMC_C1SS_MASK 0x0000001F
361#define PFMC_C1EV 0x00000020
362#define PFMC_C1RS 0x00008000
363#define PFMC_C2SS_MASK 0x001F0000
364#define PFMC_C2EV 0x00200000
365#define PFMC_C2RS 0x80000000
366#define PFMC_C1SS_SHIFT 0
367#define PFMC_C2SS_SHIFT 16
368#define PFMC_BUS_GRANT 0
369#define PFMC_GRANT_AFTER_REQ 1
370#define PFMC_TRANSACTION 2
371#define PFMC_DWORD_TRANSFER 3
372#define PFMC_SLAVE_READ 4
373#define PFMC_SLAVE_WRITE 5
374#define PFMC_PREEMPTION 6
375#define PFMC_DISCONNECT_RETRY 7
376#define PFMC_INTERRUPT 8
377#define PFMC_BUS_OWNERSHIP 9
378#define PFMC_TRANSACTION_LAG 10
379#define PFMC_PCI_CLOCK 11
380#define PFMC_SERIAL_CLOCK 12
381#define PFMC_SP_CLOCK 13
382
383/*
384 * The following defines are for the flags in the performance counter value 1
385 * register.
386 */
387#define PFCV1_PC1V_MASK 0xFFFFFFFF
388#define PFCV1_PC1V_SHIFT 0
389
390/*
391 * The following defines are for the flags in the performance counter value 2
392 * register.
393 */
394#define PFCV2_PC2V_MASK 0xFFFFFFFF
395#define PFCV2_PC2V_SHIFT 0
396
397/*
398 * The following defines are for the flags in the clock control register 1.
399 */
400#define CLKCR1_OSCS 0x00000001
401#define CLKCR1_OSCP 0x00000002
402#define CLKCR1_PLLSS_MASK 0x0000000C
403#define CLKCR1_PLLSS_SERIAL 0x00000000
404#define CLKCR1_PLLSS_CRYSTAL 0x00000004
405#define CLKCR1_PLLSS_PCI 0x00000008
406#define CLKCR1_PLLSS_RESERVED 0x0000000C
407#define CLKCR1_PLLP 0x00000010
408#define CLKCR1_SWCE 0x00000020
409#define CLKCR1_PLLOS 0x00000040
410
411/*
412 * The following defines are for the flags in the clock control register 2.
413 */
414#define CLKCR2_PDIVS_MASK 0x0000000F
415#define CLKCR2_PDIVS_1 0x00000001
416#define CLKCR2_PDIVS_2 0x00000002
417#define CLKCR2_PDIVS_4 0x00000004
418#define CLKCR2_PDIVS_7 0x00000007
419#define CLKCR2_PDIVS_8 0x00000008
420#define CLKCR2_PDIVS_16 0x00000000
421
422/*
423 * The following defines are for the flags in the PLL multiplier register.
424 */
425#define PLLM_MASK 0x000000FF
426#define PLLM_SHIFT 0
427
428/*
429 * The following defines are for the flags in the PLL capacitor coefficient
430 * register.
431 */
432#define PLLCC_CDR_MASK 0x00000007
433#ifndef NO_CS4610
434#define PLLCC_CDR_240_350_MHZ 0x00000000
435#define PLLCC_CDR_184_265_MHZ 0x00000001
436#define PLLCC_CDR_144_205_MHZ 0x00000002
437#define PLLCC_CDR_111_160_MHZ 0x00000003
438#define PLLCC_CDR_87_123_MHZ 0x00000004
439#define PLLCC_CDR_67_96_MHZ 0x00000005
440#define PLLCC_CDR_52_74_MHZ 0x00000006
441#define PLLCC_CDR_45_58_MHZ 0x00000007
442#endif
443#ifndef NO_CS4612
444#define PLLCC_CDR_271_398_MHZ 0x00000000
445#define PLLCC_CDR_227_330_MHZ 0x00000001
446#define PLLCC_CDR_167_239_MHZ 0x00000002
447#define PLLCC_CDR_150_215_MHZ 0x00000003
448#define PLLCC_CDR_107_154_MHZ 0x00000004
449#define PLLCC_CDR_98_140_MHZ 0x00000005
450#define PLLCC_CDR_73_104_MHZ 0x00000006
451#define PLLCC_CDR_63_90_MHZ 0x00000007
452#endif
453#define PLLCC_LPF_MASK 0x000000F8
454#ifndef NO_CS4610
455#define PLLCC_LPF_23850_60000_KHZ 0x00000000
456#define PLLCC_LPF_7960_26290_KHZ 0x00000008
457#define PLLCC_LPF_4160_10980_KHZ 0x00000018
458#define PLLCC_LPF_1740_4580_KHZ 0x00000038
459#define PLLCC_LPF_724_1910_KHZ 0x00000078
460#define PLLCC_LPF_317_798_KHZ 0x000000F8
461#endif
462#ifndef NO_CS4612
463#define PLLCC_LPF_25580_64530_KHZ 0x00000000
464#define PLLCC_LPF_14360_37270_KHZ 0x00000008
465#define PLLCC_LPF_6100_16020_KHZ 0x00000018
466#define PLLCC_LPF_2540_6690_KHZ 0x00000038
467#define PLLCC_LPF_1050_2780_KHZ 0x00000078
468#define PLLCC_LPF_450_1160_KHZ 0x000000F8
469#endif
470
471/*
472 * The following defines are for the flags in the feature reporting register.
473 */
474#define FRR_FAB_MASK 0x00000003
475#define FRR_MASK_MASK 0x0000001C
476#ifdef NO_CS4612
477#define FRR_CFOP_MASK 0x000000E0
478#else
479#define FRR_CFOP_MASK 0x00000FE0
480#endif
481#define FRR_CFOP_NOT_DVD 0x00000020
482#define FRR_CFOP_A3D 0x00000040
483#define FRR_CFOP_128_PIN 0x00000080
484#ifndef NO_CS4612
485#define FRR_CFOP_CS4280 0x00000800
486#endif
487#define FRR_FAB_SHIFT 0
488#define FRR_MASK_SHIFT 2
489#define FRR_CFOP_SHIFT 5
490
491/*
492 * The following defines are for the flags in the configuration load 1
493 * register.
494 */
495#define CFL1_CLOCK_SOURCE_MASK 0x00000003
496#define CFL1_CLOCK_SOURCE_CS423X 0x00000000
497#define CFL1_CLOCK_SOURCE_AC97 0x00000001
498#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
499#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
500#define CFL1_VALID_DATA_MASK 0x000000FF
501
502/*
503 * The following defines are for the flags in the configuration load 2
504 * register.
505 */
506#define CFL2_VALID_DATA_MASK 0x000000FF
507
508/*
509 * The following defines are for the flags in the serial port master control
510 * register 1.
511 */
512#define SERMC1_MSPE 0x00000001
513#define SERMC1_PTC_MASK 0x0000000E
514#define SERMC1_PTC_CS423X 0x00000000
515#define SERMC1_PTC_AC97 0x00000002
516#define SERMC1_PTC_DAC 0x00000004
517#define SERMC1_PLB 0x00000010
518#define SERMC1_XLB 0x00000020
519
520/*
521 * The following defines are for the flags in the serial port master control
522 * register 2.
523 */
524#define SERMC2_LROE 0x00000001
525#define SERMC2_MCOE 0x00000002
526#define SERMC2_MCDIV 0x00000004
527
528/*
529 * The following defines are for the flags in the serial port 1 configuration
530 * register.
531 */
532#define SERC1_SO1EN 0x00000001
533#define SERC1_SO1F_MASK 0x0000000E
534#define SERC1_SO1F_CS423X 0x00000000
535#define SERC1_SO1F_AC97 0x00000002
536#define SERC1_SO1F_DAC 0x00000004
537#define SERC1_SO1F_SPDIF 0x00000006
538
539/*
540 * The following defines are for the flags in the serial port 2 configuration
541 * register.
542 */
543#define SERC2_SI1EN 0x00000001
544#define SERC2_SI1F_MASK 0x0000000E
545#define SERC2_SI1F_CS423X 0x00000000
546#define SERC2_SI1F_AC97 0x00000002
547#define SERC2_SI1F_ADC 0x00000004
548#define SERC2_SI1F_SPDIF 0x00000006
549
550/*
551 * The following defines are for the flags in the serial port 3 configuration
552 * register.
553 */
554#define SERC3_SO2EN 0x00000001
555#define SERC3_SO2F_MASK 0x00000006
556#define SERC3_SO2F_DAC 0x00000000
557#define SERC3_SO2F_SPDIF 0x00000002
558
559/*
560 * The following defines are for the flags in the serial port 4 configuration
561 * register.
562 */
563#define SERC4_SO3EN 0x00000001
564#define SERC4_SO3F_MASK 0x00000006
565#define SERC4_SO3F_DAC 0x00000000
566#define SERC4_SO3F_SPDIF 0x00000002
567
568/*
569 * The following defines are for the flags in the serial port 5 configuration
570 * register.
571 */
572#define SERC5_SI2EN 0x00000001
573#define SERC5_SI2F_MASK 0x00000006
574#define SERC5_SI2F_ADC 0x00000000
575#define SERC5_SI2F_SPDIF 0x00000002
576
577/*
578 * The following defines are for the flags in the serial port backdoor sample
579 * pointer register.
580 */
581#define SERBSP_FSP_MASK 0x0000000F
582#define SERBSP_FSP_SHIFT 0
583
584/*
585 * The following defines are for the flags in the serial port backdoor status
586 * register.
587 */
588#define SERBST_RRDY 0x00000001
589#define SERBST_WBSY 0x00000002
590
591/*
592 * The following defines are for the flags in the serial port backdoor command
593 * register.
594 */
595#define SERBCM_RDC 0x00000001
596#define SERBCM_WRC 0x00000002
597
598/*
599 * The following defines are for the flags in the serial port backdoor address
600 * register.
601 */
602#ifdef NO_CS4612
603#define SERBAD_FAD_MASK 0x000000FF
604#else
605#define SERBAD_FAD_MASK 0x000001FF
606#endif
607#define SERBAD_FAD_SHIFT 0
608
609/*
610 * The following defines are for the flags in the serial port backdoor
611 * configuration register.
612 */
613#define SERBCF_HBP 0x00000001
614
615/*
616 * The following defines are for the flags in the serial port backdoor write
617 * port register.
618 */
619#define SERBWP_FWD_MASK 0x000FFFFF
620#define SERBWP_FWD_SHIFT 0
621
622/*
623 * The following defines are for the flags in the serial port backdoor read
624 * port register.
625 */
626#define SERBRP_FRD_MASK 0x000FFFFF
627#define SERBRP_FRD_SHIFT 0
628
629/*
630 * The following defines are for the flags in the async FIFO address register.
631 */
632#ifndef NO_CS4612
633#define ASER_FADDR_A1_MASK 0x000001FF
634#define ASER_FADDR_EN1 0x00008000
635#define ASER_FADDR_A2_MASK 0x01FF0000
636#define ASER_FADDR_EN2 0x80000000
637#define ASER_FADDR_A1_SHIFT 0
638#define ASER_FADDR_A2_SHIFT 16
639#endif
640
641/*
642 * The following defines are for the flags in the AC97 control register.
643 */
644#define ACCTL_RSTN 0x00000001
645#define ACCTL_ESYN 0x00000002
646#define ACCTL_VFRM 0x00000004
647#define ACCTL_DCV 0x00000008
648#define ACCTL_CRW 0x00000010
649#define ACCTL_ASYN 0x00000020
650#ifndef NO_CS4612
651#define ACCTL_TC 0x00000040
652#endif
653
654/*
655 * The following defines are for the flags in the AC97 status register.
656 */
657#define ACSTS_CRDY 0x00000001
658#define ACSTS_VSTS 0x00000002
659#ifndef NO_CS4612
660#define ACSTS_WKUP 0x00000004
661#endif
662
663/*
664 * The following defines are for the flags in the AC97 output slot valid
665 * register.
666 */
667#define ACOSV_SLV3 0x00000001
668#define ACOSV_SLV4 0x00000002
669#define ACOSV_SLV5 0x00000004
670#define ACOSV_SLV6 0x00000008
671#define ACOSV_SLV7 0x00000010
672#define ACOSV_SLV8 0x00000020
673#define ACOSV_SLV9 0x00000040
674#define ACOSV_SLV10 0x00000080
675#define ACOSV_SLV11 0x00000100
676#define ACOSV_SLV12 0x00000200
677
678/*
679 * The following defines are for the flags in the AC97 command address
680 * register.
681 */
682#define ACCAD_CI_MASK 0x0000007F
683#define ACCAD_CI_SHIFT 0
684
685/*
686 * The following defines are for the flags in the AC97 command data register.
687 */
688#define ACCDA_CD_MASK 0x0000FFFF
689#define ACCDA_CD_SHIFT 0
690
691/*
692 * The following defines are for the flags in the AC97 input slot valid
693 * register.
694 */
695#define ACISV_ISV3 0x00000001
696#define ACISV_ISV4 0x00000002
697#define ACISV_ISV5 0x00000004
698#define ACISV_ISV6 0x00000008
699#define ACISV_ISV7 0x00000010
700#define ACISV_ISV8 0x00000020
701#define ACISV_ISV9 0x00000040
702#define ACISV_ISV10 0x00000080
703#define ACISV_ISV11 0x00000100
704#define ACISV_ISV12 0x00000200
705
706/*
707 * The following defines are for the flags in the AC97 status address
708 * register.
709 */
710#define ACSAD_SI_MASK 0x0000007F
711#define ACSAD_SI_SHIFT 0
712
713/*
714 * The following defines are for the flags in the AC97 status data register.
715 */
716#define ACSDA_SD_MASK 0x0000FFFF
717#define ACSDA_SD_SHIFT 0
718
719/*
720 * The following defines are for the flags in the joystick poll/trigger
721 * register.
722 */
723#define JSPT_CAX 0x00000001
724#define JSPT_CAY 0x00000002
725#define JSPT_CBX 0x00000004
726#define JSPT_CBY 0x00000008
727#define JSPT_BA1 0x00000010
728#define JSPT_BA2 0x00000020
729#define JSPT_BB1 0x00000040
730#define JSPT_BB2 0x00000080
731
732/*
733 * The following defines are for the flags in the joystick control register.
734 */
735#define JSCTL_SP_MASK 0x00000003
736#define JSCTL_SP_SLOW 0x00000000
737#define JSCTL_SP_MEDIUM_SLOW 0x00000001
738#define JSCTL_SP_MEDIUM_FAST 0x00000002
739#define JSCTL_SP_FAST 0x00000003
740#define JSCTL_ARE 0x00000004
741
742/*
743 * The following defines are for the flags in the joystick coordinate pair 1
744 * readback register.
745 */
746#define JSC1_Y1V_MASK 0x0000FFFF
747#define JSC1_X1V_MASK 0xFFFF0000
748#define JSC1_Y1V_SHIFT 0
749#define JSC1_X1V_SHIFT 16
750
751/*
752 * The following defines are for the flags in the joystick coordinate pair 2
753 * readback register.
754 */
755#define JSC2_Y2V_MASK 0x0000FFFF
756#define JSC2_X2V_MASK 0xFFFF0000
757#define JSC2_Y2V_SHIFT 0
758#define JSC2_X2V_SHIFT 16
759
760/*
761 * The following defines are for the flags in the MIDI control register.
762 */
763#define MIDCR_TXE 0x00000001 /* Enable transmitting. */
764#define MIDCR_RXE 0x00000002 /* Enable receiving. */
765#define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
766#define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
767#define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
768#define MIDCR_MRST 0x00000020 /* Reset interface. */
769
770/*
771 * The following defines are for the flags in the MIDI status register.
772 */
773#define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
774#define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
775
776/*
777 * The following defines are for the flags in the MIDI write port register.
778 */
779#define MIDWP_MWD_MASK 0x000000FF
780#define MIDWP_MWD_SHIFT 0
781
782/*
783 * The following defines are for the flags in the MIDI read port register.
784 */
785#define MIDRP_MRD_MASK 0x000000FF
786#define MIDRP_MRD_SHIFT 0
787
788/*
789 * The following defines are for the flags in the joystick GPIO register.
790 */
791#define JSIO_DAX 0x00000001
792#define JSIO_DAY 0x00000002
793#define JSIO_DBX 0x00000004
794#define JSIO_DBY 0x00000008
795#define JSIO_AXOE 0x00000010
796#define JSIO_AYOE 0x00000020
797#define JSIO_BXOE 0x00000040
798#define JSIO_BYOE 0x00000080
799
800/*
801 * The following defines are for the flags in the master async/sync serial
802 * port enable register.
803 */
804#ifndef NO_CS4612
805#define ASER_MASTER_ME 0x00000001
806#endif
807
808/*
809 * The following defines are for the flags in the configuration interface
810 * register.
811 */
812#define CFGI_CLK 0x00000001
813#define CFGI_DOUT 0x00000002
814#define CFGI_DIN_EEN 0x00000004
815#define CFGI_EELD 0x00000008
816
817/*
818 * The following defines are for the flags in the subsystem ID and vendor ID
819 * register.
820 */
821#define SSVID_VID_MASK 0x0000FFFF
822#define SSVID_SID_MASK 0xFFFF0000
823#define SSVID_VID_SHIFT 0
824#define SSVID_SID_SHIFT 16
825
826/*
827 * The following defines are for the flags in the GPIO pin interface register.
828 */
829#define GPIOR_VOLDN 0x00000001
830#define GPIOR_VOLUP 0x00000002
831#define GPIOR_SI2D 0x00000004
832#define GPIOR_SI2OE 0x00000008
833
834/*
835 * The following defines are for the flags in the extended GPIO pin direction
836 * register.
837 */
838#ifndef NO_CS4612
839#define EGPIODR_GPOE0 0x00000001
840#define EGPIODR_GPOE1 0x00000002
841#define EGPIODR_GPOE2 0x00000004
842#define EGPIODR_GPOE3 0x00000008
843#define EGPIODR_GPOE4 0x00000010
844#define EGPIODR_GPOE5 0x00000020
845#define EGPIODR_GPOE6 0x00000040
846#define EGPIODR_GPOE7 0x00000080
847#define EGPIODR_GPOE8 0x00000100
848#endif
849
850/*
851 * The following defines are for the flags in the extended GPIO pin polarity/
852 * type register.
853 */
854#ifndef NO_CS4612
855#define EGPIOPTR_GPPT0 0x00000001
856#define EGPIOPTR_GPPT1 0x00000002
857#define EGPIOPTR_GPPT2 0x00000004
858#define EGPIOPTR_GPPT3 0x00000008
859#define EGPIOPTR_GPPT4 0x00000010
860#define EGPIOPTR_GPPT5 0x00000020
861#define EGPIOPTR_GPPT6 0x00000040
862#define EGPIOPTR_GPPT7 0x00000080
863#define EGPIOPTR_GPPT8 0x00000100
864#endif
865
866/*
867 * The following defines are for the flags in the extended GPIO pin sticky
868 * register.
869 */
870#ifndef NO_CS4612
871#define EGPIOTR_GPS0 0x00000001
872#define EGPIOTR_GPS1 0x00000002
873#define EGPIOTR_GPS2 0x00000004
874#define EGPIOTR_GPS3 0x00000008
875#define EGPIOTR_GPS4 0x00000010
876#define EGPIOTR_GPS5 0x00000020
877#define EGPIOTR_GPS6 0x00000040
878#define EGPIOTR_GPS7 0x00000080
879#define EGPIOTR_GPS8 0x00000100
880#endif
881
882/*
883 * The following defines are for the flags in the extended GPIO ping wakeup
884 * register.
885 */
886#ifndef NO_CS4612
887#define EGPIOWR_GPW0 0x00000001
888#define EGPIOWR_GPW1 0x00000002
889#define EGPIOWR_GPW2 0x00000004
890#define EGPIOWR_GPW3 0x00000008
891#define EGPIOWR_GPW4 0x00000010
892#define EGPIOWR_GPW5 0x00000020
893#define EGPIOWR_GPW6 0x00000040
894#define EGPIOWR_GPW7 0x00000080
895#define EGPIOWR_GPW8 0x00000100
896#endif
897
898/*
899 * The following defines are for the flags in the extended GPIO pin status
900 * register.
901 */
902#ifndef NO_CS4612
903#define EGPIOSR_GPS0 0x00000001
904#define EGPIOSR_GPS1 0x00000002
905#define EGPIOSR_GPS2 0x00000004
906#define EGPIOSR_GPS3 0x00000008
907#define EGPIOSR_GPS4 0x00000010
908#define EGPIOSR_GPS5 0x00000020
909#define EGPIOSR_GPS6 0x00000040
910#define EGPIOSR_GPS7 0x00000080
911#define EGPIOSR_GPS8 0x00000100
912#endif
913
914/*
915 * The following defines are for the flags in the serial port 6 configuration
916 * register.
917 */
918#ifndef NO_CS4612
919#define SERC6_ASDO2EN 0x00000001
920#endif
921
922/*
923 * The following defines are for the flags in the serial port 7 configuration
924 * register.
925 */
926#ifndef NO_CS4612
927#define SERC7_ASDI2EN 0x00000001
928#define SERC7_POSILB 0x00000002
929#define SERC7_SIPOLB 0x00000004
930#define SERC7_SOSILB 0x00000008
931#define SERC7_SISOLB 0x00000010
932#endif
933
934/*
935 * The following defines are for the flags in the serial port AC link
936 * configuration register.
937 */
938#ifndef NO_CS4612
939#define SERACC_CHIP_TYPE_MASK 0x00000001
940#define SERACC_CHIP_TYPE_1_03 0x00000000
941#define SERACC_CHIP_TYPE_2_0 0x00000001
942#define SERACC_TWO_CODECS 0x00000002
943#define SERACC_MDM 0x00000004
944#define SERACC_HSP 0x00000008
945#define SERACC_ODT 0x00000010 /* only CS4630 */
946#endif
947
948/*
949 * The following defines are for the flags in the AC97 control register 2.
950 */
951#ifndef NO_CS4612
952#define ACCTL2_RSTN 0x00000001
953#define ACCTL2_ESYN 0x00000002
954#define ACCTL2_VFRM 0x00000004
955#define ACCTL2_DCV 0x00000008
956#define ACCTL2_CRW 0x00000010
957#define ACCTL2_ASYN 0x00000020
958#endif
959
960/*
961 * The following defines are for the flags in the AC97 status register 2.
962 */
963#ifndef NO_CS4612
964#define ACSTS2_CRDY 0x00000001
965#define ACSTS2_VSTS 0x00000002
966#endif
967
968/*
969 * The following defines are for the flags in the AC97 output slot valid
970 * register 2.
971 */
972#ifndef NO_CS4612
973#define ACOSV2_SLV3 0x00000001
974#define ACOSV2_SLV4 0x00000002
975#define ACOSV2_SLV5 0x00000004
976#define ACOSV2_SLV6 0x00000008
977#define ACOSV2_SLV7 0x00000010
978#define ACOSV2_SLV8 0x00000020
979#define ACOSV2_SLV9 0x00000040
980#define ACOSV2_SLV10 0x00000080
981#define ACOSV2_SLV11 0x00000100
982#define ACOSV2_SLV12 0x00000200
983#endif
984
985/*
986 * The following defines are for the flags in the AC97 command address
987 * register 2.
988 */
989#ifndef NO_CS4612
990#define ACCAD2_CI_MASK 0x0000007F
991#define ACCAD2_CI_SHIFT 0
992#endif
993
994/*
995 * The following defines are for the flags in the AC97 command data register
996 * 2.
997 */
998#ifndef NO_CS4612
999#define ACCDA2_CD_MASK 0x0000FFFF
1000#define ACCDA2_CD_SHIFT 0
1001#endif
1002
1003/*
1004 * The following defines are for the flags in the AC97 input slot valid
1005 * register 2.
1006 */
1007#ifndef NO_CS4612
1008#define ACISV2_ISV3 0x00000001
1009#define ACISV2_ISV4 0x00000002
1010#define ACISV2_ISV5 0x00000004
1011#define ACISV2_ISV6 0x00000008
1012#define ACISV2_ISV7 0x00000010
1013#define ACISV2_ISV8 0x00000020
1014#define ACISV2_ISV9 0x00000040
1015#define ACISV2_ISV10 0x00000080
1016#define ACISV2_ISV11 0x00000100
1017#define ACISV2_ISV12 0x00000200
1018#endif
1019
1020/*
1021 * The following defines are for the flags in the AC97 status address
1022 * register 2.
1023 */
1024#ifndef NO_CS4612
1025#define ACSAD2_SI_MASK 0x0000007F
1026#define ACSAD2_SI_SHIFT 0
1027#endif
1028
1029/*
1030 * The following defines are for the flags in the AC97 status data register 2.
1031 */
1032#ifndef NO_CS4612
1033#define ACSDA2_SD_MASK 0x0000FFFF
1034#define ACSDA2_SD_SHIFT 0
1035#endif
1036
1037/*
1038 * The following defines are for the flags in the I/O trap address and control
1039 * registers (all 12).
1040 */
1041#ifndef NO_CS4612
1042#define IOTAC_SA_MASK 0x0000FFFF
1043#define IOTAC_MSK_MASK 0x000F0000
1044#define IOTAC_IODC_MASK 0x06000000
1045#define IOTAC_IODC_16_BIT 0x00000000
1046#define IOTAC_IODC_10_BIT 0x02000000
1047#define IOTAC_IODC_12_BIT 0x04000000
1048#define IOTAC_WSPI 0x08000000
1049#define IOTAC_RSPI 0x10000000
1050#define IOTAC_WSE 0x20000000
1051#define IOTAC_WE 0x40000000
1052#define IOTAC_RE 0x80000000
1053#define IOTAC_SA_SHIFT 0
1054#define IOTAC_MSK_SHIFT 16
1055#endif
1056
1057/*
1058 * The following defines are for the flags in the I/O trap fast read registers
1059 * (all 8).
1060 */
1061#ifndef NO_CS4612
1062#define IOTFR_D_MASK 0x0000FFFF
1063#define IOTFR_A_MASK 0x000F0000
1064#define IOTFR_R_MASK 0x0F000000
1065#define IOTFR_ALL 0x40000000
1066#define IOTFR_VL 0x80000000
1067#define IOTFR_D_SHIFT 0
1068#define IOTFR_A_SHIFT 16
1069#define IOTFR_R_SHIFT 24
1070#endif
1071
1072/*
1073 * The following defines are for the flags in the I/O trap FIFO register.
1074 */
1075#ifndef NO_CS4612
1076#define IOTFIFO_BA_MASK 0x00003FFF
1077#define IOTFIFO_S_MASK 0x00FF0000
1078#define IOTFIFO_OF 0x40000000
1079#define IOTFIFO_SPIOF 0x80000000
1080#define IOTFIFO_BA_SHIFT 0
1081#define IOTFIFO_S_SHIFT 16
1082#endif
1083
1084/*
1085 * The following defines are for the flags in the I/O trap retry read data
1086 * register.
1087 */
1088#ifndef NO_CS4612
1089#define IOTRRD_D_MASK 0x0000FFFF
1090#define IOTRRD_RDV 0x80000000
1091#define IOTRRD_D_SHIFT 0
1092#endif
1093
1094/*
1095 * The following defines are for the flags in the I/O trap FIFO pointer
1096 * register.
1097 */
1098#ifndef NO_CS4612
1099#define IOTFP_CA_MASK 0x00003FFF
1100#define IOTFP_PA_MASK 0x3FFF0000
1101#define IOTFP_CA_SHIFT 0
1102#define IOTFP_PA_SHIFT 16
1103#endif
1104
1105/*
1106 * The following defines are for the flags in the I/O trap control register.
1107 */
1108#ifndef NO_CS4612
1109#define IOTCR_ITD 0x00000001
1110#define IOTCR_HRV 0x00000002
1111#define IOTCR_SRV 0x00000004
1112#define IOTCR_DTI 0x00000008
1113#define IOTCR_DFI 0x00000010
1114#define IOTCR_DDP 0x00000020
1115#define IOTCR_JTE 0x00000040
1116#define IOTCR_PPE 0x00000080
1117#endif
1118
1119/*
1120 * The following defines are for the flags in the direct PCI data register.
1121 */
1122#ifndef NO_CS4612
1123#define DPCID_D_MASK 0xFFFFFFFF
1124#define DPCID_D_SHIFT 0
1125#endif
1126
1127/*
1128 * The following defines are for the flags in the direct PCI address register.
1129 */
1130#ifndef NO_CS4612
1131#define DPCIA_A_MASK 0xFFFFFFFF
1132#define DPCIA_A_SHIFT 0
1133#endif
1134
1135/*
1136 * The following defines are for the flags in the direct PCI command register.
1137 */
1138#ifndef NO_CS4612
1139#define DPCIC_C_MASK 0x0000000F
1140#define DPCIC_C_IOREAD 0x00000002
1141#define DPCIC_C_IOWRITE 0x00000003
1142#define DPCIC_BE_MASK 0x000000F0
1143#endif
1144
1145/*
1146 * The following defines are for the flags in the PC/PCI request register.
1147 */
1148#ifndef NO_CS4612
1149#define PCPCIR_RDC_MASK 0x00000007
1150#define PCPCIR_C_MASK 0x00007000
1151#define PCPCIR_REQ 0x00008000
1152#define PCPCIR_RDC_SHIFT 0
1153#define PCPCIR_C_SHIFT 12
1154#endif
1155
1156/*
1157 * The following defines are for the flags in the PC/PCI grant register.
1158 */
1159#ifndef NO_CS4612
1160#define PCPCIG_GDC_MASK 0x00000007
1161#define PCPCIG_VL 0x00008000
1162#define PCPCIG_GDC_SHIFT 0
1163#endif
1164
1165/*
1166 * The following defines are for the flags in the PC/PCI master enable
1167 * register.
1168 */
1169#ifndef NO_CS4612
1170#define PCPCIEN_EN 0x00000001
1171#endif
1172
1173/*
1174 * The following defines are for the flags in the extended PCI power
1175 * management control register.
1176 */
1177#ifndef NO_CS4612
1178#define EPCIPMC_GWU 0x00000001
1179#define EPCIPMC_FSPC 0x00000002
1180#endif
1181
1182/*
1183 * The following defines are for the flags in the SP control register.
1184 */
1185#define SPCR_RUN 0x00000001
1186#define SPCR_STPFR 0x00000002
1187#define SPCR_RUNFR 0x00000004
1188#define SPCR_TICK 0x00000008
1189#define SPCR_DRQEN 0x00000020
1190#define SPCR_RSTSP 0x00000040
1191#define SPCR_OREN 0x00000080
1192#ifndef NO_CS4612
1193#define SPCR_PCIINT 0x00000100
1194#define SPCR_OINTD 0x00000200
1195#define SPCR_CRE 0x00008000
1196#endif
1197
1198/*
1199 * The following defines are for the flags in the debug index register.
1200 */
1201#define DREG_REGID_MASK 0x0000007F
1202#define DREG_DEBUG 0x00000080
1203#define DREG_RGBK_MASK 0x00000700
1204#define DREG_TRAP 0x00000800
1205#if !defined(NO_CS4612)
1206#if !defined(NO_CS4615)
1207#define DREG_TRAPX 0x00001000
1208#endif
1209#endif
1210#define DREG_REGID_SHIFT 0
1211#define DREG_RGBK_SHIFT 8
1212#define DREG_RGBK_REGID_MASK 0x0000077F
1213#define DREG_REGID_R0 0x00000010
1214#define DREG_REGID_R1 0x00000011
1215#define DREG_REGID_R2 0x00000012
1216#define DREG_REGID_R3 0x00000013
1217#define DREG_REGID_R4 0x00000014
1218#define DREG_REGID_R5 0x00000015
1219#define DREG_REGID_R6 0x00000016
1220#define DREG_REGID_R7 0x00000017
1221#define DREG_REGID_R8 0x00000018
1222#define DREG_REGID_R9 0x00000019
1223#define DREG_REGID_RA 0x0000001A
1224#define DREG_REGID_RB 0x0000001B
1225#define DREG_REGID_RC 0x0000001C
1226#define DREG_REGID_RD 0x0000001D
1227#define DREG_REGID_RE 0x0000001E
1228#define DREG_REGID_RF 0x0000001F
1229#define DREG_REGID_RA_BUS_LOW 0x00000020
1230#define DREG_REGID_RA_BUS_HIGH 0x00000038
1231#define DREG_REGID_YBUS_LOW 0x00000050
1232#define DREG_REGID_YBUS_HIGH 0x00000058
1233#define DREG_REGID_TRAP_0 0x00000100
1234#define DREG_REGID_TRAP_1 0x00000101
1235#define DREG_REGID_TRAP_2 0x00000102
1236#define DREG_REGID_TRAP_3 0x00000103
1237#define DREG_REGID_TRAP_4 0x00000104
1238#define DREG_REGID_TRAP_5 0x00000105
1239#define DREG_REGID_TRAP_6 0x00000106
1240#define DREG_REGID_TRAP_7 0x00000107
1241#define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
1242#define DREG_REGID_TOP_OF_STACK 0x0000010F
1243#if !defined(NO_CS4612)
1244#if !defined(NO_CS4615)
1245#define DREG_REGID_TRAP_8 0x00000110
1246#define DREG_REGID_TRAP_9 0x00000111
1247#define DREG_REGID_TRAP_10 0x00000112
1248#define DREG_REGID_TRAP_11 0x00000113
1249#define DREG_REGID_TRAP_12 0x00000114
1250#define DREG_REGID_TRAP_13 0x00000115
1251#define DREG_REGID_TRAP_14 0x00000116
1252#define DREG_REGID_TRAP_15 0x00000117
1253#define DREG_REGID_TRAP_16 0x00000118
1254#define DREG_REGID_TRAP_17 0x00000119
1255#define DREG_REGID_TRAP_18 0x0000011A
1256#define DREG_REGID_TRAP_19 0x0000011B
1257#define DREG_REGID_TRAP_20 0x0000011C
1258#define DREG_REGID_TRAP_21 0x0000011D
1259#define DREG_REGID_TRAP_22 0x0000011E
1260#define DREG_REGID_TRAP_23 0x0000011F
1261#endif
1262#endif
1263#define DREG_REGID_RSA0_LOW 0x00000200
1264#define DREG_REGID_RSA0_HIGH 0x00000201
1265#define DREG_REGID_RSA1_LOW 0x00000202
1266#define DREG_REGID_RSA1_HIGH 0x00000203
1267#define DREG_REGID_RSA2 0x00000204
1268#define DREG_REGID_RSA3 0x00000205
1269#define DREG_REGID_RSI0_LOW 0x00000206
1270#define DREG_REGID_RSI0_HIGH 0x00000207
1271#define DREG_REGID_RSI1 0x00000208
1272#define DREG_REGID_RSI2 0x00000209
1273#define DREG_REGID_SAGUSTATUS 0x0000020A
1274#define DREG_REGID_RSCONFIG01_LOW 0x0000020B
1275#define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
1276#define DREG_REGID_RSCONFIG23_LOW 0x0000020D
1277#define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
1278#define DREG_REGID_RSDMA01E 0x0000020F
1279#define DREG_REGID_RSDMA23E 0x00000210
1280#define DREG_REGID_RSD0_LOW 0x00000211
1281#define DREG_REGID_RSD0_HIGH 0x00000212
1282#define DREG_REGID_RSD1_LOW 0x00000213
1283#define DREG_REGID_RSD1_HIGH 0x00000214
1284#define DREG_REGID_RSD2_LOW 0x00000215
1285#define DREG_REGID_RSD2_HIGH 0x00000216
1286#define DREG_REGID_RSD3_LOW 0x00000217
1287#define DREG_REGID_RSD3_HIGH 0x00000218
1288#define DREG_REGID_SRAR_HIGH 0x0000021A
1289#define DREG_REGID_SRAR_LOW 0x0000021B
1290#define DREG_REGID_DMA_STATE 0x0000021C
1291#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
1292#define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
1293#define DREG_REGID_CPU_STATUS 0x00000300
1294#define DREG_REGID_MAC_MODE 0x00000301
1295#define DREG_REGID_STACK_AND_REPEAT 0x00000302
1296#define DREG_REGID_INDEX0 0x00000304
1297#define DREG_REGID_INDEX1 0x00000305
1298#define DREG_REGID_DMA_STATE_0_3 0x00000400
1299#define DREG_REGID_DMA_STATE_4_7 0x00000404
1300#define DREG_REGID_DMA_STATE_8_11 0x00000408
1301#define DREG_REGID_DMA_STATE_12_15 0x0000040C
1302#define DREG_REGID_DMA_STATE_16_19 0x00000410
1303#define DREG_REGID_DMA_STATE_20_23 0x00000414
1304#define DREG_REGID_DMA_STATE_24_27 0x00000418
1305#define DREG_REGID_DMA_STATE_28_31 0x0000041C
1306#define DREG_REGID_DMA_STATE_32_35 0x00000420
1307#define DREG_REGID_DMA_STATE_36_39 0x00000424
1308#define DREG_REGID_DMA_STATE_40_43 0x00000428
1309#define DREG_REGID_DMA_STATE_44_47 0x0000042C
1310#define DREG_REGID_DMA_STATE_48_51 0x00000430
1311#define DREG_REGID_DMA_STATE_52_55 0x00000434
1312#define DREG_REGID_DMA_STATE_56_59 0x00000438
1313#define DREG_REGID_DMA_STATE_60_63 0x0000043C
1314#define DREG_REGID_DMA_STATE_64_67 0x00000440
1315#define DREG_REGID_DMA_STATE_68_71 0x00000444
1316#define DREG_REGID_DMA_STATE_72_75 0x00000448
1317#define DREG_REGID_DMA_STATE_76_79 0x0000044C
1318#define DREG_REGID_DMA_STATE_80_83 0x00000450
1319#define DREG_REGID_DMA_STATE_84_87 0x00000454
1320#define DREG_REGID_DMA_STATE_88_91 0x00000458
1321#define DREG_REGID_DMA_STATE_92_95 0x0000045C
1322#define DREG_REGID_TRAP_SELECT 0x00000500
1323#define DREG_REGID_TRAP_WRITE_0 0x00000500
1324#define DREG_REGID_TRAP_WRITE_1 0x00000501
1325#define DREG_REGID_TRAP_WRITE_2 0x00000502
1326#define DREG_REGID_TRAP_WRITE_3 0x00000503
1327#define DREG_REGID_TRAP_WRITE_4 0x00000504
1328#define DREG_REGID_TRAP_WRITE_5 0x00000505
1329#define DREG_REGID_TRAP_WRITE_6 0x00000506
1330#define DREG_REGID_TRAP_WRITE_7 0x00000507
1331#if !defined(NO_CS4612)
1332#if !defined(NO_CS4615)
1333#define DREG_REGID_TRAP_WRITE_8 0x00000510
1334#define DREG_REGID_TRAP_WRITE_9 0x00000511
1335#define DREG_REGID_TRAP_WRITE_10 0x00000512
1336#define DREG_REGID_TRAP_WRITE_11 0x00000513
1337#define DREG_REGID_TRAP_WRITE_12 0x00000514
1338#define DREG_REGID_TRAP_WRITE_13 0x00000515
1339#define DREG_REGID_TRAP_WRITE_14 0x00000516
1340#define DREG_REGID_TRAP_WRITE_15 0x00000517
1341#define DREG_REGID_TRAP_WRITE_16 0x00000518
1342#define DREG_REGID_TRAP_WRITE_17 0x00000519
1343#define DREG_REGID_TRAP_WRITE_18 0x0000051A
1344#define DREG_REGID_TRAP_WRITE_19 0x0000051B
1345#define DREG_REGID_TRAP_WRITE_20 0x0000051C
1346#define DREG_REGID_TRAP_WRITE_21 0x0000051D
1347#define DREG_REGID_TRAP_WRITE_22 0x0000051E
1348#define DREG_REGID_TRAP_WRITE_23 0x0000051F
1349#endif
1350#endif
1351#define DREG_REGID_MAC0_ACC0_LOW 0x00000600
1352#define DREG_REGID_MAC0_ACC1_LOW 0x00000601
1353#define DREG_REGID_MAC0_ACC2_LOW 0x00000602
1354#define DREG_REGID_MAC0_ACC3_LOW 0x00000603
1355#define DREG_REGID_MAC1_ACC0_LOW 0x00000604
1356#define DREG_REGID_MAC1_ACC1_LOW 0x00000605
1357#define DREG_REGID_MAC1_ACC2_LOW 0x00000606
1358#define DREG_REGID_MAC1_ACC3_LOW 0x00000607
1359#define DREG_REGID_MAC0_ACC0_MID 0x00000608
1360#define DREG_REGID_MAC0_ACC1_MID 0x00000609
1361#define DREG_REGID_MAC0_ACC2_MID 0x0000060A
1362#define DREG_REGID_MAC0_ACC3_MID 0x0000060B
1363#define DREG_REGID_MAC1_ACC0_MID 0x0000060C
1364#define DREG_REGID_MAC1_ACC1_MID 0x0000060D
1365#define DREG_REGID_MAC1_ACC2_MID 0x0000060E
1366#define DREG_REGID_MAC1_ACC3_MID 0x0000060F
1367#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
1368#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
1369#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
1370#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
1371#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
1372#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
1373#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
1374#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
1375#define DREG_REGID_RSHOUT_LOW 0x00000620
1376#define DREG_REGID_RSHOUT_MID 0x00000628
1377#define DREG_REGID_RSHOUT_HIGH 0x00000630
1378
1379/*
1380 * The following defines are for the flags in the DMA stream requestor write
1381 */
1382#define DSRWP_DSR_MASK 0x0000000F
1383#define DSRWP_DSR_BG_RQ 0x00000001
1384#define DSRWP_DSR_PRIORITY_MASK 0x00000006
1385#define DSRWP_DSR_PRIORITY_0 0x00000000
1386#define DSRWP_DSR_PRIORITY_1 0x00000002
1387#define DSRWP_DSR_PRIORITY_2 0x00000004
1388#define DSRWP_DSR_PRIORITY_3 0x00000006
1389#define DSRWP_DSR_RQ_PENDING 0x00000008
1390
1391/*
1392 * The following defines are for the flags in the trap write port register.
1393 */
1394#define TWPR_TW_MASK 0x0000FFFF
1395#define TWPR_TW_SHIFT 0
1396
1397/*
1398 * The following defines are for the flags in the stack pointer write
1399 * register.
1400 */
1401#define SPWR_STKP_MASK 0x0000000F
1402#define SPWR_STKP_SHIFT 0
1403
1404/*
1405 * The following defines are for the flags in the SP interrupt register.
1406 */
1407#define SPIR_FRI 0x00000001
1408#define SPIR_DOI 0x00000002
1409#define SPIR_GPI2 0x00000004
1410#define SPIR_GPI3 0x00000008
1411#define SPIR_IP0 0x00000010
1412#define SPIR_IP1 0x00000020
1413#define SPIR_IP2 0x00000040
1414#define SPIR_IP3 0x00000080
1415
1416/*
1417 * The following defines are for the flags in the functional group 1 register.
1418 */
1419#define FGR1_F1S_MASK 0x0000FFFF
1420#define FGR1_F1S_SHIFT 0
1421
1422/*
1423 * The following defines are for the flags in the SP clock status register.
1424 */
1425#define SPCS_FRI 0x00000001
1426#define SPCS_DOI 0x00000002
1427#define SPCS_GPI2 0x00000004
1428#define SPCS_GPI3 0x00000008
1429#define SPCS_IP0 0x00000010
1430#define SPCS_IP1 0x00000020
1431#define SPCS_IP2 0x00000040
1432#define SPCS_IP3 0x00000080
1433#define SPCS_SPRUN 0x00000100
1434#define SPCS_SLEEP 0x00000200
1435#define SPCS_FG 0x00000400
1436#define SPCS_ORUN 0x00000800
1437#define SPCS_IRQ 0x00001000
1438#define SPCS_FGN_MASK 0x0000E000
1439#define SPCS_FGN_SHIFT 13
1440
1441/*
1442 * The following defines are for the flags in the SP DMA requestor status
1443 * register.
1444 */
1445#define SDSR_DCS_MASK 0x000000FF
1446#define SDSR_DCS_SHIFT 0
1447#define SDSR_DCS_NONE 0x00000007
1448
1449/*
1450 * The following defines are for the flags in the frame timer register.
1451 */
1452#define FRMT_FTV_MASK 0x0000FFFF
1453#define FRMT_FTV_SHIFT 0
1454
1455/*
1456 * The following defines are for the flags in the frame timer current count
1457 * register.
1458 */
1459#define FRCC_FCC_MASK 0x0000FFFF
1460#define FRCC_FCC_SHIFT 0
1461
1462/*
1463 * The following defines are for the flags in the frame timer save count
1464 * register.
1465 */
1466#define FRSC_FCS_MASK 0x0000FFFF
1467#define FRSC_FCS_SHIFT 0
1468
1469/*
1470 * The following define the various flags stored in the scatter/gather
1471 * descriptors.
1472 */
1473#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
1474#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
1475#define DMA_SG_SAMPLE_END_FLAG 0x10000000
1476#define DMA_SG_LOOP_END_FLAG 0x20000000
1477#define DMA_SG_SIGNAL_END_FLAG 0x40000000
1478#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
1479#define DMA_SG_NEXT_ENTRY_SHIFT 3
1480#define DMA_SG_SAMPLE_END_SHIFT 16
1481
1482/*
1483 * The following define the offsets of the fields within the on-chip generic
1484 * DMA requestor.
1485 */
1486#define DMA_RQ_CONTROL1 0x00000000
1487#define DMA_RQ_CONTROL2 0x00000004
1488#define DMA_RQ_SOURCE_ADDR 0x00000008
1489#define DMA_RQ_DESTINATION_ADDR 0x0000000C
1490#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
1491#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
1492#define DMA_RQ_LOOP_START_ADDR 0x00000018
1493#define DMA_RQ_POST_LOOP_ADDR 0x0000001C
1494#define DMA_RQ_PAGE_MAP_ADDR 0x00000020
1495
1496/*
1497 * The following defines are for the flags in the first control word of the
1498 * on-chip generic DMA requestor.
1499 */
1500#define DMA_RQ_C1_COUNT_MASK 0x000003FF
1501#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
1502#define DMA_RQ_C1_SOURCE_GATHER 0x00002000
1503#define DMA_RQ_C1_DONE_FLAG 0x00004000
1504#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
1505#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
1506#define DMA_RQ_C1_FULL_PAGE 0x00000000
1507#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
1508#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
1509#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
1510#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
1511#define DMA_RQ_C1_NOT_LOOP_END 0x00000000
1512#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
1513#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
1514#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
1515#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
1516#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
1517#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
1518#define DMA_RQ_C1_PM_RESERVED 0x00200000
1519#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
1520#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
1521#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
1522#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
1523#define DMA_RQ_C1_DEST_LINEAR 0x00000000
1524#define DMA_RQ_C1_DEST_MOD16 0x01000000
1525#define DMA_RQ_C1_DEST_MOD32 0x02000000
1526#define DMA_RQ_C1_DEST_MOD64 0x03000000
1527#define DMA_RQ_C1_DEST_MOD128 0x04000000
1528#define DMA_RQ_C1_DEST_MOD256 0x05000000
1529#define DMA_RQ_C1_DEST_MOD512 0x06000000
1530#define DMA_RQ_C1_DEST_MOD1024 0x07000000
1531#define DMA_RQ_C1_DEST_ON_HOST 0x08000000
1532#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
1533#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
1534#define DMA_RQ_C1_SOURCE_MOD16 0x10000000
1535#define DMA_RQ_C1_SOURCE_MOD32 0x20000000
1536#define DMA_RQ_C1_SOURCE_MOD64 0x30000000
1537#define DMA_RQ_C1_SOURCE_MOD128 0x40000000
1538#define DMA_RQ_C1_SOURCE_MOD256 0x50000000
1539#define DMA_RQ_C1_SOURCE_MOD512 0x60000000
1540#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
1541#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
1542#define DMA_RQ_C1_COUNT_SHIFT 0
1543
1544/*
1545 * The following defines are for the flags in the second control word of the
1546 * on-chip generic DMA requestor.
1547 */
1548#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
1549#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
1550#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
1551#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
1552#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
1553#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
1554#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
1555#define DMA_RQ_C2_AC_NONE 0x00000000
1556#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
1557#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
1558#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
1559#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
1560#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
1561#define DMA_RQ_C2_LOOP_MASK 0x30000000
1562#define DMA_RQ_C2_NO_LOOP 0x00000000
1563#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
1564#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
1565#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
1566#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
1567#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
1568#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
1569#define DMA_RQ_C2_LOOP_END_SHIFT 16
1570
1571/*
1572 * The following defines are for the flags in the source and destination words
1573 * of the on-chip generic DMA requestor.
1574 */
1575#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
1576#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
1577#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
1578#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
1579#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
1580#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
1581#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
1582#define DMA_RQ_SD_END_FLAG 0x40000000
1583#define DMA_RQ_SD_ERROR_FLAG 0x80000000
1584#define DMA_RQ_SD_ADDRESS_SHIFT 0
1585
1586/*
1587 * The following defines are for the flags in the page map address word of the
1588 * on-chip generic DMA requestor.
1589 */
1590#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
1591#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
1592#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
1593#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
1594
1595#define BA1_VARIDEC_BUF_1 0x000
1596
1597#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
1598#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
1599#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
1600#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
1601#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
1602#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
1603#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
1604
1605#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
1606#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
1607#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
1608#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
1609#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
1610#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
1611#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
1612#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
1613
1614#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
1615#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
1616#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
1617#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
1618
1619/*
1620 *
1621 */
1622
1623#define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */
1624#define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */
1625
1626/*
1627 *
1628 */
1629
1630#define SAVE_REG_MAX 0x10
1631#define POWER_DOWN_ALL 0x7f0f
1632
1633/* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
1634#define MAX_NR_AC97 4
1635#define CS46XX_PRIMARY_CODEC_INDEX 0
1636#define CS46XX_SECONDARY_CODEC_INDEX 1
1637#define CS46XX_SECONDARY_CODEC_OFFSET 0x80
1638#define CS46XX_DSP_CAPTURE_CHANNEL 1
1639
1640/* capture */
1641#define CS46XX_DSP_CAPTURE_CHANNEL 1
1642
1643/* mixer */
1644#define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1
1645#define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2
1646
1647typedef struct _snd_cs46xx cs46xx_t;
1648
1649typedef struct _snd_cs46xx_pcm_t {
1650 struct snd_dma_buffer hw_buf;
1651
1652 unsigned int ctl;
1653 unsigned int shift; /* Shift count to trasform frames in bytes */
1654 snd_pcm_indirect_t pcm_rec;
1655 snd_pcm_substream_t *substream;
1656
1657 pcm_channel_descriptor_t * pcm_channel;
1658
1659 int pcm_channel_id; /* Fron Rear, Center Lfe ... */
1660} cs46xx_pcm_t;
1661
1662typedef struct {
1663 char name[24];
1664 unsigned long base;
1665 void __iomem *remap_addr;
1666 unsigned long size;
1667 struct resource *resource;
1668} snd_cs46xx_region_t;
1669
1670struct _snd_cs46xx {
1671 int irq;
1672 unsigned long ba0_addr;
1673 unsigned long ba1_addr;
1674 union {
1675 struct {
1676 snd_cs46xx_region_t ba0;
1677 snd_cs46xx_region_t data0;
1678 snd_cs46xx_region_t data1;
1679 snd_cs46xx_region_t pmem;
1680 snd_cs46xx_region_t reg;
1681 } name;
1682 snd_cs46xx_region_t idx[5];
1683 } region;
1684
1685 unsigned int mode;
1686
1687 struct {
1688 struct snd_dma_buffer hw_buf;
1689
1690 unsigned int ctl;
1691 unsigned int shift; /* Shift count to trasform frames in bytes */
1692 snd_pcm_indirect_t pcm_rec;
1693 snd_pcm_substream_t *substream;
1694 } capt;
1695
1696
1697 int nr_ac97_codecs;
1698 ac97_bus_t *ac97_bus;
1699 ac97_t *ac97[MAX_NR_AC97];
1700
1701 struct pci_dev *pci;
1702 snd_card_t *card;
1703 snd_pcm_t *pcm;
1704
1705 snd_rawmidi_t *rmidi;
1706 snd_rawmidi_substream_t *midi_input;
1707 snd_rawmidi_substream_t *midi_output;
1708
1709 spinlock_t reg_lock;
1710 unsigned int midcr;
1711 unsigned int uartm;
1712
1713 int amplifier;
1714 void (*amplifier_ctrl)(cs46xx_t *, int);
1715 void (*active_ctrl)(cs46xx_t *, int);
1716 void (*mixer_init)(cs46xx_t *);
1717
1718 struct pci_dev *acpi_dev;
1719 int acpi_port;
1720 snd_kcontrol_t *eapd_switch; /* for amplifier hack */
1721 int accept_valid; /* accept mmap valid (for OSS) */
1722
1723 struct gameport *gameport;
1724
1725#ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
1726 int current_gpio;
1727#endif
1728#ifdef CONFIG_SND_CS46XX_NEW_DSP
1729 struct semaphore spos_mutex;
1730
1731 dsp_spos_instance_t * dsp_spos_instance;
1732
1733 snd_pcm_t *pcm_rear;
1734 snd_pcm_t *pcm_center_lfe;
1735 snd_pcm_t *pcm_iec958;
1736#else /* for compatibility */
1737 cs46xx_pcm_t *playback_pcm;
1738 unsigned int play_ctl;
1739#endif
1740};
1741
1742int snd_cs46xx_create(snd_card_t *card,
1743 struct pci_dev *pci,
1744 int external_amp, int thinkpad,
1745 cs46xx_t **rcodec);
1746
1747int snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1748int snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1749int snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1750int snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
1751int snd_cs46xx_mixer(cs46xx_t *chip);
1752int snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rmidi);
1753int snd_cs46xx_start_dsp(cs46xx_t *chip);
1754int snd_cs46xx_gameport(cs46xx_t *chip);
1755
1756#endif /* __SOUND_CS46XX_H */