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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Pierre Ossman70f10482007-07-11 20:04:50 +02002 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
Russell Kingc8ebae32011-01-11 19:35:53 +00005 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
Russell King613b1522011-01-30 21:06:53 +000017#include <linux/kernel.h>
Lee Jones000bc9d2012-04-16 10:18:43 +010018#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/highmem.h>
Nicolas Pitre019a5f52007-10-11 01:06:03 -040022#include <linux/log2.h>
Ulf Hansson70be2082013-01-07 15:35:06 +010023#include <linux/mmc/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/mmc/host.h>
Linus Walleij34177802010-10-19 12:43:58 +010025#include <linux/mmc/card.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000026#include <linux/amba/bus.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000027#include <linux/clk.h>
Jens Axboebd6dee62007-10-24 09:01:09 +020028#include <linux/scatterlist.h>
Russell King89001442009-07-09 15:16:07 +010029#include <linux/gpio.h>
Lee Jones9a597012012-04-12 16:51:13 +010030#include <linux/of_gpio.h>
Linus Walleij34e84f32009-09-22 14:41:40 +010031#include <linux/regulator/consumer.h>
Russell Kingc8ebae32011-01-11 19:35:53 +000032#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/amba/mmci.h>
Russell King1c3be362011-08-14 09:17:05 +010035#include <linux/pm_runtime.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053036#include <linux/types.h>
Linus Walleija9a83782012-10-29 14:39:30 +010037#include <linux/pinctrl/consumer.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Russell King7b09cda2005-07-01 12:02:59 +010039#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/io.h>
Russell Kingc6b8fda2005-10-28 14:05:16 +010041#include <asm/sizes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
43#include "mmci.h"
44
45#define DRIVER_NAME "mmci-pl18x"
46
Linus Torvalds1da177e2005-04-16 15:20:36 -070047static unsigned int fmax = 515633;
48
Rabin Vincent4956e102010-07-21 12:54:40 +010049/**
50 * struct variant_data - MMCI variant-specific quirks
51 * @clkreg: default value for MCICLOCK register
Rabin Vincent4380c142010-07-21 12:55:18 +010052 * @clkreg_enable: enable value for MMCICLOCK register
Rabin Vincent08458ef2010-07-21 12:55:59 +010053 * @datalength_bits: number of bits in the MMCIDATALENGTH register
Rabin Vincent8301bb62010-08-09 12:57:30 +010054 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
55 * is asserted (likewise for RX)
56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
57 * is asserted (likewise for RX)
Linus Walleij34177802010-10-19 12:43:58 +010058 * @sdio: variant supports SDIO
Linus Walleijb70a67f2010-12-06 09:24:14 +010059 * @st_clkdiv: true if using a ST-specific clock divider algorithm
Philippe Langlais1784b152011-03-25 08:51:52 +010060 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010061 * @pwrreg_powerup: power up value for MMCIPOWER register
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010062 * @signal_direction: input/out direction of bus signals can be indicated
Ulf Hanssonf4670da2013-01-09 17:19:54 +010063 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
Ulf Hansson01259622013-05-15 20:53:22 +010064 * @busy_detect: true if busy detection on dat0 is supported
Ulf Hansson1ff44432013-09-04 09:05:17 +010065 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
Rabin Vincent4956e102010-07-21 12:54:40 +010066 */
67struct variant_data {
68 unsigned int clkreg;
Rabin Vincent4380c142010-07-21 12:55:18 +010069 unsigned int clkreg_enable;
Rabin Vincent08458ef2010-07-21 12:55:59 +010070 unsigned int datalength_bits;
Rabin Vincent8301bb62010-08-09 12:57:30 +010071 unsigned int fifosize;
72 unsigned int fifohalfsize;
Linus Walleij34177802010-10-19 12:43:58 +010073 bool sdio;
Linus Walleijb70a67f2010-12-06 09:24:14 +010074 bool st_clkdiv;
Philippe Langlais1784b152011-03-25 08:51:52 +010075 bool blksz_datactrl16;
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010076 u32 pwrreg_powerup;
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010077 bool signal_direction;
Ulf Hanssonf4670da2013-01-09 17:19:54 +010078 bool pwrreg_clkgate;
Ulf Hansson01259622013-05-15 20:53:22 +010079 bool busy_detect;
Ulf Hansson1ff44432013-09-04 09:05:17 +010080 bool pwrreg_nopower;
Rabin Vincent4956e102010-07-21 12:54:40 +010081};
82
83static struct variant_data variant_arm = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010084 .fifosize = 16 * 4,
85 .fifohalfsize = 8 * 4,
Rabin Vincent08458ef2010-07-21 12:55:59 +010086 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010087 .pwrreg_powerup = MCI_PWR_UP,
Rabin Vincent4956e102010-07-21 12:54:40 +010088};
89
Pawel Moll768fbc12011-03-11 17:18:07 +000090static struct variant_data variant_arm_extended_fifo = {
91 .fifosize = 128 * 4,
92 .fifohalfsize = 64 * 4,
93 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010094 .pwrreg_powerup = MCI_PWR_UP,
Pawel Moll768fbc12011-03-11 17:18:07 +000095};
96
Pawel Moll3a372982013-01-24 14:12:45 +010097static struct variant_data variant_arm_extended_fifo_hwfc = {
98 .fifosize = 128 * 4,
99 .fifohalfsize = 64 * 4,
100 .clkreg_enable = MCI_ARM_HWFCEN,
101 .datalength_bits = 16,
102 .pwrreg_powerup = MCI_PWR_UP,
103};
104
Rabin Vincent4956e102010-07-21 12:54:40 +0100105static struct variant_data variant_u300 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100106 .fifosize = 16 * 4,
107 .fifohalfsize = 8 * 4,
Linus Walleij49ac2152011-03-04 14:54:16 +0100108 .clkreg_enable = MCI_ST_U300_HWFCEN,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100109 .datalength_bits = 16,
Linus Walleij34177802010-10-19 12:43:58 +0100110 .sdio = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100111 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100112 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100113 .pwrreg_clkgate = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100114 .pwrreg_nopower = true,
Rabin Vincent4956e102010-07-21 12:54:40 +0100115};
116
Linus Walleij34fd4212012-04-10 17:43:59 +0100117static struct variant_data variant_nomadik = {
118 .fifosize = 16 * 4,
119 .fifohalfsize = 8 * 4,
120 .clkreg = MCI_CLK_ENABLE,
121 .datalength_bits = 24,
122 .sdio = true,
123 .st_clkdiv = true,
124 .pwrreg_powerup = MCI_PWR_ON,
125 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100126 .pwrreg_clkgate = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100127 .pwrreg_nopower = true,
Linus Walleij34fd4212012-04-10 17:43:59 +0100128};
129
Rabin Vincent4956e102010-07-21 12:54:40 +0100130static struct variant_data variant_ux500 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100131 .fifosize = 30 * 4,
132 .fifohalfsize = 8 * 4,
Rabin Vincent4956e102010-07-21 12:54:40 +0100133 .clkreg = MCI_CLK_ENABLE,
Linus Walleij49ac2152011-03-04 14:54:16 +0100134 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100135 .datalength_bits = 24,
Linus Walleij34177802010-10-19 12:43:58 +0100136 .sdio = true,
Linus Walleijb70a67f2010-12-06 09:24:14 +0100137 .st_clkdiv = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100138 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100139 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100140 .pwrreg_clkgate = true,
Ulf Hansson01259622013-05-15 20:53:22 +0100141 .busy_detect = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100142 .pwrreg_nopower = true,
Rabin Vincent4956e102010-07-21 12:54:40 +0100143};
Linus Walleijb70a67f2010-12-06 09:24:14 +0100144
Philippe Langlais1784b152011-03-25 08:51:52 +0100145static struct variant_data variant_ux500v2 = {
146 .fifosize = 30 * 4,
147 .fifohalfsize = 8 * 4,
148 .clkreg = MCI_CLK_ENABLE,
149 .clkreg_enable = MCI_ST_UX500_HWFCEN,
150 .datalength_bits = 24,
151 .sdio = true,
152 .st_clkdiv = true,
153 .blksz_datactrl16 = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100154 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100155 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100156 .pwrreg_clkgate = true,
Ulf Hansson01259622013-05-15 20:53:22 +0100157 .busy_detect = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100158 .pwrreg_nopower = true,
Philippe Langlais1784b152011-03-25 08:51:52 +0100159};
160
Ulf Hansson01259622013-05-15 20:53:22 +0100161static int mmci_card_busy(struct mmc_host *mmc)
162{
163 struct mmci_host *host = mmc_priv(mmc);
164 unsigned long flags;
165 int busy = 0;
166
167 pm_runtime_get_sync(mmc_dev(mmc));
168
169 spin_lock_irqsave(&host->lock, flags);
170 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
171 busy = 1;
172 spin_unlock_irqrestore(&host->lock, flags);
173
174 pm_runtime_mark_last_busy(mmc_dev(mmc));
175 pm_runtime_put_autosuspend(mmc_dev(mmc));
176
177 return busy;
178}
179
Linus Walleija6a64642009-09-14 12:56:14 +0100180/*
Ulf Hansson653a7612013-01-21 21:29:34 +0100181 * Validate mmc prerequisites
182 */
183static int mmci_validate_data(struct mmci_host *host,
184 struct mmc_data *data)
185{
186 if (!data)
187 return 0;
188
189 if (!is_power_of_2(data->blksz)) {
190 dev_err(mmc_dev(host->mmc),
191 "unsupported block size (%d bytes)\n", data->blksz);
192 return -EINVAL;
193 }
194
195 return 0;
196}
197
Ulf Hanssonf829c042013-09-04 09:01:15 +0100198static void mmci_reg_delay(struct mmci_host *host)
199{
200 /*
201 * According to the spec, at least three feedback clock cycles
202 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
203 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
204 * Worst delay time during card init is at 100 kHz => 30 us.
205 * Worst delay time when up and running is at 25 MHz => 120 ns.
206 */
207 if (host->cclk < 25000000)
208 udelay(30);
209 else
210 ndelay(120);
211}
212
Ulf Hansson653a7612013-01-21 21:29:34 +0100213/*
Linus Walleija6a64642009-09-14 12:56:14 +0100214 * This must be called with host->lock held
215 */
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100216static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
217{
218 if (host->clk_reg != clk) {
219 host->clk_reg = clk;
220 writel(clk, host->base + MMCICLOCK);
221 }
222}
223
224/*
225 * This must be called with host->lock held
226 */
227static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
228{
229 if (host->pwr_reg != pwr) {
230 host->pwr_reg = pwr;
231 writel(pwr, host->base + MMCIPOWER);
232 }
233}
234
235/*
236 * This must be called with host->lock held
237 */
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100238static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
239{
Ulf Hansson01259622013-05-15 20:53:22 +0100240 /* Keep ST Micro busy mode if enabled */
241 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
242
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100243 if (host->datactrl_reg != datactrl) {
244 host->datactrl_reg = datactrl;
245 writel(datactrl, host->base + MMCIDATACTRL);
246 }
247}
248
249/*
250 * This must be called with host->lock held
251 */
Linus Walleija6a64642009-09-14 12:56:14 +0100252static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
253{
Rabin Vincent4956e102010-07-21 12:54:40 +0100254 struct variant_data *variant = host->variant;
255 u32 clk = variant->clkreg;
Linus Walleija6a64642009-09-14 12:56:14 +0100256
Ulf Hanssonc58a8502013-05-13 15:40:03 +0100257 /* Make sure cclk reflects the current calculated clock */
258 host->cclk = 0;
259
Linus Walleija6a64642009-09-14 12:56:14 +0100260 if (desired) {
261 if (desired >= host->mclk) {
Linus Walleij991a86e2010-12-10 09:35:53 +0100262 clk = MCI_CLK_BYPASS;
Linus Walleij399bc482011-04-01 07:59:17 +0100263 if (variant->st_clkdiv)
264 clk |= MCI_ST_UX500_NEG_EDGE;
Linus Walleija6a64642009-09-14 12:56:14 +0100265 host->cclk = host->mclk;
Linus Walleijb70a67f2010-12-06 09:24:14 +0100266 } else if (variant->st_clkdiv) {
267 /*
268 * DB8500 TRM says f = mclk / (clkdiv + 2)
269 * => clkdiv = (mclk / f) - 2
270 * Round the divider up so we don't exceed the max
271 * frequency
272 */
273 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
274 if (clk >= 256)
275 clk = 255;
276 host->cclk = host->mclk / (clk + 2);
Linus Walleija6a64642009-09-14 12:56:14 +0100277 } else {
Linus Walleijb70a67f2010-12-06 09:24:14 +0100278 /*
279 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
280 * => clkdiv = mclk / (2 * f) - 1
281 */
Linus Walleija6a64642009-09-14 12:56:14 +0100282 clk = host->mclk / (2 * desired) - 1;
283 if (clk >= 256)
284 clk = 255;
285 host->cclk = host->mclk / (2 * (clk + 1));
286 }
Rabin Vincent4380c142010-07-21 12:55:18 +0100287
288 clk |= variant->clkreg_enable;
Linus Walleija6a64642009-09-14 12:56:14 +0100289 clk |= MCI_CLK_ENABLE;
290 /* This hasn't proven to be worthwhile */
291 /* clk |= MCI_CLK_PWRSAVE; */
292 }
293
Ulf Hanssonc58a8502013-05-13 15:40:03 +0100294 /* Set actual clock for debug */
295 host->mmc->actual_clock = host->cclk;
296
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100297 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
Linus Walleij771dc152010-04-08 07:38:52 +0100298 clk |= MCI_4BIT_BUS;
299 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
300 clk |= MCI_ST_8BIT_BUS;
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100301
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100302 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
303 clk |= MCI_ST_UX500_NEG_EDGE;
304
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100305 mmci_write_clkreg(host, clk);
Linus Walleija6a64642009-09-14 12:56:14 +0100306}
307
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308static void
309mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
310{
311 writel(0, host->base + MMCICOMMAND);
312
Russell Kinge47c2222007-01-08 16:42:51 +0000313 BUG_ON(host->data);
314
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 host->mrq = NULL;
316 host->cmd = NULL;
317
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 mmc_request_done(host->mmc, mrq);
Ulf Hansson2cd976c2011-12-13 17:01:11 +0100319
320 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
321 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322}
323
Linus Walleij2686b4b2010-10-19 12:39:48 +0100324static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
325{
326 void __iomem *base = host->base;
327
328 if (host->singleirq) {
329 unsigned int mask0 = readl(base + MMCIMASK0);
330
331 mask0 &= ~MCI_IRQ1MASK;
332 mask0 |= mask;
333
334 writel(mask0, base + MMCIMASK0);
335 }
336
337 writel(mask, base + MMCIMASK1);
338}
339
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340static void mmci_stop_data(struct mmci_host *host)
341{
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100342 mmci_write_datactrlreg(host, 0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100343 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 host->data = NULL;
345}
346
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100347static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
348{
349 unsigned int flags = SG_MITER_ATOMIC;
350
351 if (data->flags & MMC_DATA_READ)
352 flags |= SG_MITER_TO_SG;
353 else
354 flags |= SG_MITER_FROM_SG;
355
356 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
357}
358
Russell Kingc8ebae32011-01-11 19:35:53 +0000359/*
360 * All the DMA operation mode stuff goes inside this ifdef.
361 * This assumes that you have a generic DMA device interface,
362 * no custom DMA interfaces are supported.
363 */
364#ifdef CONFIG_DMA_ENGINE
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500365static void mmci_dma_setup(struct mmci_host *host)
Russell Kingc8ebae32011-01-11 19:35:53 +0000366{
367 struct mmci_platform_data *plat = host->plat;
368 const char *rxname, *txname;
369 dma_cap_mask_t mask;
370
Lee Jones1fd83f02013-05-03 12:51:17 +0100371 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
372 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
Russell Kingc8ebae32011-01-11 19:35:53 +0000373
Per Forlin58c7ccb2011-07-01 18:55:24 +0200374 /* initialize pre request cookie */
375 host->next_data.cookie = 1;
376
Russell Kingc8ebae32011-01-11 19:35:53 +0000377 /* Try to acquire a generic DMA engine slave channel */
378 dma_cap_zero(mask);
379 dma_cap_set(DMA_SLAVE, mask);
380
Lee Jones1fd83f02013-05-03 12:51:17 +0100381 if (plat && plat->dma_filter) {
382 if (!host->dma_rx_channel && plat->dma_rx_param) {
383 host->dma_rx_channel = dma_request_channel(mask,
384 plat->dma_filter,
385 plat->dma_rx_param);
386 /* E.g if no DMA hardware is present */
387 if (!host->dma_rx_channel)
388 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
389 }
390
391 if (!host->dma_tx_channel && plat->dma_tx_param) {
392 host->dma_tx_channel = dma_request_channel(mask,
393 plat->dma_filter,
394 plat->dma_tx_param);
395 if (!host->dma_tx_channel)
396 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
397 }
398 }
399
Russell Kingc8ebae32011-01-11 19:35:53 +0000400 /*
401 * If only an RX channel is specified, the driver will
402 * attempt to use it bidirectionally, however if it is
403 * is specified but cannot be located, DMA will be disabled.
404 */
Lee Jones1fd83f02013-05-03 12:51:17 +0100405 if (host->dma_rx_channel && !host->dma_tx_channel)
Russell Kingc8ebae32011-01-11 19:35:53 +0000406 host->dma_tx_channel = host->dma_rx_channel;
Russell Kingc8ebae32011-01-11 19:35:53 +0000407
408 if (host->dma_rx_channel)
409 rxname = dma_chan_name(host->dma_rx_channel);
410 else
411 rxname = "none";
412
413 if (host->dma_tx_channel)
414 txname = dma_chan_name(host->dma_tx_channel);
415 else
416 txname = "none";
417
418 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
419 rxname, txname);
420
421 /*
422 * Limit the maximum segment size in any SG entry according to
423 * the parameters of the DMA engine device.
424 */
425 if (host->dma_tx_channel) {
426 struct device *dev = host->dma_tx_channel->device->dev;
427 unsigned int max_seg_size = dma_get_max_seg_size(dev);
428
429 if (max_seg_size < host->mmc->max_seg_size)
430 host->mmc->max_seg_size = max_seg_size;
431 }
432 if (host->dma_rx_channel) {
433 struct device *dev = host->dma_rx_channel->device->dev;
434 unsigned int max_seg_size = dma_get_max_seg_size(dev);
435
436 if (max_seg_size < host->mmc->max_seg_size)
437 host->mmc->max_seg_size = max_seg_size;
438 }
439}
440
441/*
Bill Pemberton6e0ee712012-11-19 13:26:03 -0500442 * This is used in or so inline it
Russell Kingc8ebae32011-01-11 19:35:53 +0000443 * so it can be discarded.
444 */
445static inline void mmci_dma_release(struct mmci_host *host)
446{
447 struct mmci_platform_data *plat = host->plat;
448
449 if (host->dma_rx_channel)
450 dma_release_channel(host->dma_rx_channel);
451 if (host->dma_tx_channel && plat->dma_tx_param)
452 dma_release_channel(host->dma_tx_channel);
453 host->dma_rx_channel = host->dma_tx_channel = NULL;
454}
455
Ulf Hansson653a7612013-01-21 21:29:34 +0100456static void mmci_dma_data_error(struct mmci_host *host)
457{
458 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
459 dmaengine_terminate_all(host->dma_current);
460 host->dma_current = NULL;
461 host->dma_desc_current = NULL;
462 host->data->host_cookie = 0;
463}
464
Russell Kingc8ebae32011-01-11 19:35:53 +0000465static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
466{
Ulf Hansson653a7612013-01-21 21:29:34 +0100467 struct dma_chan *chan;
Russell Kingc8ebae32011-01-11 19:35:53 +0000468 enum dma_data_direction dir;
Ulf Hansson653a7612013-01-21 21:29:34 +0100469
470 if (data->flags & MMC_DATA_READ) {
471 dir = DMA_FROM_DEVICE;
472 chan = host->dma_rx_channel;
473 } else {
474 dir = DMA_TO_DEVICE;
475 chan = host->dma_tx_channel;
476 }
477
478 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
479}
480
481static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
482{
Russell Kingc8ebae32011-01-11 19:35:53 +0000483 u32 status;
484 int i;
485
486 /* Wait up to 1ms for the DMA to complete */
487 for (i = 0; ; i++) {
488 status = readl(host->base + MMCISTATUS);
489 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
490 break;
491 udelay(10);
492 }
493
494 /*
495 * Check to see whether we still have some data left in the FIFO -
496 * this catches DMA controllers which are unable to monitor the
497 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
498 * contiguous buffers. On TX, we'll get a FIFO underrun error.
499 */
500 if (status & MCI_RXDATAAVLBLMASK) {
Ulf Hansson653a7612013-01-21 21:29:34 +0100501 mmci_dma_data_error(host);
Russell Kingc8ebae32011-01-11 19:35:53 +0000502 if (!data->error)
503 data->error = -EIO;
504 }
505
Per Forlin58c7ccb2011-07-01 18:55:24 +0200506 if (!data->host_cookie)
Ulf Hansson653a7612013-01-21 21:29:34 +0100507 mmci_dma_unmap(host, data);
Russell Kingc8ebae32011-01-11 19:35:53 +0000508
509 /*
510 * Use of DMA with scatter-gather is impossible.
511 * Give up with DMA and switch back to PIO mode.
512 */
513 if (status & MCI_RXDATAAVLBLMASK) {
514 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
515 mmci_dma_release(host);
516 }
Ulf Hansson653a7612013-01-21 21:29:34 +0100517
518 host->dma_current = NULL;
519 host->dma_desc_current = NULL;
Russell Kingc8ebae32011-01-11 19:35:53 +0000520}
521
Ulf Hansson653a7612013-01-21 21:29:34 +0100522/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
523static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
524 struct dma_chan **dma_chan,
525 struct dma_async_tx_descriptor **dma_desc)
Russell Kingc8ebae32011-01-11 19:35:53 +0000526{
527 struct variant_data *variant = host->variant;
528 struct dma_slave_config conf = {
529 .src_addr = host->phybase + MMCIFIFO,
530 .dst_addr = host->phybase + MMCIFIFO,
531 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
532 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
533 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
534 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
Viresh Kumar258aea72012-02-01 16:12:19 +0530535 .device_fc = false,
Russell Kingc8ebae32011-01-11 19:35:53 +0000536 };
Russell Kingc8ebae32011-01-11 19:35:53 +0000537 struct dma_chan *chan;
538 struct dma_device *device;
539 struct dma_async_tx_descriptor *desc;
Vinod Koul05f57992011-10-14 10:45:11 +0530540 enum dma_data_direction buffer_dirn;
Russell Kingc8ebae32011-01-11 19:35:53 +0000541 int nr_sg;
542
Russell Kingc8ebae32011-01-11 19:35:53 +0000543 if (data->flags & MMC_DATA_READ) {
Vinod Koul05f57992011-10-14 10:45:11 +0530544 conf.direction = DMA_DEV_TO_MEM;
545 buffer_dirn = DMA_FROM_DEVICE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000546 chan = host->dma_rx_channel;
547 } else {
Vinod Koul05f57992011-10-14 10:45:11 +0530548 conf.direction = DMA_MEM_TO_DEV;
549 buffer_dirn = DMA_TO_DEVICE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000550 chan = host->dma_tx_channel;
551 }
552
553 /* If there's no DMA channel, fall back to PIO */
554 if (!chan)
555 return -EINVAL;
556
557 /* If less than or equal to the fifo size, don't bother with DMA */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200558 if (data->blksz * data->blocks <= variant->fifosize)
Russell Kingc8ebae32011-01-11 19:35:53 +0000559 return -EINVAL;
560
561 device = chan->device;
Vinod Koul05f57992011-10-14 10:45:11 +0530562 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
Russell Kingc8ebae32011-01-11 19:35:53 +0000563 if (nr_sg == 0)
564 return -EINVAL;
565
566 dmaengine_slave_config(chan, &conf);
Alexandre Bounine16052822012-03-08 16:11:18 -0500567 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
Russell Kingc8ebae32011-01-11 19:35:53 +0000568 conf.direction, DMA_CTRL_ACK);
569 if (!desc)
570 goto unmap_exit;
571
Ulf Hansson653a7612013-01-21 21:29:34 +0100572 *dma_chan = chan;
573 *dma_desc = desc;
Russell Kingc8ebae32011-01-11 19:35:53 +0000574
Per Forlin58c7ccb2011-07-01 18:55:24 +0200575 return 0;
576
577 unmap_exit:
Vinod Koul05f57992011-10-14 10:45:11 +0530578 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200579 return -ENOMEM;
580}
581
Ulf Hansson653a7612013-01-21 21:29:34 +0100582static inline int mmci_dma_prep_data(struct mmci_host *host,
583 struct mmc_data *data)
584{
585 /* Check if next job is already prepared. */
586 if (host->dma_current && host->dma_desc_current)
587 return 0;
588
589 /* No job were prepared thus do it now. */
590 return __mmci_dma_prep_data(host, data, &host->dma_current,
591 &host->dma_desc_current);
592}
593
594static inline int mmci_dma_prep_next(struct mmci_host *host,
595 struct mmc_data *data)
596{
597 struct mmci_host_next *nd = &host->next_data;
598 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
599}
600
Per Forlin58c7ccb2011-07-01 18:55:24 +0200601static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
602{
603 int ret;
604 struct mmc_data *data = host->data;
605
Ulf Hansson653a7612013-01-21 21:29:34 +0100606 ret = mmci_dma_prep_data(host, host->data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200607 if (ret)
608 return ret;
609
610 /* Okay, go for it. */
Russell Kingc8ebae32011-01-11 19:35:53 +0000611 dev_vdbg(mmc_dev(host->mmc),
612 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
613 data->sg_len, data->blksz, data->blocks, data->flags);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200614 dmaengine_submit(host->dma_desc_current);
615 dma_async_issue_pending(host->dma_current);
Russell Kingc8ebae32011-01-11 19:35:53 +0000616
617 datactrl |= MCI_DPSM_DMAENABLE;
618
619 /* Trigger the DMA transfer */
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100620 mmci_write_datactrlreg(host, datactrl);
Russell Kingc8ebae32011-01-11 19:35:53 +0000621
622 /*
623 * Let the MMCI say when the data is ended and it's time
624 * to fire next DMA request. When that happens, MMCI will
625 * call mmci_data_end()
626 */
627 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
628 host->base + MMCIMASK0);
629 return 0;
Russell Kingc8ebae32011-01-11 19:35:53 +0000630}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200631
632static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
633{
634 struct mmci_host_next *next = &host->next_data;
635
Ulf Hansson653a7612013-01-21 21:29:34 +0100636 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
637 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
Per Forlin58c7ccb2011-07-01 18:55:24 +0200638
639 host->dma_desc_current = next->dma_desc;
640 host->dma_current = next->dma_chan;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200641 next->dma_desc = NULL;
642 next->dma_chan = NULL;
643}
644
645static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
646 bool is_first_req)
647{
648 struct mmci_host *host = mmc_priv(mmc);
649 struct mmc_data *data = mrq->data;
650 struct mmci_host_next *nd = &host->next_data;
651
652 if (!data)
653 return;
654
Ulf Hansson653a7612013-01-21 21:29:34 +0100655 BUG_ON(data->host_cookie);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200656
Ulf Hansson653a7612013-01-21 21:29:34 +0100657 if (mmci_validate_data(host, data))
658 return;
659
660 if (!mmci_dma_prep_next(host, data))
661 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200662}
663
664static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
665 int err)
666{
667 struct mmci_host *host = mmc_priv(mmc);
668 struct mmc_data *data = mrq->data;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200669
Ulf Hansson653a7612013-01-21 21:29:34 +0100670 if (!data || !data->host_cookie)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200671 return;
672
Ulf Hansson653a7612013-01-21 21:29:34 +0100673 mmci_dma_unmap(host, data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200674
Ulf Hansson653a7612013-01-21 21:29:34 +0100675 if (err) {
676 struct mmci_host_next *next = &host->next_data;
677 struct dma_chan *chan;
678 if (data->flags & MMC_DATA_READ)
679 chan = host->dma_rx_channel;
680 else
681 chan = host->dma_tx_channel;
682 dmaengine_terminate_all(chan);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200683
Ulf Hansson653a7612013-01-21 21:29:34 +0100684 next->dma_desc = NULL;
685 next->dma_chan = NULL;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200686 }
687}
688
Russell Kingc8ebae32011-01-11 19:35:53 +0000689#else
690/* Blank functions if the DMA engine is not available */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200691static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
692{
693}
Russell Kingc8ebae32011-01-11 19:35:53 +0000694static inline void mmci_dma_setup(struct mmci_host *host)
695{
696}
697
698static inline void mmci_dma_release(struct mmci_host *host)
699{
700}
701
702static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
703{
704}
705
Ulf Hansson653a7612013-01-21 21:29:34 +0100706static inline void mmci_dma_finalize(struct mmci_host *host,
707 struct mmc_data *data)
708{
709}
710
Russell Kingc8ebae32011-01-11 19:35:53 +0000711static inline void mmci_dma_data_error(struct mmci_host *host)
712{
713}
714
715static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
716{
717 return -ENOSYS;
718}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200719
720#define mmci_pre_request NULL
721#define mmci_post_request NULL
722
Russell Kingc8ebae32011-01-11 19:35:53 +0000723#endif
724
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
726{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100727 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728 unsigned int datactrl, timeout, irqmask;
Russell King7b09cda2005-07-01 12:02:59 +0100729 unsigned long long clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730 void __iomem *base;
Russell King3bc87f22006-08-27 13:51:28 +0100731 int blksz_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732
Linus Walleij64de0282010-02-19 01:09:10 +0100733 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
734 data->blksz, data->blocks, data->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735
736 host->data = data;
Rabin Vincent528320d2010-07-21 12:49:49 +0100737 host->size = data->blksz * data->blocks;
Russell King51d43752011-01-27 10:56:52 +0000738 data->bytes_xfered = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739
Russell King7b09cda2005-07-01 12:02:59 +0100740 clks = (unsigned long long)data->timeout_ns * host->cclk;
741 do_div(clks, 1000000000UL);
742
743 timeout = data->timeout_clks + (unsigned int)clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744
745 base = host->base;
746 writel(timeout, base + MMCIDATATIMER);
747 writel(host->size, base + MMCIDATALENGTH);
748
Russell King3bc87f22006-08-27 13:51:28 +0100749 blksz_bits = ffs(data->blksz) - 1;
750 BUG_ON(1 << blksz_bits != data->blksz);
751
Philippe Langlais1784b152011-03-25 08:51:52 +0100752 if (variant->blksz_datactrl16)
753 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
754 else
755 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
Russell Kingc8ebae32011-01-11 19:35:53 +0000756
757 if (data->flags & MMC_DATA_READ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758 datactrl |= MCI_DPSM_DIRECTION;
Russell Kingc8ebae32011-01-11 19:35:53 +0000759
Ulf Hansson7258db72011-12-13 17:05:28 +0100760 /* The ST Micro variants has a special bit to enable SDIO */
761 if (variant->sdio && host->mmc->card)
Ulf Hansson06c1a122012-10-12 14:01:50 +0100762 if (mmc_card_sdio(host->mmc->card)) {
763 /*
764 * The ST Micro variants has a special bit
765 * to enable SDIO.
766 */
767 u32 clk;
768
Ulf Hansson7258db72011-12-13 17:05:28 +0100769 datactrl |= MCI_ST_DPSM_SDIOEN;
770
Ulf Hansson06c1a122012-10-12 14:01:50 +0100771 /*
Ulf Hansson70ac0932012-10-12 14:07:36 +0100772 * The ST Micro variant for SDIO small write transfers
773 * needs to have clock H/W flow control disabled,
774 * otherwise the transfer will not start. The threshold
775 * depends on the rate of MCLK.
Ulf Hansson06c1a122012-10-12 14:01:50 +0100776 */
Ulf Hansson70ac0932012-10-12 14:07:36 +0100777 if (data->flags & MMC_DATA_WRITE &&
778 (host->size < 8 ||
779 (host->size <= 8 && host->mclk > 50000000)))
Ulf Hansson06c1a122012-10-12 14:01:50 +0100780 clk = host->clk_reg & ~variant->clkreg_enable;
781 else
782 clk = host->clk_reg | variant->clkreg_enable;
783
784 mmci_write_clkreg(host, clk);
785 }
786
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100787 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
788 datactrl |= MCI_ST_DPSM_DDRMODE;
789
Russell Kingc8ebae32011-01-11 19:35:53 +0000790 /*
791 * Attempt to use DMA operation mode, if this
792 * should fail, fall back to PIO mode
793 */
794 if (!mmci_dma_start_data(host, datactrl))
795 return;
796
797 /* IRQ mode, map the SG list for CPU reading/writing */
798 mmci_init_sg(host, data);
799
800 if (data->flags & MMC_DATA_READ) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 irqmask = MCI_RXFIFOHALFFULLMASK;
Russell King0425a142006-02-16 16:48:31 +0000802
803 /*
Russell Kingc4d877c2011-01-27 09:50:13 +0000804 * If we have less than the fifo 'half-full' threshold to
805 * transfer, trigger a PIO interrupt as soon as any data
806 * is available.
Russell King0425a142006-02-16 16:48:31 +0000807 */
Russell Kingc4d877c2011-01-27 09:50:13 +0000808 if (host->size < variant->fifohalfsize)
Russell King0425a142006-02-16 16:48:31 +0000809 irqmask |= MCI_RXDATAAVLBLMASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 } else {
811 /*
812 * We don't actually need to include "FIFO empty" here
813 * since its implicit in "FIFO half empty".
814 */
815 irqmask = MCI_TXFIFOHALFEMPTYMASK;
816 }
817
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100818 mmci_write_datactrlreg(host, datactrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100820 mmci_set_mask1(host, irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821}
822
823static void
824mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
825{
826 void __iomem *base = host->base;
827
Linus Walleij64de0282010-02-19 01:09:10 +0100828 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 cmd->opcode, cmd->arg, cmd->flags);
830
831 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
832 writel(0, base + MMCICOMMAND);
833 udelay(1);
834 }
835
836 c |= cmd->opcode | MCI_CPSM_ENABLE;
Russell Kinge9225172006-02-02 12:23:12 +0000837 if (cmd->flags & MMC_RSP_PRESENT) {
838 if (cmd->flags & MMC_RSP_136)
839 c |= MCI_CPSM_LONGRSP;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 c |= MCI_CPSM_RESPONSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 }
842 if (/*interrupt*/0)
843 c |= MCI_CPSM_INTERRUPT;
844
845 host->cmd = cmd;
846
847 writel(cmd->arg, base + MMCIARGUMENT);
848 writel(c, base + MMCICOMMAND);
849}
850
851static void
852mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
853 unsigned int status)
854{
Linus Walleijf20f8f22010-10-19 13:41:24 +0100855 /* First check for errors */
Ulf Hanssonb63038d2011-12-13 16:51:04 +0100856 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
857 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
Linus Walleij8cb28152011-01-24 15:22:13 +0100858 u32 remain, success;
Linus Walleijf20f8f22010-10-19 13:41:24 +0100859
Russell Kingc8ebae32011-01-11 19:35:53 +0000860 /* Terminate the DMA transfer */
Ulf Hansson653a7612013-01-21 21:29:34 +0100861 if (dma_inprogress(host)) {
Russell Kingc8ebae32011-01-11 19:35:53 +0000862 mmci_dma_data_error(host);
Ulf Hansson653a7612013-01-21 21:29:34 +0100863 mmci_dma_unmap(host, data);
864 }
Russell Kingc8ebae32011-01-11 19:35:53 +0000865
Russell Kingc8afc9d2011-02-04 09:19:46 +0000866 /*
867 * Calculate how far we are into the transfer. Note that
868 * the data counter gives the number of bytes transferred
869 * on the MMC bus, not on the host side. On reads, this
870 * can be as much as a FIFO-worth of data ahead. This
871 * matters for FIFO overruns only.
872 */
Linus Walleijf5a106d2011-01-27 17:44:34 +0100873 remain = readl(host->base + MMCIDATACNT);
Linus Walleij8cb28152011-01-24 15:22:13 +0100874 success = data->blksz * data->blocks - remain;
875
Russell Kingc8afc9d2011-02-04 09:19:46 +0000876 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
877 status, success);
Linus Walleij8cb28152011-01-24 15:22:13 +0100878 if (status & MCI_DATACRCFAIL) {
879 /* Last block was not successful */
Russell Kingc8afc9d2011-02-04 09:19:46 +0000880 success -= 1;
Pierre Ossman17b04292007-07-22 22:18:46 +0200881 data->error = -EILSEQ;
Linus Walleij8cb28152011-01-24 15:22:13 +0100882 } else if (status & MCI_DATATIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200883 data->error = -ETIMEDOUT;
Linus Walleij757df742011-06-30 15:10:21 +0100884 } else if (status & MCI_STARTBITERR) {
885 data->error = -ECOMM;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000886 } else if (status & MCI_TXUNDERRUN) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200887 data->error = -EIO;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000888 } else if (status & MCI_RXOVERRUN) {
889 if (success > host->variant->fifosize)
890 success -= host->variant->fifosize;
891 else
892 success = 0;
Linus Walleij8cb28152011-01-24 15:22:13 +0100893 data->error = -EIO;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100894 }
Russell King51d43752011-01-27 10:56:52 +0000895 data->bytes_xfered = round_down(success, data->blksz);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 }
Linus Walleijf20f8f22010-10-19 13:41:24 +0100897
Linus Walleij8cb28152011-01-24 15:22:13 +0100898 if (status & MCI_DATABLOCKEND)
899 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
Linus Walleijf20f8f22010-10-19 13:41:24 +0100900
Russell Kingccff9b52011-01-30 21:03:50 +0000901 if (status & MCI_DATAEND || data->error) {
Russell Kingc8ebae32011-01-11 19:35:53 +0000902 if (dma_inprogress(host))
Ulf Hansson653a7612013-01-21 21:29:34 +0100903 mmci_dma_finalize(host, data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904 mmci_stop_data(host);
905
Linus Walleij8cb28152011-01-24 15:22:13 +0100906 if (!data->error)
907 /* The error clause is handled above, success! */
Russell King51d43752011-01-27 10:56:52 +0000908 data->bytes_xfered = data->blksz * data->blocks;
Linus Walleijf20f8f22010-10-19 13:41:24 +0100909
Ulf Hansson024629c2013-05-13 15:40:56 +0100910 if (!data->stop || host->mrq->sbc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911 mmci_request_end(host, data->mrq);
912 } else {
913 mmci_start_command(host, data->stop, 0);
914 }
915 }
916}
917
918static void
919mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
920 unsigned int status)
921{
922 void __iomem *base = host->base;
Ulf Hansson024629c2013-05-13 15:40:56 +0100923 bool sbc = (cmd == host->mrq->sbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
925 host->cmd = NULL;
926
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 if (status & MCI_CMDTIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200928 cmd->error = -ETIMEDOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200930 cmd->error = -EILSEQ;
Russell King - ARM Linux9047b432011-01-11 16:35:56 +0000931 } else {
932 cmd->resp[0] = readl(base + MMCIRESPONSE0);
933 cmd->resp[1] = readl(base + MMCIRESPONSE1);
934 cmd->resp[2] = readl(base + MMCIRESPONSE2);
935 cmd->resp[3] = readl(base + MMCIRESPONSE3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936 }
937
Ulf Hansson024629c2013-05-13 15:40:56 +0100938 if ((!sbc && !cmd->data) || cmd->error) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100939 if (host->data) {
940 /* Terminate the DMA transfer */
Ulf Hansson653a7612013-01-21 21:29:34 +0100941 if (dma_inprogress(host)) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100942 mmci_dma_data_error(host);
Ulf Hansson653a7612013-01-21 21:29:34 +0100943 mmci_dma_unmap(host, host->data);
944 }
Russell Kinge47c2222007-01-08 16:42:51 +0000945 mmci_stop_data(host);
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100946 }
Ulf Hansson024629c2013-05-13 15:40:56 +0100947 mmci_request_end(host, host->mrq);
948 } else if (sbc) {
949 mmci_start_command(host, host->mrq->cmd, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
951 mmci_start_data(host, cmd->data);
952 }
953}
954
955static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
956{
957 void __iomem *base = host->base;
958 char *ptr = buffer;
959 u32 status;
Linus Walleij26eed9a2008-04-26 23:39:44 +0100960 int host_remain = host->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961
962 do {
Linus Walleij26eed9a2008-04-26 23:39:44 +0100963 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964
965 if (count > remain)
966 count = remain;
967
968 if (count <= 0)
969 break;
970
Ulf Hansson393e5e22011-12-13 17:08:04 +0100971 /*
972 * SDIO especially may want to send something that is
973 * not divisible by 4 (as opposed to card sectors
974 * etc). Therefore make sure to always read the last bytes
975 * while only doing full 32-bit reads towards the FIFO.
976 */
977 if (unlikely(count & 0x3)) {
978 if (count < 4) {
979 unsigned char buf[4];
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100980 ioread32_rep(base + MMCIFIFO, buf, 1);
Ulf Hansson393e5e22011-12-13 17:08:04 +0100981 memcpy(ptr, buf, count);
982 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100983 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +0100984 count &= ~0x3;
985 }
986 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100987 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +0100988 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989
990 ptr += count;
991 remain -= count;
Linus Walleij26eed9a2008-04-26 23:39:44 +0100992 host_remain -= count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993
994 if (remain == 0)
995 break;
996
997 status = readl(base + MMCISTATUS);
998 } while (status & MCI_RXDATAAVLBL);
999
1000 return ptr - buffer;
1001}
1002
1003static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1004{
Rabin Vincent8301bb62010-08-09 12:57:30 +01001005 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 void __iomem *base = host->base;
1007 char *ptr = buffer;
1008
1009 do {
1010 unsigned int count, maxcnt;
1011
Rabin Vincent8301bb62010-08-09 12:57:30 +01001012 maxcnt = status & MCI_TXFIFOEMPTY ?
1013 variant->fifosize : variant->fifohalfsize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014 count = min(remain, maxcnt);
1015
Linus Walleij34177802010-10-19 12:43:58 +01001016 /*
Linus Walleij34177802010-10-19 12:43:58 +01001017 * SDIO especially may want to send something that is
1018 * not divisible by 4 (as opposed to card sectors
1019 * etc), and the FIFO only accept full 32-bit writes.
1020 * So compensate by adding +3 on the count, a single
1021 * byte become a 32bit write, 7 bytes will be two
1022 * 32bit writes etc.
1023 */
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001024 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025
1026 ptr += count;
1027 remain -= count;
1028
1029 if (remain == 0)
1030 break;
1031
1032 status = readl(base + MMCISTATUS);
1033 } while (status & MCI_TXFIFOHALFEMPTY);
1034
1035 return ptr - buffer;
1036}
1037
1038/*
1039 * PIO data transfer IRQ handler.
1040 */
David Howells7d12e782006-10-05 14:55:46 +01001041static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042{
1043 struct mmci_host *host = dev_id;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001044 struct sg_mapping_iter *sg_miter = &host->sg_miter;
Rabin Vincent8301bb62010-08-09 12:57:30 +01001045 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 void __iomem *base = host->base;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001047 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 u32 status;
1049
1050 status = readl(base + MMCISTATUS);
1051
Linus Walleij64de0282010-02-19 01:09:10 +01001052 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001054 local_irq_save(flags);
1055
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 unsigned int remain, len;
1058 char *buffer;
1059
1060 /*
1061 * For write, we only need to test the half-empty flag
1062 * here - if the FIFO is completely empty, then by
1063 * definition it is more than half empty.
1064 *
1065 * For read, check for data available.
1066 */
1067 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1068 break;
1069
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001070 if (!sg_miter_next(sg_miter))
1071 break;
1072
1073 buffer = sg_miter->addr;
1074 remain = sg_miter->length;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075
1076 len = 0;
1077 if (status & MCI_RXACTIVE)
1078 len = mmci_pio_read(host, buffer, remain);
1079 if (status & MCI_TXACTIVE)
1080 len = mmci_pio_write(host, buffer, remain, status);
1081
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001082 sg_miter->consumed = len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 host->size -= len;
1085 remain -= len;
1086
1087 if (remain)
1088 break;
1089
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090 status = readl(base + MMCISTATUS);
1091 } while (1);
1092
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001093 sg_miter_stop(sg_miter);
1094
1095 local_irq_restore(flags);
1096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097 /*
Russell Kingc4d877c2011-01-27 09:50:13 +00001098 * If we have less than the fifo 'half-full' threshold to transfer,
1099 * trigger a PIO interrupt as soon as any data is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 */
Russell Kingc4d877c2011-01-27 09:50:13 +00001101 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
Linus Walleij2686b4b2010-10-19 12:39:48 +01001102 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103
1104 /*
1105 * If we run out of data, disable the data IRQs; this
1106 * prevents a race where the FIFO becomes empty before
1107 * the chip itself has disabled the data path, and
1108 * stops us racing with our data end IRQ.
1109 */
1110 if (host->size == 0) {
Linus Walleij2686b4b2010-10-19 12:39:48 +01001111 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1113 }
1114
1115 return IRQ_HANDLED;
1116}
1117
1118/*
1119 * Handle completion of command and data transfers.
1120 */
David Howells7d12e782006-10-05 14:55:46 +01001121static irqreturn_t mmci_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122{
1123 struct mmci_host *host = dev_id;
1124 u32 status;
1125 int ret = 0;
1126
1127 spin_lock(&host->lock);
1128
1129 do {
1130 struct mmc_command *cmd;
1131 struct mmc_data *data;
1132
1133 status = readl(host->base + MMCISTATUS);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001134
1135 if (host->singleirq) {
1136 if (status & readl(host->base + MMCIMASK1))
1137 mmci_pio_irq(irq, dev_id);
1138
1139 status &= ~MCI_IRQ1MASK;
1140 }
1141
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 status &= readl(host->base + MMCIMASK0);
1143 writel(status, host->base + MMCICLEAR);
1144
Linus Walleij64de0282010-02-19 01:09:10 +01001145 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146
1147 data = host->data;
Ulf Hanssonb63038d2011-12-13 16:51:04 +01001148 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1149 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1150 MCI_DATABLOCKEND) && data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 mmci_data_irq(host, data, status);
1152
1153 cmd = host->cmd;
1154 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1155 mmci_cmd_irq(host, cmd, status);
1156
1157 ret = 1;
1158 } while (status);
1159
1160 spin_unlock(&host->lock);
1161
1162 return IRQ_RETVAL(ret);
1163}
1164
1165static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1166{
1167 struct mmci_host *host = mmc_priv(mmc);
Linus Walleij9e943022008-10-24 21:17:50 +01001168 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001169
1170 WARN_ON(host->mrq != NULL);
1171
Ulf Hansson653a7612013-01-21 21:29:34 +01001172 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1173 if (mrq->cmd->error) {
Pierre Ossman255d01a2007-07-24 20:38:53 +02001174 mmc_request_done(mmc, mrq);
1175 return;
1176 }
1177
Russell King1c3be362011-08-14 09:17:05 +01001178 pm_runtime_get_sync(mmc_dev(mmc));
1179
Linus Walleij9e943022008-10-24 21:17:50 +01001180 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181
1182 host->mrq = mrq;
1183
Per Forlin58c7ccb2011-07-01 18:55:24 +02001184 if (mrq->data)
1185 mmci_get_next_data(host, mrq->data);
1186
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1188 mmci_start_data(host, mrq->data);
1189
Ulf Hansson024629c2013-05-13 15:40:56 +01001190 if (mrq->sbc)
1191 mmci_start_command(host, mrq->sbc, 0);
1192 else
1193 mmci_start_command(host, mrq->cmd, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194
Linus Walleij9e943022008-10-24 21:17:50 +01001195 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196}
1197
1198static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1199{
1200 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001201 struct variant_data *variant = host->variant;
Linus Walleija6a64642009-09-14 12:56:14 +01001202 u32 pwr = 0;
1203 unsigned long flags;
Lee Jonesdb90f912013-05-03 12:52:12 +01001204 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001206 pm_runtime_get_sync(mmc_dev(mmc));
1207
Ulf Hanssonbc521812011-12-13 16:57:55 +01001208 if (host->plat->ios_handler &&
1209 host->plat->ios_handler(mmc_dev(mmc), ios))
1210 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1211
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212 switch (ios->power_mode) {
1213 case MMC_POWER_OFF:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001214 if (!IS_ERR(mmc->supply.vmmc))
1215 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
Lee Jones237fb5e2013-01-31 11:27:52 +00001216
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001217 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
Lee Jones237fb5e2013-01-31 11:27:52 +00001218 regulator_disable(mmc->supply.vqmmc);
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001219 host->vqmmc_enabled = false;
1220 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001221
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 break;
1223 case MMC_POWER_UP:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001224 if (!IS_ERR(mmc->supply.vmmc))
1225 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1226
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001227 /*
1228 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1229 * and instead uses MCI_PWR_ON so apply whatever value is
1230 * configured in the variant data.
1231 */
1232 pwr |= variant->pwrreg_powerup;
1233
1234 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 case MMC_POWER_ON:
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001236 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
Lee Jonesdb90f912013-05-03 12:52:12 +01001237 ret = regulator_enable(mmc->supply.vqmmc);
1238 if (ret < 0)
1239 dev_err(mmc_dev(mmc),
1240 "failed to enable vqmmc regulator\n");
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001241 else
1242 host->vqmmc_enabled = true;
Lee Jonesdb90f912013-05-03 12:52:12 +01001243 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001244
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 pwr |= MCI_PWR_ON;
1246 break;
1247 }
1248
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001249 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1250 /*
1251 * The ST Micro variant has some additional bits
1252 * indicating signal direction for the signals in
1253 * the SD/MMC bus and feedback-clock usage.
1254 */
1255 pwr |= host->plat->sigdir;
1256
1257 if (ios->bus_width == MMC_BUS_WIDTH_4)
1258 pwr &= ~MCI_ST_DATA74DIREN;
1259 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1260 pwr &= (~MCI_ST_DATA74DIREN &
1261 ~MCI_ST_DATA31DIREN &
1262 ~MCI_ST_DATA2DIREN);
1263 }
1264
Linus Walleijcc30d602009-01-04 15:18:54 +01001265 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
Linus Walleijf17a1f02009-08-04 01:01:02 +01001266 if (host->hw_designer != AMBA_VENDOR_ST)
Linus Walleijcc30d602009-01-04 15:18:54 +01001267 pwr |= MCI_ROD;
1268 else {
1269 /*
1270 * The ST Micro variant use the ROD bit for something
1271 * else and only has OD (Open Drain).
1272 */
1273 pwr |= MCI_OD;
1274 }
1275 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276
Ulf Hanssonf4670da2013-01-09 17:19:54 +01001277 /*
1278 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1279 * gating the clock, the MCI_PWR_ON bit is cleared.
1280 */
1281 if (!ios->clock && variant->pwrreg_clkgate)
1282 pwr &= ~MCI_PWR_ON;
1283
Linus Walleija6a64642009-09-14 12:56:14 +01001284 spin_lock_irqsave(&host->lock, flags);
1285
1286 mmci_set_clkreg(host, ios->clock);
Ulf Hansson7437cfa2012-01-18 09:17:27 +01001287 mmci_write_pwrreg(host, pwr);
Ulf Hanssonf829c042013-09-04 09:01:15 +01001288 mmci_reg_delay(host);
Linus Walleija6a64642009-09-14 12:56:14 +01001289
1290 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001291
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001292 pm_runtime_mark_last_busy(mmc_dev(mmc));
1293 pm_runtime_put_autosuspend(mmc_dev(mmc));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294}
1295
Russell King89001442009-07-09 15:16:07 +01001296static int mmci_get_ro(struct mmc_host *mmc)
1297{
1298 struct mmci_host *host = mmc_priv(mmc);
1299
1300 if (host->gpio_wp == -ENOSYS)
1301 return -ENOSYS;
1302
Linus Walleij18a063012010-09-12 12:56:44 +01001303 return gpio_get_value_cansleep(host->gpio_wp);
Russell King89001442009-07-09 15:16:07 +01001304}
1305
1306static int mmci_get_cd(struct mmc_host *mmc)
1307{
1308 struct mmci_host *host = mmc_priv(mmc);
Rabin Vincent29719442010-08-09 12:54:43 +01001309 struct mmci_platform_data *plat = host->plat;
Russell King89001442009-07-09 15:16:07 +01001310 unsigned int status;
1311
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001312 if (host->gpio_cd == -ENOSYS) {
1313 if (!plat->status)
1314 return 1; /* Assume always present */
1315
Rabin Vincent29719442010-08-09 12:54:43 +01001316 status = plat->status(mmc_dev(host->mmc));
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001317 } else
Linus Walleij18a063012010-09-12 12:56:44 +01001318 status = !!gpio_get_value_cansleep(host->gpio_cd)
1319 ^ plat->cd_invert;
Russell King89001442009-07-09 15:16:07 +01001320
Russell King74bc8092010-07-29 15:58:59 +01001321 /*
1322 * Use positive logic throughout - status is zero for no card,
1323 * non-zero for card inserted.
1324 */
1325 return status;
Russell King89001442009-07-09 15:16:07 +01001326}
1327
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001328static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1329{
1330 int ret = 0;
1331
1332 if (!IS_ERR(mmc->supply.vqmmc)) {
1333
1334 pm_runtime_get_sync(mmc_dev(mmc));
1335
1336 switch (ios->signal_voltage) {
1337 case MMC_SIGNAL_VOLTAGE_330:
1338 ret = regulator_set_voltage(mmc->supply.vqmmc,
1339 2700000, 3600000);
1340 break;
1341 case MMC_SIGNAL_VOLTAGE_180:
1342 ret = regulator_set_voltage(mmc->supply.vqmmc,
1343 1700000, 1950000);
1344 break;
1345 case MMC_SIGNAL_VOLTAGE_120:
1346 ret = regulator_set_voltage(mmc->supply.vqmmc,
1347 1100000, 1300000);
1348 break;
1349 }
1350
1351 if (ret)
1352 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1353
1354 pm_runtime_mark_last_busy(mmc_dev(mmc));
1355 pm_runtime_put_autosuspend(mmc_dev(mmc));
1356 }
1357
1358 return ret;
1359}
1360
Rabin Vincent148b8b32010-08-09 12:55:48 +01001361static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1362{
1363 struct mmci_host *host = dev_id;
1364
1365 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1366
1367 return IRQ_HANDLED;
1368}
1369
Ulf Hansson01259622013-05-15 20:53:22 +01001370static struct mmc_host_ops mmci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371 .request = mmci_request,
Per Forlin58c7ccb2011-07-01 18:55:24 +02001372 .pre_req = mmci_pre_request,
1373 .post_req = mmci_post_request,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 .set_ios = mmci_set_ios,
Russell King89001442009-07-09 15:16:07 +01001375 .get_ro = mmci_get_ro,
1376 .get_cd = mmci_get_cd,
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001377 .start_signal_voltage_switch = mmci_sig_volt_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378};
1379
Lee Jones000bc9d2012-04-16 10:18:43 +01001380#ifdef CONFIG_OF
1381static void mmci_dt_populate_generic_pdata(struct device_node *np,
1382 struct mmci_platform_data *pdata)
1383{
1384 int bus_width = 0;
1385
Lee Jones9a597012012-04-12 16:51:13 +01001386 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
Lee Jones9a597012012-04-12 16:51:13 +01001387 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
Lee Jones000bc9d2012-04-16 10:18:43 +01001388
1389 if (of_get_property(np, "cd-inverted", NULL))
1390 pdata->cd_invert = true;
1391 else
1392 pdata->cd_invert = false;
1393
1394 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1395 if (!pdata->f_max)
1396 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1397
1398 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1399 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1400 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1401 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1402
1403 of_property_read_u32(np, "bus-width", &bus_width);
1404 switch (bus_width) {
1405 case 0 :
1406 /* No bus-width supplied. */
1407 break;
1408 case 4 :
1409 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1410 break;
1411 case 8 :
1412 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1413 break;
1414 default :
1415 pr_warn("%s: Unsupported bus width\n", np->full_name);
1416 }
1417}
Lee Jonesc0a120a2012-05-08 13:59:38 +01001418#else
1419static void mmci_dt_populate_generic_pdata(struct device_node *np,
1420 struct mmci_platform_data *pdata)
1421{
1422 return;
1423}
Lee Jones000bc9d2012-04-16 10:18:43 +01001424#endif
1425
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001426static int mmci_probe(struct amba_device *dev,
Russell Kingaa25afa2011-02-19 15:55:00 +00001427 const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428{
Linus Walleij6ef297f2009-09-22 14:29:36 +01001429 struct mmci_platform_data *plat = dev->dev.platform_data;
Lee Jones000bc9d2012-04-16 10:18:43 +01001430 struct device_node *np = dev->dev.of_node;
Rabin Vincent4956e102010-07-21 12:54:40 +01001431 struct variant_data *variant = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 struct mmci_host *host;
1433 struct mmc_host *mmc;
1434 int ret;
1435
Lee Jones000bc9d2012-04-16 10:18:43 +01001436 /* Must have platform data or Device Tree. */
1437 if (!plat && !np) {
1438 dev_err(&dev->dev, "No plat data or DT found\n");
1439 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 }
1441
Lee Jonesb9b52912012-06-12 10:49:51 +01001442 if (!plat) {
1443 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1444 if (!plat)
1445 return -ENOMEM;
1446 }
1447
Lee Jones000bc9d2012-04-16 10:18:43 +01001448 if (np)
1449 mmci_dt_populate_generic_pdata(np, plat);
1450
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451 ret = amba_request_regions(dev, DRIVER_NAME);
1452 if (ret)
1453 goto out;
1454
1455 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1456 if (!mmc) {
1457 ret = -ENOMEM;
1458 goto rel_regions;
1459 }
1460
1461 host = mmc_priv(mmc);
Rabin Vincent4ea580f2009-04-17 08:44:19 +05301462 host->mmc = mmc;
Russell King012b7d32009-07-09 15:13:56 +01001463
Russell King89001442009-07-09 15:16:07 +01001464 host->gpio_wp = -ENOSYS;
1465 host->gpio_cd = -ENOSYS;
Rabin Vincent148b8b32010-08-09 12:55:48 +01001466 host->gpio_cd_irq = -1;
Russell King89001442009-07-09 15:16:07 +01001467
Russell King012b7d32009-07-09 15:13:56 +01001468 host->hw_designer = amba_manf(dev);
1469 host->hw_revision = amba_rev(dev);
Linus Walleij64de0282010-02-19 01:09:10 +01001470 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1471 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
Russell King012b7d32009-07-09 15:13:56 +01001472
Ulf Hansson665ba562013-05-13 15:39:17 +01001473 host->clk = devm_clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001474 if (IS_ERR(host->clk)) {
1475 ret = PTR_ERR(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 goto host_free;
1477 }
1478
Julia Lawallac940932012-08-26 16:00:59 +00001479 ret = clk_prepare_enable(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480 if (ret)
Ulf Hansson665ba562013-05-13 15:39:17 +01001481 goto host_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482
1483 host->plat = plat;
Rabin Vincent4956e102010-07-21 12:54:40 +01001484 host->variant = variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001485 host->mclk = clk_get_rate(host->clk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001486 /*
1487 * According to the spec, mclk is max 100 MHz,
1488 * so we try to adjust the clock down to this,
1489 * (if possible).
1490 */
1491 if (host->mclk > 100000000) {
1492 ret = clk_set_rate(host->clk, 100000000);
1493 if (ret < 0)
1494 goto clk_disable;
1495 host->mclk = clk_get_rate(host->clk);
Linus Walleij64de0282010-02-19 01:09:10 +01001496 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1497 host->mclk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001498 }
Russell Kingc8ebae32011-01-11 19:35:53 +00001499 host->phybase = dev->res.start;
Linus Walleijdc890c22009-06-07 23:27:31 +01001500 host->base = ioremap(dev->res.start, resource_size(&dev->res));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501 if (!host->base) {
1502 ret = -ENOMEM;
1503 goto clk_disable;
1504 }
1505
Ulf Hansson01259622013-05-15 20:53:22 +01001506 if (variant->busy_detect) {
1507 mmci_ops.card_busy = mmci_card_busy;
1508 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1509 }
1510
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 mmc->ops = &mmci_ops;
Linus Walleij7f294e42011-07-08 09:57:15 +01001512 /*
1513 * The ARM and ST versions of the block have slightly different
1514 * clock divider equations which means that the minimum divider
1515 * differs too.
1516 */
1517 if (variant->st_clkdiv)
1518 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1519 else
1520 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
Linus Walleij808d97c2010-04-08 07:39:38 +01001521 /*
1522 * If the platform data supplies a maximum operating
1523 * frequency, this takes precedence. Else, we fall back
1524 * to using the module parameter, which has a (low)
1525 * default value in case it is not specified. Either
1526 * value must not exceed the clock rate into the block,
1527 * of course.
1528 */
1529 if (plat->f_max)
1530 mmc->f_max = min(host->mclk, plat->f_max);
1531 else
1532 mmc->f_max = min(host->mclk, fmax);
Linus Walleij64de0282010-02-19 01:09:10 +01001533 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1534
Ulf Hansson599c1d52013-01-07 16:22:50 +01001535 /* Get regulators and the supported OCR mask */
1536 mmc_regulator_get_supply(mmc);
1537 if (!mmc->ocr_avail)
Linus Walleij34e84f32009-09-22 14:41:40 +01001538 mmc->ocr_avail = plat->ocr_mask;
Ulf Hansson599c1d52013-01-07 16:22:50 +01001539 else if (plat->ocr_mask)
1540 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1541
Linus Walleij9e6c82c2009-09-14 12:57:11 +01001542 mmc->caps = plat->capabilities;
Per Forlin5a092622011-11-14 12:02:28 +01001543 mmc->caps2 = plat->capabilities2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544
Ulf Hansson70be2082013-01-07 15:35:06 +01001545 /* We support these PM capabilities. */
1546 mmc->pm_caps = MMC_PM_KEEP_POWER;
1547
Linus Torvalds1da177e2005-04-16 15:20:36 -07001548 /*
1549 * We can do SGIO
1550 */
Martin K. Petersena36274e2010-09-10 01:33:59 -04001551 mmc->max_segs = NR_SG;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552
1553 /*
Rabin Vincent08458ef2010-07-21 12:55:59 +01001554 * Since only a certain number of bits are valid in the data length
1555 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1556 * single request.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 */
Rabin Vincent08458ef2010-07-21 12:55:59 +01001558 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559
1560 /*
1561 * Set the maximum segment size. Since we aren't doing DMA
1562 * (yet) we are only limited by the data length register.
1563 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001564 mmc->max_seg_size = mmc->max_req_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001566 /*
1567 * Block size can be up to 2048 bytes, but must be a power of two.
1568 */
Will Deacon8f7f6b72012-02-24 11:25:21 +00001569 mmc->max_blk_size = 1 << 11;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001570
Pierre Ossman55db8902006-11-21 17:55:45 +01001571 /*
Will Deacon8f7f6b72012-02-24 11:25:21 +00001572 * Limit the number of blocks transferred so that we don't overflow
1573 * the maximum request size.
Pierre Ossman55db8902006-11-21 17:55:45 +01001574 */
Will Deacon8f7f6b72012-02-24 11:25:21 +00001575 mmc->max_blk_count = mmc->max_req_size >> 11;
Pierre Ossman55db8902006-11-21 17:55:45 +01001576
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577 spin_lock_init(&host->lock);
1578
1579 writel(0, host->base + MMCIMASK0);
1580 writel(0, host->base + MMCIMASK1);
1581 writel(0xfff, host->base + MMCICLEAR);
1582
Roland Stigge2805b9a2012-06-17 21:14:27 +01001583 if (plat->gpio_cd == -EPROBE_DEFER) {
1584 ret = -EPROBE_DEFER;
1585 goto err_gpio_cd;
1586 }
Russell King89001442009-07-09 15:16:07 +01001587 if (gpio_is_valid(plat->gpio_cd)) {
1588 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1589 if (ret == 0)
1590 ret = gpio_direction_input(plat->gpio_cd);
1591 if (ret == 0)
1592 host->gpio_cd = plat->gpio_cd;
1593 else if (ret != -ENOSYS)
1594 goto err_gpio_cd;
Rabin Vincent148b8b32010-08-09 12:55:48 +01001595
Linus Walleij17ee0832011-05-05 17:23:10 +01001596 /*
1597 * A gpio pin that will detect cards when inserted and removed
1598 * will most likely want to trigger on the edges if it is
1599 * 0 when ejected and 1 when inserted (or mutatis mutandis
1600 * for the inverted case) so we request triggers on both
1601 * edges.
1602 */
Rabin Vincent148b8b32010-08-09 12:55:48 +01001603 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
Linus Walleij17ee0832011-05-05 17:23:10 +01001604 mmci_cd_irq,
1605 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1606 DRIVER_NAME " (cd)", host);
Rabin Vincent148b8b32010-08-09 12:55:48 +01001607 if (ret >= 0)
1608 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
Russell King89001442009-07-09 15:16:07 +01001609 }
Roland Stigge2805b9a2012-06-17 21:14:27 +01001610 if (plat->gpio_wp == -EPROBE_DEFER) {
1611 ret = -EPROBE_DEFER;
1612 goto err_gpio_wp;
1613 }
Russell King89001442009-07-09 15:16:07 +01001614 if (gpio_is_valid(plat->gpio_wp)) {
1615 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1616 if (ret == 0)
1617 ret = gpio_direction_input(plat->gpio_wp);
1618 if (ret == 0)
1619 host->gpio_wp = plat->gpio_wp;
1620 else if (ret != -ENOSYS)
1621 goto err_gpio_wp;
1622 }
1623
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001624 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1625 && host->gpio_cd_irq < 0)
Rabin Vincent148b8b32010-08-09 12:55:48 +01001626 mmc->caps |= MMC_CAP_NEEDS_POLL;
1627
Thomas Gleixnerdace1452006-07-01 19:29:38 -07001628 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629 if (ret)
1630 goto unmap;
1631
Russell Kingdfb851852012-05-03 11:33:15 +01001632 if (!dev->irq[1])
Linus Walleij2686b4b2010-10-19 12:39:48 +01001633 host->singleirq = true;
1634 else {
1635 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1636 DRIVER_NAME " (pio)", host);
1637 if (ret)
1638 goto irq0_free;
1639 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640
Linus Walleij8cb28152011-01-24 15:22:13 +01001641 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642
1643 amba_set_drvdata(dev, mmc);
1644
Russell Kingc8ebae32011-01-11 19:35:53 +00001645 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1646 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1647 amba_rev(dev), (unsigned long long)dev->res.start,
1648 dev->irq[0], dev->irq[1]);
1649
1650 mmci_dma_setup(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001652 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1653 pm_runtime_use_autosuspend(&dev->dev);
Russell King1c3be362011-08-14 09:17:05 +01001654 pm_runtime_put(&dev->dev);
1655
Russell King8c11a942010-12-28 19:40:40 +00001656 mmc_add_host(mmc);
1657
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658 return 0;
1659
1660 irq0_free:
1661 free_irq(dev->irq[0], host);
1662 unmap:
Russell King89001442009-07-09 15:16:07 +01001663 if (host->gpio_wp != -ENOSYS)
1664 gpio_free(host->gpio_wp);
1665 err_gpio_wp:
Rabin Vincent148b8b32010-08-09 12:55:48 +01001666 if (host->gpio_cd_irq >= 0)
1667 free_irq(host->gpio_cd_irq, host);
Russell King89001442009-07-09 15:16:07 +01001668 if (host->gpio_cd != -ENOSYS)
1669 gpio_free(host->gpio_cd);
1670 err_gpio_cd:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671 iounmap(host->base);
1672 clk_disable:
Julia Lawallac940932012-08-26 16:00:59 +00001673 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674 host_free:
1675 mmc_free_host(mmc);
1676 rel_regions:
1677 amba_release_regions(dev);
1678 out:
1679 return ret;
1680}
1681
Bill Pemberton6e0ee712012-11-19 13:26:03 -05001682static int mmci_remove(struct amba_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683{
1684 struct mmc_host *mmc = amba_get_drvdata(dev);
1685
1686 amba_set_drvdata(dev, NULL);
1687
1688 if (mmc) {
1689 struct mmci_host *host = mmc_priv(mmc);
1690
Russell King1c3be362011-08-14 09:17:05 +01001691 /*
1692 * Undo pm_runtime_put() in probe. We use the _sync
1693 * version here so that we can access the primecell.
1694 */
1695 pm_runtime_get_sync(&dev->dev);
1696
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697 mmc_remove_host(mmc);
1698
1699 writel(0, host->base + MMCIMASK0);
1700 writel(0, host->base + MMCIMASK1);
1701
1702 writel(0, host->base + MMCICOMMAND);
1703 writel(0, host->base + MMCIDATACTRL);
1704
Russell Kingc8ebae32011-01-11 19:35:53 +00001705 mmci_dma_release(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706 free_irq(dev->irq[0], host);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001707 if (!host->singleirq)
1708 free_irq(dev->irq[1], host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709
Russell King89001442009-07-09 15:16:07 +01001710 if (host->gpio_wp != -ENOSYS)
1711 gpio_free(host->gpio_wp);
Rabin Vincent148b8b32010-08-09 12:55:48 +01001712 if (host->gpio_cd_irq >= 0)
1713 free_irq(host->gpio_cd_irq, host);
Russell King89001442009-07-09 15:16:07 +01001714 if (host->gpio_cd != -ENOSYS)
1715 gpio_free(host->gpio_cd);
1716
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717 iounmap(host->base);
Julia Lawallac940932012-08-26 16:00:59 +00001718 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001719
1720 mmc_free_host(mmc);
1721
1722 amba_release_regions(dev);
1723 }
1724
1725 return 0;
1726}
1727
Ulf Hansson48fa7002011-12-13 16:59:34 +01001728#ifdef CONFIG_SUSPEND
1729static int mmci_suspend(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730{
Ulf Hansson48fa7002011-12-13 16:59:34 +01001731 struct amba_device *adev = to_amba_device(dev);
1732 struct mmc_host *mmc = amba_get_drvdata(adev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733 int ret = 0;
1734
1735 if (mmc) {
1736 struct mmci_host *host = mmc_priv(mmc);
1737
Matt Fleming1a13f8f2010-05-26 14:42:08 -07001738 ret = mmc_suspend_host(mmc);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001739 if (ret == 0) {
1740 pm_runtime_get_sync(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741 writel(0, host->base + MMCIMASK0);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001742 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743 }
1744
1745 return ret;
1746}
1747
Ulf Hansson48fa7002011-12-13 16:59:34 +01001748static int mmci_resume(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749{
Ulf Hansson48fa7002011-12-13 16:59:34 +01001750 struct amba_device *adev = to_amba_device(dev);
1751 struct mmc_host *mmc = amba_get_drvdata(adev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001752 int ret = 0;
1753
1754 if (mmc) {
1755 struct mmci_host *host = mmc_priv(mmc);
1756
1757 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001758 pm_runtime_put(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759
1760 ret = mmc_resume_host(mmc);
1761 }
1762
1763 return ret;
1764}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765#endif
1766
Ulf Hansson82592932013-01-09 11:15:26 +01001767#ifdef CONFIG_PM_RUNTIME
Ulf Hansson1ff44432013-09-04 09:05:17 +01001768static void mmci_save(struct mmci_host *host)
1769{
1770 unsigned long flags;
1771
1772 if (host->variant->pwrreg_nopower) {
1773 spin_lock_irqsave(&host->lock, flags);
1774
1775 writel(0, host->base + MMCIMASK0);
1776 writel(0, host->base + MMCIDATACTRL);
1777 writel(0, host->base + MMCIPOWER);
1778 writel(0, host->base + MMCICLOCK);
1779 mmci_reg_delay(host);
1780
1781 spin_unlock_irqrestore(&host->lock, flags);
1782 }
1783
1784}
1785
1786static void mmci_restore(struct mmci_host *host)
1787{
1788 unsigned long flags;
1789
1790 if (host->variant->pwrreg_nopower) {
1791 spin_lock_irqsave(&host->lock, flags);
1792
1793 writel(host->clk_reg, host->base + MMCICLOCK);
1794 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1795 writel(host->pwr_reg, host->base + MMCIPOWER);
1796 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1797 mmci_reg_delay(host);
1798
1799 spin_unlock_irqrestore(&host->lock, flags);
1800 }
1801}
1802
Ulf Hansson82592932013-01-09 11:15:26 +01001803static int mmci_runtime_suspend(struct device *dev)
1804{
1805 struct amba_device *adev = to_amba_device(dev);
1806 struct mmc_host *mmc = amba_get_drvdata(adev);
1807
1808 if (mmc) {
1809 struct mmci_host *host = mmc_priv(mmc);
Ulf Hanssone36bd9c62013-09-04 09:00:37 +01001810 pinctrl_pm_select_sleep_state(dev);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001811 mmci_save(host);
Ulf Hansson82592932013-01-09 11:15:26 +01001812 clk_disable_unprepare(host->clk);
1813 }
1814
1815 return 0;
1816}
1817
1818static int mmci_runtime_resume(struct device *dev)
1819{
1820 struct amba_device *adev = to_amba_device(dev);
1821 struct mmc_host *mmc = amba_get_drvdata(adev);
1822
1823 if (mmc) {
1824 struct mmci_host *host = mmc_priv(mmc);
1825 clk_prepare_enable(host->clk);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001826 mmci_restore(host);
Ulf Hanssone36bd9c62013-09-04 09:00:37 +01001827 pinctrl_pm_select_default_state(dev);
Ulf Hansson82592932013-01-09 11:15:26 +01001828 }
1829
1830 return 0;
1831}
1832#endif
1833
Ulf Hansson48fa7002011-12-13 16:59:34 +01001834static const struct dev_pm_ops mmci_dev_pm_ops = {
1835 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
Ulf Hansson82592932013-01-09 11:15:26 +01001836 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
Ulf Hansson48fa7002011-12-13 16:59:34 +01001837};
1838
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839static struct amba_id mmci_ids[] = {
1840 {
1841 .id = 0x00041180,
Pawel Moll768fbc12011-03-11 17:18:07 +00001842 .mask = 0xff0fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001843 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001844 },
1845 {
Pawel Moll768fbc12011-03-11 17:18:07 +00001846 .id = 0x01041180,
1847 .mask = 0xff0fffff,
1848 .data = &variant_arm_extended_fifo,
1849 },
1850 {
Pawel Moll3a372982013-01-24 14:12:45 +01001851 .id = 0x02041180,
1852 .mask = 0xff0fffff,
1853 .data = &variant_arm_extended_fifo_hwfc,
1854 },
1855 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856 .id = 0x00041181,
1857 .mask = 0x000fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001858 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859 },
Linus Walleijcc30d602009-01-04 15:18:54 +01001860 /* ST Micro variants */
1861 {
1862 .id = 0x00180180,
1863 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001864 .data = &variant_u300,
Linus Walleijcc30d602009-01-04 15:18:54 +01001865 },
1866 {
Linus Walleij34fd4212012-04-10 17:43:59 +01001867 .id = 0x10180180,
1868 .mask = 0xf0ffffff,
1869 .data = &variant_nomadik,
1870 },
1871 {
Linus Walleijcc30d602009-01-04 15:18:54 +01001872 .id = 0x00280180,
1873 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001874 .data = &variant_u300,
1875 },
1876 {
1877 .id = 0x00480180,
Philippe Langlais1784b152011-03-25 08:51:52 +01001878 .mask = 0xf0ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001879 .data = &variant_ux500,
Linus Walleijcc30d602009-01-04 15:18:54 +01001880 },
Philippe Langlais1784b152011-03-25 08:51:52 +01001881 {
1882 .id = 0x10480180,
1883 .mask = 0xf0ffffff,
1884 .data = &variant_ux500v2,
1885 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 { 0, 0 },
1887};
1888
Dave Martin9f998352011-10-05 15:15:21 +01001889MODULE_DEVICE_TABLE(amba, mmci_ids);
1890
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891static struct amba_driver mmci_driver = {
1892 .drv = {
1893 .name = DRIVER_NAME,
Ulf Hansson48fa7002011-12-13 16:59:34 +01001894 .pm = &mmci_dev_pm_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 },
1896 .probe = mmci_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -05001897 .remove = mmci_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 .id_table = mmci_ids,
1899};
1900
viresh kumar9e5ed092012-03-15 10:40:38 +01001901module_amba_driver(mmci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902
Linus Torvalds1da177e2005-04-16 15:20:36 -07001903module_param(fmax, uint, 0444);
1904
1905MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1906MODULE_LICENSE("GPL");