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Mattias Nilssonfea799e2011-08-12 10:28:02 +02001/*
2 * Copyright (C) ST Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * STE Ux500 PRCMU API
7 */
8#ifndef __MACH_PRCMU_H
9#define __MACH_PRCMU_H
10
11#include <linux/interrupt.h>
12#include <linux/notifier.h>
Mattias Nilsson05089012012-01-13 16:20:20 +010013#include <linux/err.h>
Mattias Nilssonfea799e2011-08-12 10:28:02 +020014
15/* PRCMU Wakeup defines */
16enum prcmu_wakeup_index {
17 PRCMU_WAKEUP_INDEX_RTC,
18 PRCMU_WAKEUP_INDEX_RTT0,
19 PRCMU_WAKEUP_INDEX_RTT1,
20 PRCMU_WAKEUP_INDEX_HSI0,
21 PRCMU_WAKEUP_INDEX_HSI1,
22 PRCMU_WAKEUP_INDEX_USB,
23 PRCMU_WAKEUP_INDEX_ABB,
24 PRCMU_WAKEUP_INDEX_ABB_FIFO,
25 PRCMU_WAKEUP_INDEX_ARM,
26 PRCMU_WAKEUP_INDEX_CD_IRQ,
27 NUM_PRCMU_WAKEUP_INDICES
28};
29#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
30
31/* EPOD (power domain) IDs */
32
33/*
34 * DB8500 EPODs
35 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
36 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
37 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
38 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
39 * - EPOD_ID_SGA: power domain for SGA
40 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
41 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
42 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
43 * - NUM_EPOD_ID: number of power domains
44 *
45 * TODO: These should be prefixed.
46 */
47#define EPOD_ID_SVAMMDSP 0
48#define EPOD_ID_SVAPIPE 1
49#define EPOD_ID_SIAMMDSP 2
50#define EPOD_ID_SIAPIPE 3
51#define EPOD_ID_SGA 4
52#define EPOD_ID_B2R2_MCDE 5
53#define EPOD_ID_ESRAM12 6
54#define EPOD_ID_ESRAM34 7
55#define NUM_EPOD_ID 8
56
57/*
Mattias Nilssonfea799e2011-08-12 10:28:02 +020058 * state definition for EPOD (power domain)
59 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
60 * - EPOD_STATE_OFF: The EPOD is switched off
61 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
62 * retention
63 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
64 * - EPOD_STATE_ON: Same as above, but with clock enabled
65 */
66#define EPOD_STATE_NO_CHANGE 0x00
67#define EPOD_STATE_OFF 0x01
68#define EPOD_STATE_RAMRET 0x02
69#define EPOD_STATE_ON_CLK_OFF 0x03
70#define EPOD_STATE_ON 0x04
71
72/*
73 * CLKOUT sources
74 */
75#define PRCMU_CLKSRC_CLK38M 0x00
76#define PRCMU_CLKSRC_ACLK 0x01
77#define PRCMU_CLKSRC_SYSCLK 0x02
78#define PRCMU_CLKSRC_LCDCLK 0x03
79#define PRCMU_CLKSRC_SDMMCCLK 0x04
80#define PRCMU_CLKSRC_TVCLK 0x05
81#define PRCMU_CLKSRC_TIMCLK 0x06
82#define PRCMU_CLKSRC_CLK009 0x07
83/* These are only valid for CLKOUT1: */
84#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
85#define PRCMU_CLKSRC_I2CCLK 0x41
86#define PRCMU_CLKSRC_MSP02CLK 0x42
87#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
88#define PRCMU_CLKSRC_HSIRXCLK 0x44
89#define PRCMU_CLKSRC_HSITXCLK 0x45
90#define PRCMU_CLKSRC_ARMCLKFIX 0x46
91#define PRCMU_CLKSRC_HDMICLK 0x47
92
93/*
94 * Clock identifiers.
95 */
96enum prcmu_clock {
97 PRCMU_SGACLK,
98 PRCMU_UARTCLK,
99 PRCMU_MSP02CLK,
100 PRCMU_MSP1CLK,
101 PRCMU_I2CCLK,
102 PRCMU_SDMMCCLK,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100103 PRCMU_SPARE1CLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200104 PRCMU_SLIMCLK,
105 PRCMU_PER1CLK,
106 PRCMU_PER2CLK,
107 PRCMU_PER3CLK,
108 PRCMU_PER5CLK,
109 PRCMU_PER6CLK,
110 PRCMU_PER7CLK,
111 PRCMU_LCDCLK,
112 PRCMU_BMLCLK,
113 PRCMU_HSITXCLK,
114 PRCMU_HSIRXCLK,
115 PRCMU_HDMICLK,
116 PRCMU_APEATCLK,
117 PRCMU_APETRACECLK,
118 PRCMU_MCDECLK,
119 PRCMU_IPI2CCLK,
120 PRCMU_DSIALTCLK,
121 PRCMU_DMACLK,
122 PRCMU_B2R2CLK,
123 PRCMU_TVCLK,
124 PRCMU_SSPCLK,
125 PRCMU_RNGCLK,
126 PRCMU_UICCCLK,
127 PRCMU_PWMCLK,
128 PRCMU_IRDACLK,
129 PRCMU_IRRCCLK,
130 PRCMU_SIACLK,
131 PRCMU_SVACLK,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100132 PRCMU_ACLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200133 PRCMU_NUM_REG_CLOCKS,
134 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100135 PRCMU_CDCLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200136 PRCMU_TIMCLK,
137 PRCMU_PLLSOC0,
138 PRCMU_PLLSOC1,
Michel Jaouen20aee5b2012-08-31 14:21:30 +0200139 PRCMU_ARMSS,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200140 PRCMU_PLLDDR,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100141 PRCMU_PLLDSI,
142 PRCMU_DSI0CLK,
143 PRCMU_DSI1CLK,
144 PRCMU_DSI0ESCCLK,
145 PRCMU_DSI1ESCCLK,
146 PRCMU_DSI2ESCCLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200147};
148
149/**
150 * enum ape_opp - APE OPP states definition
151 * @APE_OPP_INIT:
152 * @APE_NO_CHANGE: The APE operating point is unchanged
153 * @APE_100_OPP: The new APE operating point is ape100opp
154 * @APE_50_OPP: 50%
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100155 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200156 */
157enum ape_opp {
158 APE_OPP_INIT = 0x00,
159 APE_NO_CHANGE = 0x01,
160 APE_100_OPP = 0x02,
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100161 APE_50_OPP = 0x03,
162 APE_50_PARTLY_25_OPP = 0xFF,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200163};
164
165/**
166 * enum arm_opp - ARM OPP states definition
167 * @ARM_OPP_INIT:
168 * @ARM_NO_CHANGE: The ARM operating point is unchanged
169 * @ARM_100_OPP: The new ARM operating point is arm100opp
170 * @ARM_50_OPP: The new ARM operating point is arm50opp
171 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
172 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
173 * @ARM_EXTCLK: The new ARM operating point is armExtClk
174 */
175enum arm_opp {
176 ARM_OPP_INIT = 0x00,
177 ARM_NO_CHANGE = 0x01,
178 ARM_100_OPP = 0x02,
179 ARM_50_OPP = 0x03,
180 ARM_MAX_OPP = 0x04,
181 ARM_MAX_FREQ100OPP = 0x05,
182 ARM_EXTCLK = 0x07
183};
184
185/**
186 * enum ddr_opp - DDR OPP states definition
187 * @DDR_100_OPP: The new DDR operating point is ddr100opp
188 * @DDR_50_OPP: The new DDR operating point is ddr50opp
189 * @DDR_25_OPP: The new DDR operating point is ddr25opp
190 */
191enum ddr_opp {
192 DDR_100_OPP = 0x00,
193 DDR_50_OPP = 0x01,
194 DDR_25_OPP = 0x02,
195};
196
197/*
198 * Definitions for controlling ESRAM0 in deep sleep.
199 */
200#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
201#define ESRAM0_DEEP_SLEEP_STATE_RET 2
202
203/**
204 * enum ddr_pwrst - DDR power states definition
205 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
206 * @DDR_PWR_STATE_ON:
207 * @DDR_PWR_STATE_OFFLOWLAT:
208 * @DDR_PWR_STATE_OFFHIGHLAT:
209 */
210enum ddr_pwrst {
211 DDR_PWR_STATE_UNCHANGED = 0x00,
212 DDR_PWR_STATE_ON = 0x01,
213 DDR_PWR_STATE_OFFLOWLAT = 0x02,
214 DDR_PWR_STATE_OFFHIGHLAT = 0x03
215};
216
217#include <linux/mfd/db8500-prcmu.h>
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200218
Linus Walleijdece3702012-04-13 14:01:39 +0200219#if defined(CONFIG_UX500_SOC_DB8500)
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200220
Mattias Nilsson05089012012-01-13 16:20:20 +0100221#include <mach/id.h>
222
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200223static inline void __init prcmu_early_init(void)
224{
Linus Walleijdece3702012-04-13 14:01:39 +0200225 return db8500_prcmu_early_init();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200226}
227
228static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
229 bool keep_ap_pll)
230{
Linus Walleijdece3702012-04-13 14:01:39 +0200231 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
232 keep_ap_pll);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200233}
234
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100235static inline u8 prcmu_get_power_state_result(void)
236{
Linus Walleijdece3702012-04-13 14:01:39 +0200237 return db8500_prcmu_get_power_state_result();
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100238}
239
Daniel Lezcano485540d2012-02-20 12:30:26 +0100240static inline int prcmu_gic_decouple(void)
241{
Linus Walleijdece3702012-04-13 14:01:39 +0200242 return db8500_prcmu_gic_decouple();
Daniel Lezcano485540d2012-02-20 12:30:26 +0100243}
244
245static inline int prcmu_gic_recouple(void)
246{
Linus Walleijdece3702012-04-13 14:01:39 +0200247 return db8500_prcmu_gic_recouple();
Daniel Lezcano485540d2012-02-20 12:30:26 +0100248}
249
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +0100250static inline bool prcmu_gic_pending_irq(void)
251{
Linus Walleijdece3702012-04-13 14:01:39 +0200252 return db8500_prcmu_gic_pending_irq();
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +0100253}
254
Daniel Lezcano34fe6f12012-02-28 22:46:09 +0100255static inline bool prcmu_is_cpu_in_wfi(int cpu)
256{
Linus Walleijdece3702012-04-13 14:01:39 +0200257 return db8500_prcmu_is_cpu_in_wfi(cpu);
Daniel Lezcano34fe6f12012-02-28 22:46:09 +0100258}
259
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100260static inline int prcmu_copy_gic_settings(void)
261{
Linus Walleijdece3702012-04-13 14:01:39 +0200262 return db8500_prcmu_copy_gic_settings();
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100263}
264
Daniel Lezcano9ab492e2012-02-28 22:46:08 +0100265static inline bool prcmu_pending_irq(void)
266{
Linus Walleijdece3702012-04-13 14:01:39 +0200267 return db8500_prcmu_pending_irq();
Daniel Lezcano9ab492e2012-02-28 22:46:08 +0100268}
269
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200270static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
271{
Linus Walleijdece3702012-04-13 14:01:39 +0200272 return db8500_prcmu_set_epod(epod_id, epod_state);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200273}
274
275static inline void prcmu_enable_wakeups(u32 wakeups)
276{
Linus Walleijdece3702012-04-13 14:01:39 +0200277 db8500_prcmu_enable_wakeups(wakeups);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200278}
279
280static inline void prcmu_disable_wakeups(void)
281{
282 prcmu_enable_wakeups(0);
283}
284
285static inline void prcmu_config_abb_event_readout(u32 abb_events)
286{
Linus Walleijdece3702012-04-13 14:01:39 +0200287 db8500_prcmu_config_abb_event_readout(abb_events);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200288}
289
290static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
291{
Linus Walleijdece3702012-04-13 14:01:39 +0200292 db8500_prcmu_get_abb_event_buffer(buf);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200293}
294
295int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
296int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
Mattias Nilsson3c3e4892012-03-08 14:02:05 +0100297int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200298
299int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
300
301static inline int prcmu_request_clock(u8 clock, bool enable)
302{
Linus Walleijdece3702012-04-13 14:01:39 +0200303 return db8500_prcmu_request_clock(clock, enable);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200304}
305
Mattias Nilsson05089012012-01-13 16:20:20 +0100306unsigned long prcmu_clock_rate(u8 clock);
307long prcmu_round_clock_rate(u8 clock, unsigned long rate);
308int prcmu_set_clock_rate(u8 clock, unsigned long rate);
309
310static inline int prcmu_set_ddr_opp(u8 opp)
311{
Linus Walleijdece3702012-04-13 14:01:39 +0200312 return db8500_prcmu_set_ddr_opp(opp);
Mattias Nilsson05089012012-01-13 16:20:20 +0100313}
314static inline int prcmu_get_ddr_opp(void)
315{
Linus Walleijdece3702012-04-13 14:01:39 +0200316 return db8500_prcmu_get_ddr_opp();
Mattias Nilsson05089012012-01-13 16:20:20 +0100317}
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200318
319static inline int prcmu_set_arm_opp(u8 opp)
320{
Linus Walleijdece3702012-04-13 14:01:39 +0200321 return db8500_prcmu_set_arm_opp(opp);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200322}
323
324static inline int prcmu_get_arm_opp(void)
325{
Linus Walleijdece3702012-04-13 14:01:39 +0200326 return db8500_prcmu_get_arm_opp();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200327}
328
Mattias Nilsson05089012012-01-13 16:20:20 +0100329static inline int prcmu_set_ape_opp(u8 opp)
330{
Linus Walleijdece3702012-04-13 14:01:39 +0200331 return db8500_prcmu_set_ape_opp(opp);
Mattias Nilsson05089012012-01-13 16:20:20 +0100332}
333
334static inline int prcmu_get_ape_opp(void)
335{
Linus Walleijdece3702012-04-13 14:01:39 +0200336 return db8500_prcmu_get_ape_opp();
Mattias Nilsson05089012012-01-13 16:20:20 +0100337}
338
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200339static inline void prcmu_system_reset(u16 reset_code)
340{
Linus Walleijdece3702012-04-13 14:01:39 +0200341 return db8500_prcmu_system_reset(reset_code);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200342}
343
344static inline u16 prcmu_get_reset_code(void)
345{
Linus Walleijdece3702012-04-13 14:01:39 +0200346 return db8500_prcmu_get_reset_code();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200347}
348
Arun Murthy5261e102012-05-21 14:28:21 +0530349int prcmu_ac_wake_req(void);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200350void prcmu_ac_sleep_req(void);
Mattias Nilsson05089012012-01-13 16:20:20 +0100351static inline void prcmu_modem_reset(void)
352{
Linus Walleijdece3702012-04-13 14:01:39 +0200353 return db8500_prcmu_modem_reset();
Mattias Nilsson05089012012-01-13 16:20:20 +0100354}
355
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200356static inline bool prcmu_is_ac_wake_requested(void)
357{
Linus Walleijdece3702012-04-13 14:01:39 +0200358 return db8500_prcmu_is_ac_wake_requested();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200359}
360
361static inline int prcmu_set_display_clocks(void)
362{
Linus Walleijdece3702012-04-13 14:01:39 +0200363 return db8500_prcmu_set_display_clocks();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200364}
365
366static inline int prcmu_disable_dsipll(void)
367{
Linus Walleijdece3702012-04-13 14:01:39 +0200368 return db8500_prcmu_disable_dsipll();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200369}
370
371static inline int prcmu_enable_dsipll(void)
372{
Linus Walleijdece3702012-04-13 14:01:39 +0200373 return db8500_prcmu_enable_dsipll();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200374}
375
376static inline int prcmu_config_esram0_deep_sleep(u8 state)
377{
Linus Walleijdece3702012-04-13 14:01:39 +0200378 return db8500_prcmu_config_esram0_deep_sleep(state);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200379}
Mattias Nilsson05089012012-01-13 16:20:20 +0100380
381static inline int prcmu_config_hotdog(u8 threshold)
382{
Linus Walleijdece3702012-04-13 14:01:39 +0200383 return db8500_prcmu_config_hotdog(threshold);
Mattias Nilsson05089012012-01-13 16:20:20 +0100384}
385
386static inline int prcmu_config_hotmon(u8 low, u8 high)
387{
Linus Walleijdece3702012-04-13 14:01:39 +0200388 return db8500_prcmu_config_hotmon(low, high);
Mattias Nilsson05089012012-01-13 16:20:20 +0100389}
390
391static inline int prcmu_start_temp_sense(u16 cycles32k)
392{
Linus Walleijdece3702012-04-13 14:01:39 +0200393 return db8500_prcmu_start_temp_sense(cycles32k);
Mattias Nilsson05089012012-01-13 16:20:20 +0100394}
395
396static inline int prcmu_stop_temp_sense(void)
397{
Linus Walleijdece3702012-04-13 14:01:39 +0200398 return db8500_prcmu_stop_temp_sense();
Mattias Nilsson05089012012-01-13 16:20:20 +0100399}
400
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100401static inline u32 prcmu_read(unsigned int reg)
402{
Linus Walleijdece3702012-04-13 14:01:39 +0200403 return db8500_prcmu_read(reg);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100404}
405
406static inline void prcmu_write(unsigned int reg, u32 value)
407{
Linus Walleijdece3702012-04-13 14:01:39 +0200408 db8500_prcmu_write(reg, value);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100409}
410
411static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
412{
Linus Walleijdece3702012-04-13 14:01:39 +0200413 db8500_prcmu_write_masked(reg, mask, value);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100414}
415
Mattias Nilsson05089012012-01-13 16:20:20 +0100416static inline int prcmu_enable_a9wdog(u8 id)
417{
Linus Walleijdece3702012-04-13 14:01:39 +0200418 return db8500_prcmu_enable_a9wdog(id);
Mattias Nilsson05089012012-01-13 16:20:20 +0100419}
420
421static inline int prcmu_disable_a9wdog(u8 id)
422{
Linus Walleijdece3702012-04-13 14:01:39 +0200423 return db8500_prcmu_disable_a9wdog(id);
Mattias Nilsson05089012012-01-13 16:20:20 +0100424}
425
426static inline int prcmu_kick_a9wdog(u8 id)
427{
Linus Walleijdece3702012-04-13 14:01:39 +0200428 return db8500_prcmu_kick_a9wdog(id);
Mattias Nilsson05089012012-01-13 16:20:20 +0100429}
430
431static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
432{
Linus Walleijdece3702012-04-13 14:01:39 +0200433 return db8500_prcmu_load_a9wdog(id, timeout);
Mattias Nilsson05089012012-01-13 16:20:20 +0100434}
435
436static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
437{
Linus Walleijdece3702012-04-13 14:01:39 +0200438 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
Mattias Nilsson05089012012-01-13 16:20:20 +0100439}
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200440#else
441
442static inline void __init prcmu_early_init(void) {}
443
444static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
445 bool keep_ap_pll)
446{
447 return 0;
448}
449
450static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
451{
452 return 0;
453}
454
455static inline void prcmu_enable_wakeups(u32 wakeups) {}
456
457static inline void prcmu_disable_wakeups(void) {}
458
459static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
460{
461 return -ENOSYS;
462}
463
464static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
465{
466 return -ENOSYS;
467}
468
Mattias Nilsson3c3e4892012-03-08 14:02:05 +0100469static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
470 u8 size)
471{
472 return -ENOSYS;
473}
474
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200475static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
476{
477 return 0;
478}
479
480static inline int prcmu_request_clock(u8 clock, bool enable)
481{
482 return 0;
483}
484
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100485static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
486{
487 return 0;
488}
489
490static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
491{
492 return 0;
493}
494
495static inline unsigned long prcmu_clock_rate(u8 clock)
496{
497 return 0;
498}
499
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200500static inline int prcmu_set_ape_opp(u8 opp)
501{
502 return 0;
503}
504
505static inline int prcmu_get_ape_opp(void)
506{
507 return APE_100_OPP;
508}
509
510static inline int prcmu_set_arm_opp(u8 opp)
511{
512 return 0;
513}
514
515static inline int prcmu_get_arm_opp(void)
516{
517 return ARM_100_OPP;
518}
519
520static inline int prcmu_set_ddr_opp(u8 opp)
521{
522 return 0;
523}
524
525static inline int prcmu_get_ddr_opp(void)
526{
527 return DDR_100_OPP;
528}
529
530static inline void prcmu_system_reset(u16 reset_code) {}
531
532static inline u16 prcmu_get_reset_code(void)
533{
534 return 0;
535}
536
Arun Murthy5261e102012-05-21 14:28:21 +0530537static inline int prcmu_ac_wake_req(void)
538{
539 return 0;
540}
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200541
542static inline void prcmu_ac_sleep_req(void) {}
543
544static inline void prcmu_modem_reset(void) {}
545
546static inline bool prcmu_is_ac_wake_requested(void)
547{
548 return false;
549}
550
551static inline int prcmu_set_display_clocks(void)
552{
553 return 0;
554}
555
556static inline int prcmu_disable_dsipll(void)
557{
558 return 0;
559}
560
561static inline int prcmu_enable_dsipll(void)
562{
563 return 0;
564}
565
566static inline int prcmu_config_esram0_deep_sleep(u8 state)
567{
568 return 0;
569}
570
571static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
572
573static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
574{
575 *buf = NULL;
576}
577
Mattias Nilsson05089012012-01-13 16:20:20 +0100578static inline int prcmu_config_hotdog(u8 threshold)
579{
580 return 0;
581}
582
583static inline int prcmu_config_hotmon(u8 low, u8 high)
584{
585 return 0;
586}
587
588static inline int prcmu_start_temp_sense(u16 cycles32k)
589{
590 return 0;
591}
592
593static inline int prcmu_stop_temp_sense(void)
594{
595 return 0;
596}
597
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100598static inline u32 prcmu_read(unsigned int reg)
599{
600 return 0;
601}
602
603static inline void prcmu_write(unsigned int reg, u32 value) {}
604
605static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
606
607#endif
608
609static inline void prcmu_set(unsigned int reg, u32 bits)
610{
611 prcmu_write_masked(reg, bits, bits);
612}
613
614static inline void prcmu_clear(unsigned int reg, u32 bits)
615{
616 prcmu_write_masked(reg, bits, 0);
617}
618
Linus Walleijdece3702012-04-13 14:01:39 +0200619#if defined(CONFIG_UX500_SOC_DB8500)
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100620
621/**
622 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
623 */
624static inline void prcmu_enable_spi2(void)
625{
626 if (cpu_is_u8500())
627 prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
628}
629
630/**
631 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
632 */
633static inline void prcmu_disable_spi2(void)
634{
635 if (cpu_is_u8500())
636 prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
637}
638
639/**
640 * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
641 * and UARTMOD on OtherAlternateC3.
642 */
643static inline void prcmu_enable_stm_mod_uart(void)
644{
645 if (cpu_is_u8500()) {
646 prcmu_set(DB8500_PRCM_GPIOCR,
647 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
648 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
649 }
650}
651
652/**
653 * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
654 * and UARTMOD on OtherAlternateC3.
655 */
656static inline void prcmu_disable_stm_mod_uart(void)
657{
658 if (cpu_is_u8500()) {
659 prcmu_clear(DB8500_PRCM_GPIOCR,
660 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
661 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
662 }
663}
664
665/**
666 * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
667 */
668static inline void prcmu_enable_stm_ape(void)
669{
670 if (cpu_is_u8500()) {
671 prcmu_set(DB8500_PRCM_GPIOCR,
672 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
673 }
674}
675
676/**
677 * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
678 */
679static inline void prcmu_disable_stm_ape(void)
680{
681 if (cpu_is_u8500()) {
682 prcmu_clear(DB8500_PRCM_GPIOCR,
683 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
684 }
685}
686
687#else
688
689static inline void prcmu_enable_spi2(void) {}
690static inline void prcmu_disable_spi2(void) {}
691static inline void prcmu_enable_stm_mod_uart(void) {}
692static inline void prcmu_disable_stm_mod_uart(void) {}
693static inline void prcmu_enable_stm_ape(void) {}
694static inline void prcmu_disable_stm_ape(void) {}
695
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200696#endif
697
698/* PRCMU QoS APE OPP class */
699#define PRCMU_QOS_APE_OPP 1
700#define PRCMU_QOS_DDR_OPP 2
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100701#define PRCMU_QOS_ARM_OPP 3
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200702#define PRCMU_QOS_DEFAULT_VALUE -1
703
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100704#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200705
706unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
707void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
708void prcmu_qos_force_opp(int, s32);
709int prcmu_qos_requirement(int pm_qos_class);
710int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
711int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
712void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
713int prcmu_qos_add_notifier(int prcmu_qos_class,
714 struct notifier_block *notifier);
715int prcmu_qos_remove_notifier(int prcmu_qos_class,
716 struct notifier_block *notifier);
717
718#else
719
720static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
721{
722 return 0;
723}
724
725static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
726
727static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
728
729static inline int prcmu_qos_requirement(int prcmu_qos_class)
730{
731 return 0;
732}
733
734static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
735 char *name, s32 value)
736{
737 return 0;
738}
739
740static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
741 char *name, s32 new_value)
742{
743 return 0;
744}
745
746static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
747{
748}
749
750static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
751 struct notifier_block *notifier)
752{
753 return 0;
754}
755static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
756 struct notifier_block *notifier)
757{
758 return 0;
759}
760
761#endif
762
763#endif /* __MACH_PRCMU_H */