Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1 | /* |
Tomoya MORINAGA | eca9dfa | 2011-10-28 09:38:50 +0900 | [diff] [blame] | 2 | *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 3 | * |
| 4 | *This program is free software; you can redistribute it and/or modify |
| 5 | *it under the terms of the GNU General Public License as published by |
| 6 | *the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | *This program is distributed in the hope that it will be useful, |
| 9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | *GNU General Public License for more details. |
| 12 | * |
| 13 | *You should have received a copy of the GNU General Public License |
| 14 | *along with this program; if not, write to the Free Software |
| 15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 16 | */ |
Uwe Kleine-König | 0e2adc0 | 2011-05-26 10:41:17 +0200 | [diff] [blame] | 17 | #include <linux/kernel.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 18 | #include <linux/serial_reg.h> |
Andrew Morton | 023bc8e | 2011-05-24 17:13:44 -0700 | [diff] [blame] | 19 | #include <linux/slab.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/pci.h> |
| 22 | #include <linux/serial_core.h> |
Jiri Slaby | ee160a3 | 2011-09-01 16:20:57 +0200 | [diff] [blame] | 23 | #include <linux/tty.h> |
| 24 | #include <linux/tty_flip.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/io.h> |
Denis Turischev | 6ae705b | 2011-03-10 15:14:00 +0200 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 28 | #include <linux/console.h> |
| 29 | #include <linux/nmi.h> |
| 30 | #include <linux/delay.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 31 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 33 | #include <linux/dmaengine.h> |
| 34 | #include <linux/pch_dma.h> |
| 35 | |
| 36 | enum { |
| 37 | PCH_UART_HANDLED_RX_INT_SHIFT, |
| 38 | PCH_UART_HANDLED_TX_INT_SHIFT, |
| 39 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, |
| 40 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, |
| 41 | PCH_UART_HANDLED_MS_INT_SHIFT, |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 42 | PCH_UART_HANDLED_LS_INT_SHIFT, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | enum { |
| 46 | PCH_UART_8LINE, |
| 47 | PCH_UART_2LINE, |
| 48 | }; |
| 49 | |
| 50 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" |
| 51 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 52 | /* Set the max number of UART port |
| 53 | * Intel EG20T PCH: 4 port |
Tomoya MORINAGA | eca9dfa | 2011-10-28 09:38:50 +0900 | [diff] [blame] | 54 | * LAPIS Semiconductor ML7213 IOH: 3 port |
| 55 | * LAPIS Semiconductor ML7223 IOH: 2 port |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 56 | */ |
| 57 | #define PCH_UART_NR 4 |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 58 | |
| 59 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) |
| 60 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) |
| 61 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ |
| 62 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) |
| 63 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ |
| 64 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) |
| 65 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) |
| 66 | |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 67 | #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) |
| 68 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 69 | #define PCH_UART_RBR 0x00 |
| 70 | #define PCH_UART_THR 0x00 |
| 71 | |
| 72 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ |
| 73 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) |
| 74 | #define PCH_UART_IER_ERBFI 0x00000001 |
| 75 | #define PCH_UART_IER_ETBEI 0x00000002 |
| 76 | #define PCH_UART_IER_ELSI 0x00000004 |
| 77 | #define PCH_UART_IER_EDSSI 0x00000008 |
| 78 | |
| 79 | #define PCH_UART_IIR_IP 0x00000001 |
| 80 | #define PCH_UART_IIR_IID 0x00000006 |
| 81 | #define PCH_UART_IIR_MSI 0x00000000 |
| 82 | #define PCH_UART_IIR_TRI 0x00000002 |
| 83 | #define PCH_UART_IIR_RRI 0x00000004 |
| 84 | #define PCH_UART_IIR_REI 0x00000006 |
| 85 | #define PCH_UART_IIR_TOI 0x00000008 |
| 86 | #define PCH_UART_IIR_FIFO256 0x00000020 |
| 87 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 |
| 88 | #define PCH_UART_IIR_FE 0x000000C0 |
| 89 | |
| 90 | #define PCH_UART_FCR_FIFOE 0x00000001 |
| 91 | #define PCH_UART_FCR_RFR 0x00000002 |
| 92 | #define PCH_UART_FCR_TFR 0x00000004 |
| 93 | #define PCH_UART_FCR_DMS 0x00000008 |
| 94 | #define PCH_UART_FCR_FIFO256 0x00000020 |
| 95 | #define PCH_UART_FCR_RFTL 0x000000C0 |
| 96 | |
| 97 | #define PCH_UART_FCR_RFTL1 0x00000000 |
| 98 | #define PCH_UART_FCR_RFTL64 0x00000040 |
| 99 | #define PCH_UART_FCR_RFTL128 0x00000080 |
| 100 | #define PCH_UART_FCR_RFTL224 0x000000C0 |
| 101 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 |
| 102 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 |
| 103 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 |
| 104 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 |
| 105 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 |
| 106 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 |
| 107 | #define PCH_UART_FCR_RFTL_SHIFT 6 |
| 108 | |
| 109 | #define PCH_UART_LCR_WLS 0x00000003 |
| 110 | #define PCH_UART_LCR_STB 0x00000004 |
| 111 | #define PCH_UART_LCR_PEN 0x00000008 |
| 112 | #define PCH_UART_LCR_EPS 0x00000010 |
| 113 | #define PCH_UART_LCR_SP 0x00000020 |
| 114 | #define PCH_UART_LCR_SB 0x00000040 |
| 115 | #define PCH_UART_LCR_DLAB 0x00000080 |
| 116 | #define PCH_UART_LCR_NP 0x00000000 |
| 117 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN |
| 118 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) |
| 119 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) |
| 120 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ |
| 121 | PCH_UART_LCR_SP) |
| 122 | |
| 123 | #define PCH_UART_LCR_5BIT 0x00000000 |
| 124 | #define PCH_UART_LCR_6BIT 0x00000001 |
| 125 | #define PCH_UART_LCR_7BIT 0x00000002 |
| 126 | #define PCH_UART_LCR_8BIT 0x00000003 |
| 127 | |
| 128 | #define PCH_UART_MCR_DTR 0x00000001 |
| 129 | #define PCH_UART_MCR_RTS 0x00000002 |
| 130 | #define PCH_UART_MCR_OUT 0x0000000C |
| 131 | #define PCH_UART_MCR_LOOP 0x00000010 |
| 132 | #define PCH_UART_MCR_AFE 0x00000020 |
| 133 | |
| 134 | #define PCH_UART_LSR_DR 0x00000001 |
| 135 | #define PCH_UART_LSR_ERR (1<<7) |
| 136 | |
| 137 | #define PCH_UART_MSR_DCTS 0x00000001 |
| 138 | #define PCH_UART_MSR_DDSR 0x00000002 |
| 139 | #define PCH_UART_MSR_TERI 0x00000004 |
| 140 | #define PCH_UART_MSR_DDCD 0x00000008 |
| 141 | #define PCH_UART_MSR_CTS 0x00000010 |
| 142 | #define PCH_UART_MSR_DSR 0x00000020 |
| 143 | #define PCH_UART_MSR_RI 0x00000040 |
| 144 | #define PCH_UART_MSR_DCD 0x00000080 |
| 145 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ |
| 146 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) |
| 147 | |
| 148 | #define PCH_UART_DLL 0x00 |
| 149 | #define PCH_UART_DLM 0x01 |
| 150 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 151 | #define PCH_UART_BRCSR 0x0E |
| 152 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 153 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) |
| 154 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) |
| 155 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) |
| 156 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) |
| 157 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) |
| 158 | |
| 159 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) |
| 160 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) |
| 161 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) |
| 162 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) |
| 163 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) |
| 164 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) |
| 165 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) |
| 166 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) |
| 167 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) |
| 168 | #define PCH_UART_HAL_STB1 0 |
| 169 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) |
| 170 | |
| 171 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) |
| 172 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) |
| 173 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ |
| 174 | PCH_UART_HAL_CLR_RX_FIFO) |
| 175 | |
| 176 | #define PCH_UART_HAL_DMA_MODE0 0 |
| 177 | #define PCH_UART_HAL_FIFO_DIS 0 |
| 178 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) |
| 179 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ |
| 180 | PCH_UART_FCR_FIFO256) |
| 181 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) |
| 182 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) |
| 183 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) |
| 184 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) |
| 185 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) |
| 186 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) |
| 187 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) |
| 188 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) |
| 189 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) |
| 190 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) |
| 191 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) |
| 192 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) |
| 193 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) |
| 194 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) |
| 195 | |
| 196 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) |
| 197 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) |
| 198 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) |
| 199 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) |
| 200 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) |
| 201 | |
| 202 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) |
| 203 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) |
| 204 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) |
| 205 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) |
| 206 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) |
| 207 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 208 | #define PCI_VENDOR_ID_ROHM 0x10DB |
| 209 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 210 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
| 211 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 212 | #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ |
| 213 | #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ |
| 214 | #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ |
| 215 | #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ |
Michael Brunner | 11bbd5b | 2012-03-23 11:06:37 +0100 | [diff] [blame] | 216 | #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 217 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 218 | struct pch_uart_buffer { |
| 219 | unsigned char *buf; |
| 220 | int size; |
| 221 | }; |
| 222 | |
| 223 | struct eg20t_port { |
| 224 | struct uart_port port; |
| 225 | int port_type; |
| 226 | void __iomem *membase; |
| 227 | resource_size_t mapbase; |
| 228 | unsigned int iobase; |
| 229 | struct pci_dev *pdev; |
| 230 | int fifo_size; |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 231 | int uartclk; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 232 | int start_tx; |
| 233 | int start_rx; |
| 234 | int tx_empty; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 235 | int trigger; |
| 236 | int trigger_level; |
| 237 | struct pch_uart_buffer rxbuf; |
| 238 | unsigned int dmsr; |
| 239 | unsigned int fcr; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 240 | unsigned int mcr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 241 | unsigned int use_dma; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 242 | struct dma_async_tx_descriptor *desc_tx; |
| 243 | struct dma_async_tx_descriptor *desc_rx; |
| 244 | struct pch_dma_slave param_tx; |
| 245 | struct pch_dma_slave param_rx; |
| 246 | struct dma_chan *chan_tx; |
| 247 | struct dma_chan *chan_rx; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 248 | struct scatterlist *sg_tx_p; |
| 249 | int nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 250 | struct scatterlist sg_rx; |
| 251 | int tx_dma_use; |
| 252 | void *rx_buf_virt; |
| 253 | dma_addr_t rx_buf_dma; |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 254 | |
| 255 | struct dentry *debugfs; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 256 | |
| 257 | /* protect the eg20t_port private structure and io access to membase */ |
| 258 | spinlock_t lock; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 259 | }; |
| 260 | |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 261 | /** |
| 262 | * struct pch_uart_driver_data - private data structure for UART-DMA |
| 263 | * @port_type: The number of DMA channel |
| 264 | * @line_no: UART port line number (0, 1, 2...) |
| 265 | */ |
| 266 | struct pch_uart_driver_data { |
| 267 | int port_type; |
| 268 | int line_no; |
| 269 | }; |
| 270 | |
| 271 | enum pch_uart_num_t { |
| 272 | pch_et20t_uart0 = 0, |
| 273 | pch_et20t_uart1, |
| 274 | pch_et20t_uart2, |
| 275 | pch_et20t_uart3, |
| 276 | pch_ml7213_uart0, |
| 277 | pch_ml7213_uart1, |
| 278 | pch_ml7213_uart2, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 279 | pch_ml7223_uart0, |
| 280 | pch_ml7223_uart1, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 281 | pch_ml7831_uart0, |
| 282 | pch_ml7831_uart1, |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 283 | }; |
| 284 | |
| 285 | static struct pch_uart_driver_data drv_dat[] = { |
| 286 | [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, |
| 287 | [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, |
| 288 | [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, |
| 289 | [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, |
| 290 | [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, |
| 291 | [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, |
| 292 | [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 293 | [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, |
| 294 | [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 295 | [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, |
| 296 | [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 297 | }; |
| 298 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 299 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 300 | static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; |
| 301 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 302 | static unsigned int default_baud = 9600; |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 303 | static unsigned int user_uartclk = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 304 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; |
| 305 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; |
| 306 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; |
| 307 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; |
| 308 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 309 | #ifdef CONFIG_DEBUG_FS |
| 310 | |
| 311 | #define PCH_REGS_BUFSIZE 1024 |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 312 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 313 | |
| 314 | static ssize_t port_show_regs(struct file *file, char __user *user_buf, |
| 315 | size_t count, loff_t *ppos) |
| 316 | { |
| 317 | struct eg20t_port *priv = file->private_data; |
| 318 | char *buf; |
| 319 | u32 len = 0; |
| 320 | ssize_t ret; |
| 321 | unsigned char lcr; |
| 322 | |
| 323 | buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); |
| 324 | if (!buf) |
| 325 | return 0; |
| 326 | |
| 327 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 328 | "PCH EG20T port[%d] regs:\n", priv->port.line); |
| 329 | |
| 330 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 331 | "=================================\n"); |
| 332 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 333 | "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); |
| 334 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 335 | "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); |
| 336 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 337 | "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); |
| 338 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 339 | "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); |
| 340 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 341 | "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); |
| 342 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 343 | "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); |
| 344 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 345 | "BRCSR: \t0x%02x\n", |
| 346 | ioread8(priv->membase + PCH_UART_BRCSR)); |
| 347 | |
| 348 | lcr = ioread8(priv->membase + UART_LCR); |
| 349 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 350 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 351 | "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); |
| 352 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 353 | "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); |
| 354 | iowrite8(lcr, priv->membase + UART_LCR); |
| 355 | |
| 356 | if (len > PCH_REGS_BUFSIZE) |
| 357 | len = PCH_REGS_BUFSIZE; |
| 358 | |
| 359 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 360 | kfree(buf); |
| 361 | return ret; |
| 362 | } |
| 363 | |
| 364 | static const struct file_operations port_regs_ops = { |
| 365 | .owner = THIS_MODULE, |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 366 | .open = simple_open, |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 367 | .read = port_show_regs, |
| 368 | .llseek = default_llseek, |
| 369 | }; |
| 370 | #endif /* CONFIG_DEBUG_FS */ |
| 371 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 372 | /* Return UART clock, checking for board specific clocks. */ |
| 373 | static int pch_uart_get_uartclk(void) |
| 374 | { |
| 375 | const char *cmp; |
| 376 | |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 377 | if (user_uartclk) |
| 378 | return user_uartclk; |
| 379 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 380 | cmp = dmi_get_system_info(DMI_BOARD_NAME); |
| 381 | if (cmp && strstr(cmp, "CM-iTC")) |
| 382 | return CMITC_UARTCLK; |
| 383 | |
| 384 | cmp = dmi_get_system_info(DMI_BIOS_VERSION); |
| 385 | if (cmp && strnstr(cmp, "FRI2", 4)) |
| 386 | return FRI2_64_UARTCLK; |
| 387 | |
| 388 | cmp = dmi_get_system_info(DMI_PRODUCT_NAME); |
| 389 | if (cmp && strstr(cmp, "Fish River Island II")) |
| 390 | return FRI2_48_UARTCLK; |
| 391 | |
Michael Brunner | 11bbd5b | 2012-03-23 11:06:37 +0100 | [diff] [blame] | 392 | /* Kontron COMe-mTT10 (nanoETXexpress-TT) */ |
| 393 | cmp = dmi_get_system_info(DMI_BOARD_NAME); |
| 394 | if (cmp && (strstr(cmp, "COMe-mTT") || |
| 395 | strstr(cmp, "nanoETXexpress-TT"))) |
| 396 | return NTC1_UARTCLK; |
| 397 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 398 | return DEFAULT_UARTCLK; |
| 399 | } |
| 400 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 401 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, |
| 402 | unsigned int flag) |
| 403 | { |
| 404 | u8 ier = ioread8(priv->membase + UART_IER); |
| 405 | ier |= flag & PCH_UART_IER_MASK; |
| 406 | iowrite8(ier, priv->membase + UART_IER); |
| 407 | } |
| 408 | |
| 409 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, |
| 410 | unsigned int flag) |
| 411 | { |
| 412 | u8 ier = ioread8(priv->membase + UART_IER); |
| 413 | ier &= ~(flag & PCH_UART_IER_MASK); |
| 414 | iowrite8(ier, priv->membase + UART_IER); |
| 415 | } |
| 416 | |
| 417 | static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, |
| 418 | unsigned int parity, unsigned int bits, |
| 419 | unsigned int stb) |
| 420 | { |
| 421 | unsigned int dll, dlm, lcr; |
| 422 | int div; |
| 423 | |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 424 | div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 425 | if (div < 0 || USHRT_MAX <= div) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 426 | dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 427 | return -EINVAL; |
| 428 | } |
| 429 | |
| 430 | dll = (unsigned int)div & 0x00FFU; |
| 431 | dlm = ((unsigned int)div >> 8) & 0x00FFU; |
| 432 | |
| 433 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 434 | dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 435 | return -EINVAL; |
| 436 | } |
| 437 | |
| 438 | if (bits & ~PCH_UART_LCR_WLS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 439 | dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 440 | return -EINVAL; |
| 441 | } |
| 442 | |
| 443 | if (stb & ~PCH_UART_LCR_STB) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 444 | dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 445 | return -EINVAL; |
| 446 | } |
| 447 | |
| 448 | lcr = parity; |
| 449 | lcr |= bits; |
| 450 | lcr |= stb; |
| 451 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 452 | dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 453 | __func__, baud, div, lcr, jiffies); |
| 454 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 455 | iowrite8(dll, priv->membase + PCH_UART_DLL); |
| 456 | iowrite8(dlm, priv->membase + PCH_UART_DLM); |
| 457 | iowrite8(lcr, priv->membase + UART_LCR); |
| 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, |
| 463 | unsigned int flag) |
| 464 | { |
| 465 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 466 | dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", |
| 467 | __func__, flag); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 468 | return -EINVAL; |
| 469 | } |
| 470 | |
| 471 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); |
| 472 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, |
| 473 | priv->membase + UART_FCR); |
| 474 | iowrite8(priv->fcr, priv->membase + UART_FCR); |
| 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, |
| 480 | unsigned int dmamode, |
| 481 | unsigned int fifo_size, unsigned int trigger) |
| 482 | { |
| 483 | u8 fcr; |
| 484 | |
| 485 | if (dmamode & ~PCH_UART_FCR_DMS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 486 | dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", |
| 487 | __func__, dmamode); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 488 | return -EINVAL; |
| 489 | } |
| 490 | |
| 491 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 492 | dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", |
| 493 | __func__, fifo_size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 494 | return -EINVAL; |
| 495 | } |
| 496 | |
| 497 | if (trigger & ~PCH_UART_FCR_RFTL) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 498 | dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", |
| 499 | __func__, trigger); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 500 | return -EINVAL; |
| 501 | } |
| 502 | |
| 503 | switch (priv->fifo_size) { |
| 504 | case 256: |
| 505 | priv->trigger_level = |
| 506 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 507 | break; |
| 508 | case 64: |
| 509 | priv->trigger_level = |
| 510 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 511 | break; |
| 512 | case 16: |
| 513 | priv->trigger_level = |
| 514 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 515 | break; |
| 516 | default: |
| 517 | priv->trigger_level = |
| 518 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 519 | break; |
| 520 | } |
| 521 | fcr = |
| 522 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; |
| 523 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); |
| 524 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, |
| 525 | priv->membase + UART_FCR); |
| 526 | iowrite8(fcr, priv->membase + UART_FCR); |
| 527 | priv->fcr = fcr; |
| 528 | |
| 529 | return 0; |
| 530 | } |
| 531 | |
| 532 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) |
| 533 | { |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 534 | unsigned int msr = ioread8(priv->membase + UART_MSR); |
| 535 | priv->dmsr = msr & PCH_UART_MSR_DELTA; |
| 536 | return (u8)msr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 537 | } |
| 538 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 539 | static void pch_uart_hal_write(struct eg20t_port *priv, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 540 | const unsigned char *buf, int tx_size) |
| 541 | { |
| 542 | int i; |
| 543 | unsigned int thr; |
| 544 | |
| 545 | for (i = 0; i < tx_size;) { |
| 546 | thr = buf[i++]; |
| 547 | iowrite8(thr, priv->membase + PCH_UART_THR); |
| 548 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, |
| 552 | int rx_size) |
| 553 | { |
| 554 | int i; |
| 555 | u8 rbr, lsr; |
| 556 | |
| 557 | lsr = ioread8(priv->membase + UART_LSR); |
| 558 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); |
| 559 | i < rx_size && lsr & UART_LSR_DR; |
| 560 | lsr = ioread8(priv->membase + UART_LSR)) { |
| 561 | rbr = ioread8(priv->membase + PCH_UART_RBR); |
| 562 | buf[i++] = rbr; |
| 563 | } |
| 564 | return i; |
| 565 | } |
| 566 | |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 567 | static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 568 | { |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 569 | return ioread8(priv->membase + UART_IIR) &\ |
| 570 | (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) |
| 574 | { |
| 575 | return ioread8(priv->membase + UART_LSR); |
| 576 | } |
| 577 | |
| 578 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) |
| 579 | { |
| 580 | unsigned int lcr; |
| 581 | |
| 582 | lcr = ioread8(priv->membase + UART_LCR); |
| 583 | if (on) |
| 584 | lcr |= PCH_UART_LCR_SB; |
| 585 | else |
| 586 | lcr &= ~PCH_UART_LCR_SB; |
| 587 | |
| 588 | iowrite8(lcr, priv->membase + UART_LCR); |
| 589 | } |
| 590 | |
| 591 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, |
| 592 | int size) |
| 593 | { |
| 594 | struct uart_port *port; |
| 595 | struct tty_struct *tty; |
| 596 | |
| 597 | port = &priv->port; |
| 598 | tty = tty_port_tty_get(&port->state->port); |
| 599 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 600 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 601 | return -EBUSY; |
| 602 | } |
| 603 | |
| 604 | tty_insert_flip_string(tty, buf, size); |
| 605 | tty_flip_buffer_push(tty); |
| 606 | tty_kref_put(tty); |
| 607 | |
| 608 | return 0; |
| 609 | } |
| 610 | |
| 611 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) |
| 612 | { |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 613 | int ret = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 614 | struct uart_port *port = &priv->port; |
| 615 | |
| 616 | if (port->x_char) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 617 | dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", |
| 618 | __func__, port->x_char, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 619 | buf[0] = port->x_char; |
| 620 | port->x_char = 0; |
| 621 | ret = 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 622 | } |
| 623 | |
| 624 | return ret; |
| 625 | } |
| 626 | |
| 627 | static int dma_push_rx(struct eg20t_port *priv, int size) |
| 628 | { |
| 629 | struct tty_struct *tty; |
| 630 | int room; |
| 631 | struct uart_port *port = &priv->port; |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame^] | 632 | struct tty_port *tport = &port->state->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 633 | |
| 634 | port = &priv->port; |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame^] | 635 | tty = tty_port_tty_get(tport); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 636 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 637 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 638 | return 0; |
| 639 | } |
| 640 | |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame^] | 641 | room = tty_buffer_request_room(tport, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 642 | |
| 643 | if (room < size) |
| 644 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", |
| 645 | size - room); |
| 646 | if (!room) |
| 647 | return room; |
| 648 | |
| 649 | tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); |
| 650 | |
| 651 | port->icount.rx += room; |
| 652 | tty_kref_put(tty); |
| 653 | |
| 654 | return room; |
| 655 | } |
| 656 | |
| 657 | static void pch_free_dma(struct uart_port *port) |
| 658 | { |
| 659 | struct eg20t_port *priv; |
| 660 | priv = container_of(port, struct eg20t_port, port); |
| 661 | |
| 662 | if (priv->chan_tx) { |
| 663 | dma_release_channel(priv->chan_tx); |
| 664 | priv->chan_tx = NULL; |
| 665 | } |
| 666 | if (priv->chan_rx) { |
| 667 | dma_release_channel(priv->chan_rx); |
| 668 | priv->chan_rx = NULL; |
| 669 | } |
Tomoya MORINAGA | ef4f9d4 | 2012-03-26 14:43:06 +0900 | [diff] [blame] | 670 | |
| 671 | if (priv->rx_buf_dma) { |
| 672 | dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, |
| 673 | priv->rx_buf_dma); |
| 674 | priv->rx_buf_virt = NULL; |
| 675 | priv->rx_buf_dma = 0; |
| 676 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 677 | |
| 678 | return; |
| 679 | } |
| 680 | |
| 681 | static bool filter(struct dma_chan *chan, void *slave) |
| 682 | { |
| 683 | struct pch_dma_slave *param = slave; |
| 684 | |
| 685 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == |
| 686 | chan->device->dev)) { |
| 687 | chan->private = param; |
| 688 | return true; |
| 689 | } else { |
| 690 | return false; |
| 691 | } |
| 692 | } |
| 693 | |
| 694 | static void pch_request_dma(struct uart_port *port) |
| 695 | { |
| 696 | dma_cap_mask_t mask; |
| 697 | struct dma_chan *chan; |
| 698 | struct pci_dev *dma_dev; |
| 699 | struct pch_dma_slave *param; |
| 700 | struct eg20t_port *priv = |
| 701 | container_of(port, struct eg20t_port, port); |
| 702 | dma_cap_zero(mask); |
| 703 | dma_cap_set(DMA_SLAVE, mask); |
| 704 | |
Tomoya MORINAGA | 6c4b47d | 2011-07-20 20:17:49 +0900 | [diff] [blame] | 705 | dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, |
| 706 | PCI_DEVFN(0xa, 0)); /* Get DMA's dev |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 707 | information */ |
| 708 | /* Set Tx DMA */ |
| 709 | param = &priv->param_tx; |
| 710 | param->dma_dev = &dma_dev->dev; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 711 | param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ |
| 712 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 713 | param->tx_reg = port->mapbase + UART_TX; |
| 714 | chan = dma_request_channel(mask, filter, param); |
| 715 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 716 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", |
| 717 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 718 | return; |
| 719 | } |
| 720 | priv->chan_tx = chan; |
| 721 | |
| 722 | /* Set Rx DMA */ |
| 723 | param = &priv->param_rx; |
| 724 | param->dma_dev = &dma_dev->dev; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 725 | param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ |
| 726 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 727 | param->rx_reg = port->mapbase + UART_RX; |
| 728 | chan = dma_request_channel(mask, filter, param); |
| 729 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 730 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", |
| 731 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 732 | dma_release_channel(priv->chan_tx); |
Tomoya MORINAGA | 90f04c2 | 2011-11-11 10:55:27 +0900 | [diff] [blame] | 733 | priv->chan_tx = NULL; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 734 | return; |
| 735 | } |
| 736 | |
| 737 | /* Get Consistent memory for DMA */ |
| 738 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, |
| 739 | &priv->rx_buf_dma, GFP_KERNEL); |
| 740 | priv->chan_rx = chan; |
| 741 | } |
| 742 | |
| 743 | static void pch_dma_rx_complete(void *arg) |
| 744 | { |
| 745 | struct eg20t_port *priv = arg; |
| 746 | struct uart_port *port = &priv->port; |
| 747 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 748 | int count; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 749 | |
| 750 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 751 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 752 | return; |
| 753 | } |
| 754 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 755 | dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); |
| 756 | count = dma_push_rx(priv, priv->trigger_level); |
| 757 | if (count) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 758 | tty_flip_buffer_push(tty); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 759 | tty_kref_put(tty); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 760 | async_tx_ack(priv->desc_rx); |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 761 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 762 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 763 | } |
| 764 | |
| 765 | static void pch_dma_tx_complete(void *arg) |
| 766 | { |
| 767 | struct eg20t_port *priv = arg; |
| 768 | struct uart_port *port = &priv->port; |
| 769 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 770 | struct scatterlist *sg = priv->sg_tx_p; |
| 771 | int i; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 772 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 773 | for (i = 0; i < priv->nent; i++, sg++) { |
| 774 | xmit->tail += sg_dma_len(sg); |
| 775 | port->icount.tx += sg_dma_len(sg); |
| 776 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 777 | xmit->tail &= UART_XMIT_SIZE - 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 778 | async_tx_ack(priv->desc_tx); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 779 | dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 780 | priv->tx_dma_use = 0; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 781 | priv->nent = 0; |
| 782 | kfree(priv->sg_tx_p); |
Tomoya MORINAGA | 60d1031 | 2011-02-23 10:03:18 +0900 | [diff] [blame] | 783 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 784 | } |
| 785 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 786 | static int pop_tx(struct eg20t_port *priv, int size) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 787 | { |
| 788 | int count = 0; |
| 789 | struct uart_port *port = &priv->port; |
| 790 | struct circ_buf *xmit = &port->state->xmit; |
| 791 | |
| 792 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) |
| 793 | goto pop_tx_end; |
| 794 | |
| 795 | do { |
| 796 | int cnt_to_end = |
| 797 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
| 798 | int sz = min(size - count, cnt_to_end); |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 799 | pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 800 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); |
| 801 | count += sz; |
| 802 | } while (!uart_circ_empty(xmit) && count < size); |
| 803 | |
| 804 | pop_tx_end: |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 805 | dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 806 | count, size - count, jiffies); |
| 807 | |
| 808 | return count; |
| 809 | } |
| 810 | |
| 811 | static int handle_rx_to(struct eg20t_port *priv) |
| 812 | { |
| 813 | struct pch_uart_buffer *buf; |
| 814 | int rx_size; |
| 815 | int ret; |
| 816 | if (!priv->start_rx) { |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 817 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 818 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 819 | return 0; |
| 820 | } |
| 821 | buf = &priv->rxbuf; |
| 822 | do { |
| 823 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); |
| 824 | ret = push_rx(priv, buf->buf, rx_size); |
| 825 | if (ret) |
| 826 | return 0; |
| 827 | } while (rx_size == buf->size); |
| 828 | |
| 829 | return PCH_UART_HANDLED_RX_INT; |
| 830 | } |
| 831 | |
| 832 | static int handle_rx(struct eg20t_port *priv) |
| 833 | { |
| 834 | return handle_rx_to(priv); |
| 835 | } |
| 836 | |
| 837 | static int dma_handle_rx(struct eg20t_port *priv) |
| 838 | { |
| 839 | struct uart_port *port = &priv->port; |
| 840 | struct dma_async_tx_descriptor *desc; |
| 841 | struct scatterlist *sg; |
| 842 | |
| 843 | priv = container_of(port, struct eg20t_port, port); |
| 844 | sg = &priv->sg_rx; |
| 845 | |
| 846 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ |
| 847 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 848 | sg_dma_len(sg) = priv->trigger_level; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 849 | |
| 850 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 851 | sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & |
| 852 | ~PAGE_MASK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 853 | |
| 854 | sg_dma_address(sg) = priv->rx_buf_dma; |
| 855 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 856 | desc = dmaengine_prep_slave_sg(priv->chan_rx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 857 | sg, 1, DMA_DEV_TO_MEM, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 858 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 859 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 860 | if (!desc) |
| 861 | return 0; |
| 862 | |
| 863 | priv->desc_rx = desc; |
| 864 | desc->callback = pch_dma_rx_complete; |
| 865 | desc->callback_param = priv; |
| 866 | desc->tx_submit(desc); |
| 867 | dma_async_issue_pending(priv->chan_rx); |
| 868 | |
| 869 | return PCH_UART_HANDLED_RX_INT; |
| 870 | } |
| 871 | |
| 872 | static unsigned int handle_tx(struct eg20t_port *priv) |
| 873 | { |
| 874 | struct uart_port *port = &priv->port; |
| 875 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 876 | int fifo_size; |
| 877 | int tx_size; |
| 878 | int size; |
| 879 | int tx_empty; |
| 880 | |
| 881 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 882 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 883 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 884 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 885 | priv->tx_empty = 1; |
| 886 | return 0; |
| 887 | } |
| 888 | |
| 889 | fifo_size = max(priv->fifo_size, 1); |
| 890 | tx_empty = 1; |
| 891 | if (pop_tx_x(priv, xmit->buf)) { |
| 892 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 893 | port->icount.tx++; |
| 894 | tx_empty = 0; |
| 895 | fifo_size--; |
| 896 | } |
| 897 | size = min(xmit->head - xmit->tail, fifo_size); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 898 | if (size < 0) |
| 899 | size = fifo_size; |
| 900 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 901 | tx_size = pop_tx(priv, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 902 | if (tx_size > 0) { |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 903 | port->icount.tx += tx_size; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 904 | tx_empty = 0; |
| 905 | } |
| 906 | |
| 907 | priv->tx_empty = tx_empty; |
| 908 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 909 | if (tx_empty) { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 910 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 911 | uart_write_wakeup(port); |
| 912 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 913 | |
| 914 | return PCH_UART_HANDLED_TX_INT; |
| 915 | } |
| 916 | |
| 917 | static unsigned int dma_handle_tx(struct eg20t_port *priv) |
| 918 | { |
| 919 | struct uart_port *port = &priv->port; |
| 920 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 921 | struct scatterlist *sg; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 922 | int nent; |
| 923 | int fifo_size; |
| 924 | int tx_empty; |
| 925 | struct dma_async_tx_descriptor *desc; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 926 | int num; |
| 927 | int i; |
| 928 | int bytes; |
| 929 | int size; |
| 930 | int rem; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 931 | |
| 932 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 933 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 934 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 935 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 936 | priv->tx_empty = 1; |
| 937 | return 0; |
| 938 | } |
| 939 | |
Tomoya MORINAGA | 60d1031 | 2011-02-23 10:03:18 +0900 | [diff] [blame] | 940 | if (priv->tx_dma_use) { |
| 941 | dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", |
| 942 | __func__, jiffies); |
| 943 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 944 | priv->tx_empty = 1; |
| 945 | return 0; |
| 946 | } |
| 947 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 948 | fifo_size = max(priv->fifo_size, 1); |
| 949 | tx_empty = 1; |
| 950 | if (pop_tx_x(priv, xmit->buf)) { |
| 951 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 952 | port->icount.tx++; |
| 953 | tx_empty = 0; |
| 954 | fifo_size--; |
| 955 | } |
| 956 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 957 | bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, |
| 958 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, |
| 959 | xmit->tail, UART_XMIT_SIZE)); |
| 960 | if (!bytes) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 961 | dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 962 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 963 | uart_write_wakeup(port); |
| 964 | return 0; |
| 965 | } |
| 966 | |
| 967 | if (bytes > fifo_size) { |
| 968 | num = bytes / fifo_size + 1; |
| 969 | size = fifo_size; |
| 970 | rem = bytes % fifo_size; |
| 971 | } else { |
| 972 | num = 1; |
| 973 | size = bytes; |
| 974 | rem = bytes; |
| 975 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 976 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 977 | dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", |
| 978 | __func__, num, size, rem); |
| 979 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 980 | priv->tx_dma_use = 1; |
| 981 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 982 | priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
Fengguang Wu | a92098a | 2012-07-28 20:43:57 +0800 | [diff] [blame] | 983 | if (!priv->sg_tx_p) { |
| 984 | dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); |
| 985 | return 0; |
| 986 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 987 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 988 | sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ |
| 989 | sg = priv->sg_tx_p; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 990 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 991 | for (i = 0; i < num; i++, sg++) { |
| 992 | if (i == (num - 1)) |
| 993 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 994 | rem, fifo_size * i); |
| 995 | else |
| 996 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 997 | size, fifo_size * i); |
| 998 | } |
| 999 | |
| 1000 | sg = priv->sg_tx_p; |
| 1001 | nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1002 | if (!nent) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1003 | dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1004 | return 0; |
| 1005 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1006 | priv->nent = nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1007 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1008 | for (i = 0; i < nent; i++, sg++) { |
| 1009 | sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + |
| 1010 | fifo_size * i; |
| 1011 | sg_dma_address(sg) = (sg_dma_address(sg) & |
| 1012 | ~(UART_XMIT_SIZE - 1)) + sg->offset; |
| 1013 | if (i == (nent - 1)) |
| 1014 | sg_dma_len(sg) = rem; |
| 1015 | else |
| 1016 | sg_dma_len(sg) = size; |
| 1017 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1018 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 1019 | desc = dmaengine_prep_slave_sg(priv->chan_tx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1020 | priv->sg_tx_p, nent, DMA_MEM_TO_DEV, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1021 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1022 | if (!desc) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1023 | dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", |
| 1024 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1025 | return 0; |
| 1026 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1027 | dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1028 | priv->desc_tx = desc; |
| 1029 | desc->callback = pch_dma_tx_complete; |
| 1030 | desc->callback_param = priv; |
| 1031 | |
| 1032 | desc->tx_submit(desc); |
| 1033 | |
| 1034 | dma_async_issue_pending(priv->chan_tx); |
| 1035 | |
| 1036 | return PCH_UART_HANDLED_TX_INT; |
| 1037 | } |
| 1038 | |
| 1039 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) |
| 1040 | { |
| 1041 | u8 fcr = ioread8(priv->membase + UART_FCR); |
| 1042 | |
| 1043 | /* Reset FIFO */ |
| 1044 | fcr |= UART_FCR_CLEAR_RCVR; |
| 1045 | iowrite8(fcr, priv->membase + UART_FCR); |
| 1046 | |
| 1047 | if (lsr & PCH_UART_LSR_ERR) |
| 1048 | dev_err(&priv->pdev->dev, "Error data in FIFO\n"); |
| 1049 | |
| 1050 | if (lsr & UART_LSR_FE) |
| 1051 | dev_err(&priv->pdev->dev, "Framing Error\n"); |
| 1052 | |
| 1053 | if (lsr & UART_LSR_PE) |
| 1054 | dev_err(&priv->pdev->dev, "Parity Error\n"); |
| 1055 | |
| 1056 | if (lsr & UART_LSR_OE) |
| 1057 | dev_err(&priv->pdev->dev, "Overrun Error\n"); |
| 1058 | } |
| 1059 | |
| 1060 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) |
| 1061 | { |
| 1062 | struct eg20t_port *priv = dev_id; |
| 1063 | unsigned int handled; |
| 1064 | u8 lsr; |
| 1065 | int ret = 0; |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 1066 | unsigned char iid; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1067 | unsigned long flags; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1068 | int next = 1; |
| 1069 | u8 msr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1070 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1071 | spin_lock_irqsave(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1072 | handled = 0; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1073 | while (next) { |
| 1074 | iid = pch_uart_hal_get_iid(priv); |
| 1075 | if (iid & PCH_UART_IIR_IP) /* No Interrupt */ |
| 1076 | break; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1077 | switch (iid) { |
| 1078 | case PCH_UART_IID_RLS: /* Receiver Line Status */ |
| 1079 | lsr = pch_uart_hal_get_line_status(priv); |
| 1080 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | |
| 1081 | UART_LSR_PE | UART_LSR_OE)) { |
| 1082 | pch_uart_err_ir(priv, lsr); |
| 1083 | ret = PCH_UART_HANDLED_RX_ERR_INT; |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 1084 | } else { |
| 1085 | ret = PCH_UART_HANDLED_LS_INT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1086 | } |
| 1087 | break; |
| 1088 | case PCH_UART_IID_RDR: /* Received Data Ready */ |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1089 | if (priv->use_dma) { |
| 1090 | pch_uart_hal_disable_interrupt(priv, |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1091 | PCH_UART_HAL_RX_INT | |
| 1092 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1093 | ret = dma_handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1094 | if (!ret) |
| 1095 | pch_uart_hal_enable_interrupt(priv, |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1096 | PCH_UART_HAL_RX_INT | |
| 1097 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1098 | } else { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1099 | ret = handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1100 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1101 | break; |
| 1102 | case PCH_UART_IID_RDR_TO: /* Received Data Ready |
| 1103 | (FIFO Timeout) */ |
| 1104 | ret = handle_rx_to(priv); |
| 1105 | break; |
| 1106 | case PCH_UART_IID_THRE: /* Transmitter Holding Register |
| 1107 | Empty */ |
| 1108 | if (priv->use_dma) |
| 1109 | ret = dma_handle_tx(priv); |
| 1110 | else |
| 1111 | ret = handle_tx(priv); |
| 1112 | break; |
| 1113 | case PCH_UART_IID_MS: /* Modem Status */ |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1114 | msr = pch_uart_hal_get_modem(priv); |
| 1115 | next = 0; /* MS ir prioirty is the lowest. So, MS ir |
| 1116 | means final interrupt */ |
| 1117 | if ((msr & UART_MSR_ANY_DELTA) == 0) |
| 1118 | break; |
| 1119 | ret |= PCH_UART_HANDLED_MS_INT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1120 | break; |
| 1121 | default: /* Never junp to this label */ |
Tomoya MORINAGA | b23954a3 | 2012-03-26 14:43:02 +0900 | [diff] [blame] | 1122 | dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1123 | iid, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1124 | ret = -1; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1125 | next = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1126 | break; |
| 1127 | } |
| 1128 | handled |= (unsigned int)ret; |
| 1129 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1130 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1131 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1132 | return IRQ_RETVAL(handled); |
| 1133 | } |
| 1134 | |
| 1135 | /* This function tests whether the transmitter fifo and shifter for the port |
| 1136 | described by 'port' is empty. */ |
| 1137 | static unsigned int pch_uart_tx_empty(struct uart_port *port) |
| 1138 | { |
| 1139 | struct eg20t_port *priv; |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1140 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1141 | priv = container_of(port, struct eg20t_port, port); |
| 1142 | if (priv->tx_empty) |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1143 | return TIOCSER_TEMT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1144 | else |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1145 | return 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1146 | } |
| 1147 | |
| 1148 | /* Returns the current state of modem control inputs. */ |
| 1149 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) |
| 1150 | { |
| 1151 | struct eg20t_port *priv; |
| 1152 | u8 modem; |
| 1153 | unsigned int ret = 0; |
| 1154 | |
| 1155 | priv = container_of(port, struct eg20t_port, port); |
| 1156 | modem = pch_uart_hal_get_modem(priv); |
| 1157 | |
| 1158 | if (modem & UART_MSR_DCD) |
| 1159 | ret |= TIOCM_CAR; |
| 1160 | |
| 1161 | if (modem & UART_MSR_RI) |
| 1162 | ret |= TIOCM_RNG; |
| 1163 | |
| 1164 | if (modem & UART_MSR_DSR) |
| 1165 | ret |= TIOCM_DSR; |
| 1166 | |
| 1167 | if (modem & UART_MSR_CTS) |
| 1168 | ret |= TIOCM_CTS; |
| 1169 | |
| 1170 | return ret; |
| 1171 | } |
| 1172 | |
| 1173 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 1174 | { |
| 1175 | u32 mcr = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1176 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); |
| 1177 | |
| 1178 | if (mctrl & TIOCM_DTR) |
| 1179 | mcr |= UART_MCR_DTR; |
| 1180 | if (mctrl & TIOCM_RTS) |
| 1181 | mcr |= UART_MCR_RTS; |
| 1182 | if (mctrl & TIOCM_LOOP) |
| 1183 | mcr |= UART_MCR_LOOP; |
| 1184 | |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 1185 | if (priv->mcr & UART_MCR_AFE) |
| 1186 | mcr |= UART_MCR_AFE; |
| 1187 | |
| 1188 | if (mctrl) |
| 1189 | iowrite8(mcr, priv->membase + UART_MCR); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1190 | } |
| 1191 | |
| 1192 | static void pch_uart_stop_tx(struct uart_port *port) |
| 1193 | { |
| 1194 | struct eg20t_port *priv; |
| 1195 | priv = container_of(port, struct eg20t_port, port); |
| 1196 | priv->start_tx = 0; |
| 1197 | priv->tx_dma_use = 0; |
| 1198 | } |
| 1199 | |
| 1200 | static void pch_uart_start_tx(struct uart_port *port) |
| 1201 | { |
| 1202 | struct eg20t_port *priv; |
| 1203 | |
| 1204 | priv = container_of(port, struct eg20t_port, port); |
| 1205 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1206 | if (priv->use_dma) { |
| 1207 | if (priv->tx_dma_use) { |
| 1208 | dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", |
| 1209 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1210 | return; |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1211 | } |
| 1212 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1213 | |
| 1214 | priv->start_tx = 1; |
| 1215 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 1216 | } |
| 1217 | |
| 1218 | static void pch_uart_stop_rx(struct uart_port *port) |
| 1219 | { |
| 1220 | struct eg20t_port *priv; |
| 1221 | priv = container_of(port, struct eg20t_port, port); |
| 1222 | priv->start_rx = 0; |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1223 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 1224 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1225 | } |
| 1226 | |
| 1227 | /* Enable the modem status interrupts. */ |
| 1228 | static void pch_uart_enable_ms(struct uart_port *port) |
| 1229 | { |
| 1230 | struct eg20t_port *priv; |
| 1231 | priv = container_of(port, struct eg20t_port, port); |
| 1232 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); |
| 1233 | } |
| 1234 | |
| 1235 | /* Control the transmission of a break signal. */ |
| 1236 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) |
| 1237 | { |
| 1238 | struct eg20t_port *priv; |
| 1239 | unsigned long flags; |
| 1240 | |
| 1241 | priv = container_of(port, struct eg20t_port, port); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1242 | spin_lock_irqsave(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1243 | pch_uart_hal_set_break(priv, ctl); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1244 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1245 | } |
| 1246 | |
| 1247 | /* Grab any interrupt resources and initialise any low level driver state. */ |
| 1248 | static int pch_uart_startup(struct uart_port *port) |
| 1249 | { |
| 1250 | struct eg20t_port *priv; |
| 1251 | int ret; |
| 1252 | int fifo_size; |
| 1253 | int trigger_level; |
| 1254 | |
| 1255 | priv = container_of(port, struct eg20t_port, port); |
| 1256 | priv->tx_empty = 1; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1257 | |
| 1258 | if (port->uartclk) |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 1259 | priv->uartclk = port->uartclk; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1260 | else |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 1261 | port->uartclk = priv->uartclk; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1262 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1263 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1264 | ret = pch_uart_hal_set_line(priv, default_baud, |
| 1265 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, |
| 1266 | PCH_UART_HAL_STB1); |
| 1267 | if (ret) |
| 1268 | return ret; |
| 1269 | |
| 1270 | switch (priv->fifo_size) { |
| 1271 | case 256: |
| 1272 | fifo_size = PCH_UART_HAL_FIFO256; |
| 1273 | break; |
| 1274 | case 64: |
| 1275 | fifo_size = PCH_UART_HAL_FIFO64; |
| 1276 | break; |
| 1277 | case 16: |
| 1278 | fifo_size = PCH_UART_HAL_FIFO16; |
Alan Cox | 669bd45 | 2012-07-02 18:51:38 +0100 | [diff] [blame] | 1279 | break; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1280 | case 1: |
| 1281 | default: |
| 1282 | fifo_size = PCH_UART_HAL_FIFO_DIS; |
| 1283 | break; |
| 1284 | } |
| 1285 | |
| 1286 | switch (priv->trigger) { |
| 1287 | case PCH_UART_HAL_TRIGGER1: |
| 1288 | trigger_level = 1; |
| 1289 | break; |
| 1290 | case PCH_UART_HAL_TRIGGER_L: |
| 1291 | trigger_level = priv->fifo_size / 4; |
| 1292 | break; |
| 1293 | case PCH_UART_HAL_TRIGGER_M: |
| 1294 | trigger_level = priv->fifo_size / 2; |
| 1295 | break; |
| 1296 | case PCH_UART_HAL_TRIGGER_H: |
| 1297 | default: |
| 1298 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); |
| 1299 | break; |
| 1300 | } |
| 1301 | |
| 1302 | priv->trigger_level = trigger_level; |
| 1303 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1304 | fifo_size, priv->trigger); |
| 1305 | if (ret < 0) |
| 1306 | return ret; |
| 1307 | |
| 1308 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, |
| 1309 | KBUILD_MODNAME, priv); |
| 1310 | if (ret < 0) |
| 1311 | return ret; |
| 1312 | |
| 1313 | if (priv->use_dma) |
| 1314 | pch_request_dma(port); |
| 1315 | |
| 1316 | priv->start_rx = 1; |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1317 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 1318 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1319 | uart_update_timeout(port, CS8, default_baud); |
| 1320 | |
| 1321 | return 0; |
| 1322 | } |
| 1323 | |
| 1324 | static void pch_uart_shutdown(struct uart_port *port) |
| 1325 | { |
| 1326 | struct eg20t_port *priv; |
| 1327 | int ret; |
| 1328 | |
| 1329 | priv = container_of(port, struct eg20t_port, port); |
| 1330 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1331 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); |
| 1332 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1333 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); |
| 1334 | if (ret) |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1335 | dev_err(priv->port.dev, |
| 1336 | "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1337 | |
Tomoya MORINAGA | 90f04c2 | 2011-11-11 10:55:27 +0900 | [diff] [blame] | 1338 | pch_free_dma(port); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1339 | |
| 1340 | free_irq(priv->port.irq, priv); |
| 1341 | } |
| 1342 | |
| 1343 | /* Change the port parameters, including word length, parity, stop |
| 1344 | *bits. Update read_status_mask and ignore_status_mask to indicate |
| 1345 | *the types of events we are interested in receiving. */ |
| 1346 | static void pch_uart_set_termios(struct uart_port *port, |
| 1347 | struct ktermios *termios, struct ktermios *old) |
| 1348 | { |
| 1349 | int baud; |
| 1350 | int rtn; |
| 1351 | unsigned int parity, bits, stb; |
| 1352 | struct eg20t_port *priv; |
| 1353 | unsigned long flags; |
| 1354 | |
| 1355 | priv = container_of(port, struct eg20t_port, port); |
| 1356 | switch (termios->c_cflag & CSIZE) { |
| 1357 | case CS5: |
| 1358 | bits = PCH_UART_HAL_5BIT; |
| 1359 | break; |
| 1360 | case CS6: |
| 1361 | bits = PCH_UART_HAL_6BIT; |
| 1362 | break; |
| 1363 | case CS7: |
| 1364 | bits = PCH_UART_HAL_7BIT; |
| 1365 | break; |
| 1366 | default: /* CS8 */ |
| 1367 | bits = PCH_UART_HAL_8BIT; |
| 1368 | break; |
| 1369 | } |
| 1370 | if (termios->c_cflag & CSTOPB) |
| 1371 | stb = PCH_UART_HAL_STB2; |
| 1372 | else |
| 1373 | stb = PCH_UART_HAL_STB1; |
| 1374 | |
| 1375 | if (termios->c_cflag & PARENB) { |
Tomoya MORINAGA | 2fc39ae | 2012-07-06 17:19:43 +0900 | [diff] [blame] | 1376 | if (termios->c_cflag & PARODD) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1377 | parity = PCH_UART_HAL_PARITY_ODD; |
| 1378 | else |
| 1379 | parity = PCH_UART_HAL_PARITY_EVEN; |
| 1380 | |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1381 | } else |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1382 | parity = PCH_UART_HAL_PARITY_NONE; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 1383 | |
| 1384 | /* Only UART0 has auto hardware flow function */ |
| 1385 | if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) |
| 1386 | priv->mcr |= UART_MCR_AFE; |
| 1387 | else |
| 1388 | priv->mcr &= ~UART_MCR_AFE; |
| 1389 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1390 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
| 1391 | |
| 1392 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
| 1393 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1394 | spin_lock_irqsave(&priv->lock, flags); |
| 1395 | spin_lock(&port->lock); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1396 | |
| 1397 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1398 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); |
| 1399 | if (rtn) |
| 1400 | goto out; |
| 1401 | |
Tomoya MORINAGA | a1d7cfe | 2011-10-27 15:45:18 +0900 | [diff] [blame] | 1402 | pch_uart_set_mctrl(&priv->port, priv->port.mctrl); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1403 | /* Don't rewrite B0 */ |
| 1404 | if (tty_termios_baud_rate(termios)) |
| 1405 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 1406 | |
| 1407 | out: |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1408 | spin_unlock(&port->lock); |
| 1409 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1410 | } |
| 1411 | |
| 1412 | static const char *pch_uart_type(struct uart_port *port) |
| 1413 | { |
| 1414 | return KBUILD_MODNAME; |
| 1415 | } |
| 1416 | |
| 1417 | static void pch_uart_release_port(struct uart_port *port) |
| 1418 | { |
| 1419 | struct eg20t_port *priv; |
| 1420 | |
| 1421 | priv = container_of(port, struct eg20t_port, port); |
| 1422 | pci_iounmap(priv->pdev, priv->membase); |
| 1423 | pci_release_regions(priv->pdev); |
| 1424 | } |
| 1425 | |
| 1426 | static int pch_uart_request_port(struct uart_port *port) |
| 1427 | { |
| 1428 | struct eg20t_port *priv; |
| 1429 | int ret; |
| 1430 | void __iomem *membase; |
| 1431 | |
| 1432 | priv = container_of(port, struct eg20t_port, port); |
| 1433 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); |
| 1434 | if (ret < 0) |
| 1435 | return -EBUSY; |
| 1436 | |
| 1437 | membase = pci_iomap(priv->pdev, 1, 0); |
| 1438 | if (!membase) { |
| 1439 | pci_release_regions(priv->pdev); |
| 1440 | return -EBUSY; |
| 1441 | } |
| 1442 | priv->membase = port->membase = membase; |
| 1443 | |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | static void pch_uart_config_port(struct uart_port *port, int type) |
| 1448 | { |
| 1449 | struct eg20t_port *priv; |
| 1450 | |
| 1451 | priv = container_of(port, struct eg20t_port, port); |
| 1452 | if (type & UART_CONFIG_TYPE) { |
| 1453 | port->type = priv->port_type; |
| 1454 | pch_uart_request_port(port); |
| 1455 | } |
| 1456 | } |
| 1457 | |
| 1458 | static int pch_uart_verify_port(struct uart_port *port, |
| 1459 | struct serial_struct *serinfo) |
| 1460 | { |
| 1461 | struct eg20t_port *priv; |
| 1462 | |
| 1463 | priv = container_of(port, struct eg20t_port, port); |
| 1464 | if (serinfo->flags & UPF_LOW_LATENCY) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1465 | dev_info(priv->port.dev, |
| 1466 | "PCH UART : Use PIO Mode (without DMA)\n"); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1467 | priv->use_dma = 0; |
| 1468 | serinfo->flags &= ~UPF_LOW_LATENCY; |
| 1469 | } else { |
| 1470 | #ifndef CONFIG_PCH_DMA |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1471 | dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", |
| 1472 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1473 | return -EOPNOTSUPP; |
| 1474 | #endif |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1475 | dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); |
Tomoya MORINAGA | af6d17c | 2012-04-12 10:47:50 +0900 | [diff] [blame] | 1476 | if (!priv->use_dma) |
| 1477 | pch_request_dma(port); |
| 1478 | priv->use_dma = 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1479 | } |
| 1480 | |
| 1481 | return 0; |
| 1482 | } |
| 1483 | |
| 1484 | static struct uart_ops pch_uart_ops = { |
| 1485 | .tx_empty = pch_uart_tx_empty, |
| 1486 | .set_mctrl = pch_uart_set_mctrl, |
| 1487 | .get_mctrl = pch_uart_get_mctrl, |
| 1488 | .stop_tx = pch_uart_stop_tx, |
| 1489 | .start_tx = pch_uart_start_tx, |
| 1490 | .stop_rx = pch_uart_stop_rx, |
| 1491 | .enable_ms = pch_uart_enable_ms, |
| 1492 | .break_ctl = pch_uart_break_ctl, |
| 1493 | .startup = pch_uart_startup, |
| 1494 | .shutdown = pch_uart_shutdown, |
| 1495 | .set_termios = pch_uart_set_termios, |
| 1496 | /* .pm = pch_uart_pm, Not supported yet */ |
| 1497 | /* .set_wake = pch_uart_set_wake, Not supported yet */ |
| 1498 | .type = pch_uart_type, |
| 1499 | .release_port = pch_uart_release_port, |
| 1500 | .request_port = pch_uart_request_port, |
| 1501 | .config_port = pch_uart_config_port, |
| 1502 | .verify_port = pch_uart_verify_port |
| 1503 | }; |
| 1504 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1505 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1506 | |
| 1507 | /* |
| 1508 | * Wait for transmitter & holding register to empty |
| 1509 | */ |
| 1510 | static void wait_for_xmitr(struct eg20t_port *up, int bits) |
| 1511 | { |
| 1512 | unsigned int status, tmout = 10000; |
| 1513 | |
| 1514 | /* Wait up to 10ms for the character(s) to be sent. */ |
| 1515 | for (;;) { |
| 1516 | status = ioread8(up->membase + UART_LSR); |
| 1517 | |
| 1518 | if ((status & bits) == bits) |
| 1519 | break; |
| 1520 | if (--tmout == 0) |
| 1521 | break; |
| 1522 | udelay(1); |
| 1523 | } |
| 1524 | |
| 1525 | /* Wait up to 1s for flow control if necessary */ |
| 1526 | if (up->port.flags & UPF_CONS_FLOW) { |
| 1527 | unsigned int tmout; |
| 1528 | for (tmout = 1000000; tmout; tmout--) { |
| 1529 | unsigned int msr = ioread8(up->membase + UART_MSR); |
| 1530 | if (msr & UART_MSR_CTS) |
| 1531 | break; |
| 1532 | udelay(1); |
| 1533 | touch_nmi_watchdog(); |
| 1534 | } |
| 1535 | } |
| 1536 | } |
| 1537 | |
| 1538 | static void pch_console_putchar(struct uart_port *port, int ch) |
| 1539 | { |
| 1540 | struct eg20t_port *priv = |
| 1541 | container_of(port, struct eg20t_port, port); |
| 1542 | |
| 1543 | wait_for_xmitr(priv, UART_LSR_THRE); |
| 1544 | iowrite8(ch, priv->membase + PCH_UART_THR); |
| 1545 | } |
| 1546 | |
| 1547 | /* |
| 1548 | * Print a string to the serial port trying not to disturb |
| 1549 | * any possible real use of the port... |
| 1550 | * |
| 1551 | * The console_lock must be held when we get here. |
| 1552 | */ |
| 1553 | static void |
| 1554 | pch_console_write(struct console *co, const char *s, unsigned int count) |
| 1555 | { |
| 1556 | struct eg20t_port *priv; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1557 | unsigned long flags; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1558 | int priv_locked = 1; |
| 1559 | int port_locked = 1; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1560 | u8 ier; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1561 | |
| 1562 | priv = pch_uart_ports[co->index]; |
| 1563 | |
| 1564 | touch_nmi_watchdog(); |
| 1565 | |
| 1566 | local_irq_save(flags); |
| 1567 | if (priv->port.sysrq) { |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1568 | spin_lock(&priv->lock); |
| 1569 | /* serial8250_handle_port() already took the port lock */ |
| 1570 | port_locked = 0; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1571 | } else if (oops_in_progress) { |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1572 | priv_locked = spin_trylock(&priv->lock); |
| 1573 | port_locked = spin_trylock(&priv->port.lock); |
| 1574 | } else { |
| 1575 | spin_lock(&priv->lock); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1576 | spin_lock(&priv->port.lock); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1577 | } |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1578 | |
| 1579 | /* |
| 1580 | * First save the IER then disable the interrupts |
| 1581 | */ |
| 1582 | ier = ioread8(priv->membase + UART_IER); |
| 1583 | |
| 1584 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1585 | |
| 1586 | uart_console_write(&priv->port, s, count, pch_console_putchar); |
| 1587 | |
| 1588 | /* |
| 1589 | * Finally, wait for transmitter to become empty |
| 1590 | * and restore the IER |
| 1591 | */ |
| 1592 | wait_for_xmitr(priv, BOTH_EMPTY); |
| 1593 | iowrite8(ier, priv->membase + UART_IER); |
| 1594 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1595 | if (port_locked) |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1596 | spin_unlock(&priv->port.lock); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1597 | if (priv_locked) |
| 1598 | spin_unlock(&priv->lock); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1599 | local_irq_restore(flags); |
| 1600 | } |
| 1601 | |
| 1602 | static int __init pch_console_setup(struct console *co, char *options) |
| 1603 | { |
| 1604 | struct uart_port *port; |
Darren Hart | 7ce9251 | 2012-03-09 09:51:51 -0800 | [diff] [blame] | 1605 | int baud = default_baud; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1606 | int bits = 8; |
| 1607 | int parity = 'n'; |
| 1608 | int flow = 'n'; |
| 1609 | |
| 1610 | /* |
| 1611 | * Check whether an invalid uart number has been specified, and |
| 1612 | * if so, search for the first available port that does have |
| 1613 | * console support. |
| 1614 | */ |
| 1615 | if (co->index >= PCH_UART_NR) |
| 1616 | co->index = 0; |
| 1617 | port = &pch_uart_ports[co->index]->port; |
| 1618 | |
| 1619 | if (!port || (!port->iobase && !port->membase)) |
| 1620 | return -ENODEV; |
| 1621 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1622 | port->uartclk = pch_uart_get_uartclk(); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1623 | |
| 1624 | if (options) |
| 1625 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 1626 | |
| 1627 | return uart_set_options(port, co, baud, parity, bits, flow); |
| 1628 | } |
| 1629 | |
| 1630 | static struct uart_driver pch_uart_driver; |
| 1631 | |
| 1632 | static struct console pch_console = { |
| 1633 | .name = PCH_UART_DRIVER_DEVICE, |
| 1634 | .write = pch_console_write, |
| 1635 | .device = uart_console_device, |
| 1636 | .setup = pch_console_setup, |
| 1637 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
| 1638 | .index = -1, |
| 1639 | .data = &pch_uart_driver, |
| 1640 | }; |
| 1641 | |
| 1642 | #define PCH_CONSOLE (&pch_console) |
| 1643 | #else |
| 1644 | #define PCH_CONSOLE NULL |
| 1645 | #endif |
| 1646 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1647 | static struct uart_driver pch_uart_driver = { |
| 1648 | .owner = THIS_MODULE, |
| 1649 | .driver_name = KBUILD_MODNAME, |
| 1650 | .dev_name = PCH_UART_DRIVER_DEVICE, |
| 1651 | .major = 0, |
| 1652 | .minor = 0, |
| 1653 | .nr = PCH_UART_NR, |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1654 | .cons = PCH_CONSOLE, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1655 | }; |
| 1656 | |
| 1657 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1658 | const struct pci_device_id *id) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1659 | { |
| 1660 | struct eg20t_port *priv; |
| 1661 | int ret; |
| 1662 | unsigned int iobase; |
| 1663 | unsigned int mapbase; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1664 | unsigned char *rxbuf; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1665 | int fifosize; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1666 | int port_type; |
| 1667 | struct pch_uart_driver_data *board; |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1668 | char name[32]; /* for debugfs file name */ |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1669 | |
| 1670 | board = &drv_dat[id->driver_data]; |
| 1671 | port_type = board->port_type; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1672 | |
| 1673 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); |
| 1674 | if (priv == NULL) |
| 1675 | goto init_port_alloc_err; |
| 1676 | |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1677 | rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1678 | if (!rxbuf) |
| 1679 | goto init_port_free_txbuf; |
| 1680 | |
| 1681 | switch (port_type) { |
| 1682 | case PORT_UNKNOWN: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1683 | fifosize = 256; /* EG20T/ML7213: UART0 */ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1684 | break; |
| 1685 | case PORT_8250: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1686 | fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1687 | break; |
| 1688 | default: |
| 1689 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); |
| 1690 | goto init_port_hal_free; |
| 1691 | } |
| 1692 | |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1693 | pci_enable_msi(pdev); |
Tomoya MORINAGA | 867c902 | 2012-04-02 14:36:22 +0900 | [diff] [blame] | 1694 | pci_set_master(pdev); |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1695 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1696 | spin_lock_init(&priv->lock); |
| 1697 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1698 | iobase = pci_resource_start(pdev, 0); |
| 1699 | mapbase = pci_resource_start(pdev, 1); |
| 1700 | priv->mapbase = mapbase; |
| 1701 | priv->iobase = iobase; |
| 1702 | priv->pdev = pdev; |
| 1703 | priv->tx_empty = 1; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1704 | priv->rxbuf.buf = rxbuf; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1705 | priv->rxbuf.size = PAGE_SIZE; |
| 1706 | |
| 1707 | priv->fifo_size = fifosize; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1708 | priv->uartclk = pch_uart_get_uartclk(); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1709 | priv->port_type = PORT_MAX_8250 + port_type + 1; |
| 1710 | priv->port.dev = &pdev->dev; |
| 1711 | priv->port.iobase = iobase; |
| 1712 | priv->port.membase = NULL; |
| 1713 | priv->port.mapbase = mapbase; |
| 1714 | priv->port.irq = pdev->irq; |
| 1715 | priv->port.iotype = UPIO_PORT; |
| 1716 | priv->port.ops = &pch_uart_ops; |
| 1717 | priv->port.flags = UPF_BOOT_AUTOCONF; |
| 1718 | priv->port.fifosize = fifosize; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1719 | priv->port.line = board->line_no; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1720 | priv->trigger = PCH_UART_HAL_TRIGGER_M; |
| 1721 | |
Tomoya MORINAGA | 7e46132 | 2011-02-23 10:03:13 +0900 | [diff] [blame] | 1722 | spin_lock_init(&priv->port.lock); |
| 1723 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1724 | pci_set_drvdata(pdev, priv); |
Feng Tang | 6f56d0f | 2012-02-06 17:24:45 +0800 | [diff] [blame] | 1725 | priv->trigger_level = 1; |
| 1726 | priv->fcr = 0; |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1727 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1728 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1729 | pch_uart_ports[board->line_no] = priv; |
| 1730 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1731 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); |
| 1732 | if (ret < 0) |
| 1733 | goto init_port_hal_free; |
| 1734 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1735 | #ifdef CONFIG_DEBUG_FS |
| 1736 | snprintf(name, sizeof(name), "uart%d_regs", board->line_no); |
| 1737 | priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, |
| 1738 | NULL, priv, &port_regs_ops); |
| 1739 | #endif |
| 1740 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1741 | return priv; |
| 1742 | |
| 1743 | init_port_hal_free: |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1744 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1745 | pch_uart_ports[board->line_no] = NULL; |
| 1746 | #endif |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1747 | free_page((unsigned long)rxbuf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1748 | init_port_free_txbuf: |
| 1749 | kfree(priv); |
| 1750 | init_port_alloc_err: |
| 1751 | |
| 1752 | return NULL; |
| 1753 | } |
| 1754 | |
| 1755 | static void pch_uart_exit_port(struct eg20t_port *priv) |
| 1756 | { |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1757 | |
| 1758 | #ifdef CONFIG_DEBUG_FS |
| 1759 | if (priv->debugfs) |
| 1760 | debugfs_remove(priv->debugfs); |
| 1761 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1762 | uart_remove_one_port(&pch_uart_driver, &priv->port); |
| 1763 | pci_set_drvdata(priv->pdev, NULL); |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1764 | free_page((unsigned long)priv->rxbuf.buf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1765 | } |
| 1766 | |
| 1767 | static void pch_uart_pci_remove(struct pci_dev *pdev) |
| 1768 | { |
Feng Tang | 6f56d0f | 2012-02-06 17:24:45 +0800 | [diff] [blame] | 1769 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1770 | |
| 1771 | pci_disable_msi(pdev); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1772 | |
| 1773 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1774 | pch_uart_ports[priv->port.line] = NULL; |
| 1775 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1776 | pch_uart_exit_port(priv); |
| 1777 | pci_disable_device(pdev); |
| 1778 | kfree(priv); |
| 1779 | return; |
| 1780 | } |
| 1781 | #ifdef CONFIG_PM |
| 1782 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1783 | { |
| 1784 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1785 | |
| 1786 | uart_suspend_port(&pch_uart_driver, &priv->port); |
| 1787 | |
| 1788 | pci_save_state(pdev); |
| 1789 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 1790 | return 0; |
| 1791 | } |
| 1792 | |
| 1793 | static int pch_uart_pci_resume(struct pci_dev *pdev) |
| 1794 | { |
| 1795 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1796 | int ret; |
| 1797 | |
| 1798 | pci_set_power_state(pdev, PCI_D0); |
| 1799 | pci_restore_state(pdev); |
| 1800 | |
| 1801 | ret = pci_enable_device(pdev); |
| 1802 | if (ret) { |
| 1803 | dev_err(&pdev->dev, |
| 1804 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); |
| 1805 | return ret; |
| 1806 | } |
| 1807 | |
| 1808 | uart_resume_port(&pch_uart_driver, &priv->port); |
| 1809 | |
| 1810 | return 0; |
| 1811 | } |
| 1812 | #else |
| 1813 | #define pch_uart_pci_suspend NULL |
| 1814 | #define pch_uart_pci_resume NULL |
| 1815 | #endif |
| 1816 | |
| 1817 | static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { |
| 1818 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1819 | .driver_data = pch_et20t_uart0}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1820 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1821 | .driver_data = pch_et20t_uart1}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1822 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1823 | .driver_data = pch_et20t_uart2}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1824 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1825 | .driver_data = pch_et20t_uart3}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1826 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1827 | .driver_data = pch_ml7213_uart0}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1828 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1829 | .driver_data = pch_ml7213_uart1}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1830 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1831 | .driver_data = pch_ml7213_uart2}, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 1832 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), |
| 1833 | .driver_data = pch_ml7223_uart0}, |
| 1834 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), |
| 1835 | .driver_data = pch_ml7223_uart1}, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 1836 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), |
| 1837 | .driver_data = pch_ml7831_uart0}, |
| 1838 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), |
| 1839 | .driver_data = pch_ml7831_uart1}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1840 | {0,}, |
| 1841 | }; |
| 1842 | |
Bill Pemberton | 9671f09 | 2012-11-19 13:21:50 -0500 | [diff] [blame] | 1843 | static int pch_uart_pci_probe(struct pci_dev *pdev, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1844 | const struct pci_device_id *id) |
| 1845 | { |
| 1846 | int ret; |
| 1847 | struct eg20t_port *priv; |
| 1848 | |
| 1849 | ret = pci_enable_device(pdev); |
| 1850 | if (ret < 0) |
| 1851 | goto probe_error; |
| 1852 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1853 | priv = pch_uart_init_port(pdev, id); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1854 | if (!priv) { |
| 1855 | ret = -EBUSY; |
| 1856 | goto probe_disable_device; |
| 1857 | } |
| 1858 | pci_set_drvdata(pdev, priv); |
| 1859 | |
| 1860 | return ret; |
| 1861 | |
| 1862 | probe_disable_device: |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1863 | pci_disable_msi(pdev); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1864 | pci_disable_device(pdev); |
| 1865 | probe_error: |
| 1866 | return ret; |
| 1867 | } |
| 1868 | |
| 1869 | static struct pci_driver pch_uart_pci_driver = { |
| 1870 | .name = "pch_uart", |
| 1871 | .id_table = pch_uart_pci_id, |
| 1872 | .probe = pch_uart_pci_probe, |
Bill Pemberton | 2d47b71 | 2012-11-19 13:21:34 -0500 | [diff] [blame] | 1873 | .remove = pch_uart_pci_remove, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1874 | .suspend = pch_uart_pci_suspend, |
| 1875 | .resume = pch_uart_pci_resume, |
| 1876 | }; |
| 1877 | |
| 1878 | static int __init pch_uart_module_init(void) |
| 1879 | { |
| 1880 | int ret; |
| 1881 | |
| 1882 | /* register as UART driver */ |
| 1883 | ret = uart_register_driver(&pch_uart_driver); |
| 1884 | if (ret < 0) |
| 1885 | return ret; |
| 1886 | |
| 1887 | /* register as PCI driver */ |
| 1888 | ret = pci_register_driver(&pch_uart_pci_driver); |
| 1889 | if (ret < 0) |
| 1890 | uart_unregister_driver(&pch_uart_driver); |
| 1891 | |
| 1892 | return ret; |
| 1893 | } |
| 1894 | module_init(pch_uart_module_init); |
| 1895 | |
| 1896 | static void __exit pch_uart_module_exit(void) |
| 1897 | { |
| 1898 | pci_unregister_driver(&pch_uart_pci_driver); |
| 1899 | uart_unregister_driver(&pch_uart_driver); |
| 1900 | } |
| 1901 | module_exit(pch_uart_module_exit); |
| 1902 | |
| 1903 | MODULE_LICENSE("GPL v2"); |
| 1904 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); |
| 1905 | module_param(default_baud, uint, S_IRUGO); |
Darren Hart | a46f553 | 2012-03-09 09:51:52 -0800 | [diff] [blame] | 1906 | MODULE_PARM_DESC(default_baud, |
| 1907 | "Default BAUD for initial driver state and console (default 9600)"); |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 1908 | module_param(user_uartclk, uint, S_IRUGO); |
Darren Hart | a46f553 | 2012-03-09 09:51:52 -0800 | [diff] [blame] | 1909 | MODULE_PARM_DESC(user_uartclk, |
| 1910 | "Override UART default or board specific UART clock"); |