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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070016#include <linux/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/module.h>
18#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080019#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053020#include <linux/log2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090022#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -070024unsigned int pci_pm_d3_delay = 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
Atsushi Nemoto4516a612007-02-05 16:36:06 -080026#define DEFAULT_CARDBUS_IO_SIZE (256)
27#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
28/* pci=cbmemsize=nnM,cbiosize=nn can override this */
29unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
30unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
31
Linus Torvalds1da177e2005-04-16 15:20:36 -070032/**
33 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
34 * @bus: pointer to PCI bus structure to search
35 *
36 * Given a PCI bus, returns the highest PCI bus number present in the set
37 * including the given PCI bus and its list of child PCI buses.
38 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080039unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070040{
41 struct list_head *tmp;
42 unsigned char max, n;
43
Kristen Accardib82db5c2006-01-17 16:56:56 -080044 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070045 list_for_each(tmp, &bus->children) {
46 n = pci_bus_max_busnr(pci_bus_b(tmp));
47 if(n > max)
48 max = n;
49 }
50 return max;
51}
Kristen Accardib82db5c2006-01-17 16:56:56 -080052EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Kristen Accardib82db5c2006-01-17 16:56:56 -080054#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070055/**
56 * pci_max_busnr - returns maximum PCI bus number
57 *
58 * Returns the highest PCI bus number present in the system global list of
59 * PCI buses.
60 */
61unsigned char __devinit
62pci_max_busnr(void)
63{
64 struct pci_bus *bus = NULL;
65 unsigned char max, n;
66
67 max = 0;
68 while ((bus = pci_find_next_bus(bus)) != NULL) {
69 n = pci_bus_max_busnr(bus);
70 if(n > max)
71 max = n;
72 }
73 return max;
74}
75
Adrian Bunk54c762f2005-12-22 01:08:52 +010076#endif /* 0 */
77
Michael Ellerman687d5fe2006-11-22 18:26:18 +110078#define PCI_FIND_CAP_TTL 48
79
80static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
81 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -070082{
83 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -070084
Michael Ellerman687d5fe2006-11-22 18:26:18 +110085 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -070086 pci_bus_read_config_byte(bus, devfn, pos, &pos);
87 if (pos < 0x40)
88 break;
89 pos &= ~3;
90 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
91 &id);
92 if (id == 0xff)
93 break;
94 if (id == cap)
95 return pos;
96 pos += PCI_CAP_LIST_NEXT;
97 }
98 return 0;
99}
100
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100101static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
102 u8 pos, int cap)
103{
104 int ttl = PCI_FIND_CAP_TTL;
105
106 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
107}
108
Roland Dreier24a4e372005-10-28 17:35:34 -0700109int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
110{
111 return __pci_find_next_cap(dev->bus, dev->devfn,
112 pos + PCI_CAP_LIST_NEXT, cap);
113}
114EXPORT_SYMBOL_GPL(pci_find_next_capability);
115
Michael Ellermand3bac112006-11-22 18:26:16 +1100116static int __pci_bus_find_cap_start(struct pci_bus *bus,
117 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118{
119 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
121 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
122 if (!(status & PCI_STATUS_CAP_LIST))
123 return 0;
124
125 switch (hdr_type) {
126 case PCI_HEADER_TYPE_NORMAL:
127 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100128 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100130 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 default:
132 return 0;
133 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100134
135 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136}
137
138/**
139 * pci_find_capability - query for devices' capabilities
140 * @dev: PCI device to query
141 * @cap: capability code
142 *
143 * Tell if a device supports a given PCI capability.
144 * Returns the address of the requested capability structure within the
145 * device's PCI configuration space or 0 in case the device does not
146 * support it. Possible values for @cap:
147 *
148 * %PCI_CAP_ID_PM Power Management
149 * %PCI_CAP_ID_AGP Accelerated Graphics Port
150 * %PCI_CAP_ID_VPD Vital Product Data
151 * %PCI_CAP_ID_SLOTID Slot Identification
152 * %PCI_CAP_ID_MSI Message Signalled Interrupts
153 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
154 * %PCI_CAP_ID_PCIX PCI-X
155 * %PCI_CAP_ID_EXP PCI Express
156 */
157int pci_find_capability(struct pci_dev *dev, int cap)
158{
Michael Ellermand3bac112006-11-22 18:26:16 +1100159 int pos;
160
161 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
162 if (pos)
163 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
164
165 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166}
167
168/**
169 * pci_bus_find_capability - query for devices' capabilities
170 * @bus: the PCI bus to query
171 * @devfn: PCI device to query
172 * @cap: capability code
173 *
174 * Like pci_find_capability() but works for pci devices that do not have a
175 * pci_dev structure set up yet.
176 *
177 * Returns the address of the requested capability structure within the
178 * device's PCI configuration space or 0 in case the device does not
179 * support it.
180 */
181int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
182{
Michael Ellermand3bac112006-11-22 18:26:16 +1100183 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 u8 hdr_type;
185
186 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
187
Michael Ellermand3bac112006-11-22 18:26:16 +1100188 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
189 if (pos)
190 pos = __pci_find_next_cap(bus, devfn, pos, cap);
191
192 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193}
194
195/**
196 * pci_find_ext_capability - Find an extended capability
197 * @dev: PCI device to query
198 * @cap: capability code
199 *
200 * Returns the address of the requested extended capability structure
201 * within the device's PCI configuration space or 0 if the device does
202 * not support it. Possible values for @cap:
203 *
204 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
205 * %PCI_EXT_CAP_ID_VC Virtual Channel
206 * %PCI_EXT_CAP_ID_DSN Device Serial Number
207 * %PCI_EXT_CAP_ID_PWR Power Budgeting
208 */
209int pci_find_ext_capability(struct pci_dev *dev, int cap)
210{
211 u32 header;
212 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
213 int pos = 0x100;
214
215 if (dev->cfg_size <= 256)
216 return 0;
217
218 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
219 return 0;
220
221 /*
222 * If we have no capabilities, this is indicated by cap ID,
223 * cap version and next pointer all being 0.
224 */
225 if (header == 0)
226 return 0;
227
228 while (ttl-- > 0) {
229 if (PCI_EXT_CAP_ID(header) == cap)
230 return pos;
231
232 pos = PCI_EXT_CAP_NEXT(header);
233 if (pos < 0x100)
234 break;
235
236 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
237 break;
238 }
239
240 return 0;
241}
Brice Goglin3a720d72006-05-23 06:10:01 -0400242EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100244static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
245{
246 int rc, ttl = PCI_FIND_CAP_TTL;
247 u8 cap, mask;
248
249 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
250 mask = HT_3BIT_CAP_MASK;
251 else
252 mask = HT_5BIT_CAP_MASK;
253
254 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
255 PCI_CAP_ID_HT, &ttl);
256 while (pos) {
257 rc = pci_read_config_byte(dev, pos + 3, &cap);
258 if (rc != PCIBIOS_SUCCESSFUL)
259 return 0;
260
261 if ((cap & mask) == ht_cap)
262 return pos;
263
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800264 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
265 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100266 PCI_CAP_ID_HT, &ttl);
267 }
268
269 return 0;
270}
271/**
272 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
273 * @dev: PCI device to query
274 * @pos: Position from which to continue searching
275 * @ht_cap: Hypertransport capability code
276 *
277 * To be used in conjunction with pci_find_ht_capability() to search for
278 * all capabilities matching @ht_cap. @pos should always be a value returned
279 * from pci_find_ht_capability().
280 *
281 * NB. To be 100% safe against broken PCI devices, the caller should take
282 * steps to avoid an infinite loop.
283 */
284int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
285{
286 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
287}
288EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
289
290/**
291 * pci_find_ht_capability - query a device's Hypertransport capabilities
292 * @dev: PCI device to query
293 * @ht_cap: Hypertransport capability code
294 *
295 * Tell if a device supports a given Hypertransport capability.
296 * Returns an address within the device's PCI configuration space
297 * or 0 in case the device does not support the request capability.
298 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
299 * which has a Hypertransport capability matching @ht_cap.
300 */
301int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
302{
303 int pos;
304
305 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
306 if (pos)
307 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
308
309 return pos;
310}
311EXPORT_SYMBOL_GPL(pci_find_ht_capability);
312
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313/**
314 * pci_find_parent_resource - return resource region of parent bus of given region
315 * @dev: PCI device structure contains resources to be searched
316 * @res: child resource record for which parent is sought
317 *
318 * For given resource region of given device, return the resource
319 * region of parent bus the given region is contained in or where
320 * it should be allocated from.
321 */
322struct resource *
323pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
324{
325 const struct pci_bus *bus = dev->bus;
326 int i;
327 struct resource *best = NULL;
328
329 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
330 struct resource *r = bus->resource[i];
331 if (!r)
332 continue;
333 if (res->start && !(res->start >= r->start && res->end <= r->end))
334 continue; /* Not contained */
335 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
336 continue; /* Wrong type */
337 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
338 return r; /* Exact match */
339 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
340 best = r; /* Approximating prefetchable by non-prefetchable */
341 }
342 return best;
343}
344
345/**
John W. Linville064b53db2005-07-27 10:19:44 -0400346 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
347 * @dev: PCI device to have its BARs restored
348 *
349 * Restore the BAR values for a given device, so as to make it
350 * accessible by its driver.
351 */
352void
353pci_restore_bars(struct pci_dev *dev)
354{
355 int i, numres;
356
357 switch (dev->hdr_type) {
358 case PCI_HEADER_TYPE_NORMAL:
359 numres = 6;
360 break;
361 case PCI_HEADER_TYPE_BRIDGE:
362 numres = 2;
363 break;
364 case PCI_HEADER_TYPE_CARDBUS:
365 numres = 1;
366 break;
367 default:
368 /* Should never get here, but just in case... */
369 return;
370 }
371
372 for (i = 0; i < numres; i ++)
373 pci_update_resource(dev, &dev->resource[i], i);
374}
375
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700376int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
377
John W. Linville064b53db2005-07-27 10:19:44 -0400378/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 * pci_set_power_state - Set the power state of a PCI device
380 * @dev: PCI device to be suspended
381 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
382 *
383 * Transition a device to a new power state, using the Power Management
384 * Capabilities in the device's config space.
385 *
386 * RETURN VALUE:
387 * -EINVAL if trying to enter a lower state than we're already in.
388 * 0 if we're already in the requested state.
389 * -EIO if device does not support PCI PM.
390 * 0 if we can successfully change the power state.
391 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392int
393pci_set_power_state(struct pci_dev *dev, pci_power_t state)
394{
John W. Linville064b53db2005-07-27 10:19:44 -0400395 int pm, need_restore = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 u16 pmcsr, pmc;
397
398 /* bound the state we're entering */
399 if (state > PCI_D3hot)
400 state = PCI_D3hot;
401
Pavel Macheke36c4552007-01-16 12:17:13 +0100402 /*
403 * If the device or the parent bridge can't support PCI PM, ignore
404 * the request if we're doing anything besides putting it into D0
405 * (which would only happen on boot).
406 */
407 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
408 return 0;
409
Andrew Lunncca03de2007-07-09 11:55:58 -0700410 /* find PCI PM capability in list */
411 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
412
413 /* abort if the device doesn't support PM capabilities */
414 if (!pm)
415 return -EIO;
416
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 /* Validate current state:
418 * Can enter D0 from any state, but if we can only go deeper
419 * to sleep if we're already in a low power state
420 */
Andrew Morton02669492006-03-23 01:38:34 -0800421 if (state != PCI_D0 && dev->current_state > state) {
422 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
423 __FUNCTION__, pci_name(dev), state, dev->current_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 return -EINVAL;
Andrew Morton02669492006-03-23 01:38:34 -0800425 } else if (dev->current_state == state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 return 0; /* we're already there */
427
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700430 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 printk(KERN_DEBUG
432 "PCI: %s has unsupported PM cap regs version (%u)\n",
433 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
434 return -EIO;
435 }
436
437 /* check if this device supports the desired state */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700438 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
439 return -EIO;
440 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
441 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442
John W. Linville064b53db2005-07-27 10:19:44 -0400443 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
444
John W. Linville32a36582005-09-14 09:52:42 -0400445 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 * This doesn't affect PME_Status, disables PME_En, and
447 * sets PowerState to 0.
448 */
John W. Linville32a36582005-09-14 09:52:42 -0400449 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400450 case PCI_D0:
451 case PCI_D1:
452 case PCI_D2:
453 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
454 pmcsr |= state;
455 break;
John W. Linville32a36582005-09-14 09:52:42 -0400456 case PCI_UNKNOWN: /* Boot-up */
457 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
458 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
John W. Linville064b53db2005-07-27 10:19:44 -0400459 need_restore = 1;
John W. Linville32a36582005-09-14 09:52:42 -0400460 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400461 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400462 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400463 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 }
465
466 /* enter specified state */
467 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
468
469 /* Mandatory power management transition delays */
470 /* see PCI PM 1.1 5.6.1 table 18 */
471 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700472 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 else if (state == PCI_D2 || dev->current_state == PCI_D2)
474 udelay(200);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475
David Shaohua Lib9131002005-03-19 00:16:18 -0500476 /*
477 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
Andreas Mohrd6e05ed2006-06-26 18:35:02 +0200478 * Firmware method after native method ?
David Shaohua Lib9131002005-03-19 00:16:18 -0500479 */
480 if (platform_pci_set_power_state)
481 platform_pci_set_power_state(dev, state);
482
483 dev->current_state = state;
John W. Linville064b53db2005-07-27 10:19:44 -0400484
485 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
486 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
487 * from D3hot to D0 _may_ perform an internal reset, thereby
488 * going to "D0 Uninitialized" rather than "D0 Initialized".
489 * For example, at least some versions of the 3c905B and the
490 * 3c556B exhibit this behaviour.
491 *
492 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
493 * devices in a D3hot state at boot. Consequently, we need to
494 * restore at least the BARs so that the device will be
495 * accessible to its driver.
496 */
497 if (need_restore)
498 pci_restore_bars(dev);
499
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 return 0;
501}
502
Shaohua Liab826ca2007-07-20 10:03:22 +0800503pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
David Shaohua Li0f644742005-03-19 00:15:48 -0500504
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505/**
506 * pci_choose_state - Choose the power state of a PCI device
507 * @dev: PCI device to be suspended
508 * @state: target sleep state for the whole system. This is the value
509 * that is passed to suspend() function.
510 *
511 * Returns PCI power state suitable for given device and given system
512 * message.
513 */
514
515pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
516{
Shaohua Liab826ca2007-07-20 10:03:22 +0800517 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500518
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
520 return PCI_D0;
521
David Shaohua Li0f644742005-03-19 00:15:48 -0500522 if (platform_pci_choose_state) {
523 ret = platform_pci_choose_state(dev, state);
Shaohua Liab826ca2007-07-20 10:03:22 +0800524 if (ret != PCI_POWER_ERROR)
525 return ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500526 }
Pavel Machekca078ba2005-09-03 15:56:57 -0700527
528 switch (state.event) {
529 case PM_EVENT_ON:
530 return PCI_D0;
531 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700532 case PM_EVENT_PRETHAW:
533 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700534 case PM_EVENT_SUSPEND:
535 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 default:
David Brownellb887d2e2006-08-14 23:11:05 -0700537 printk("Unrecognized suspend event %d\n", state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 BUG();
539 }
540 return PCI_D0;
541}
542
543EXPORT_SYMBOL(pci_choose_state);
544
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300545static int pci_save_pcie_state(struct pci_dev *dev)
546{
547 int pos, i = 0;
548 struct pci_cap_saved_state *save_state;
549 u16 *cap;
550
551 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
552 if (pos <= 0)
553 return 0;
554
Eric W. Biederman9f355752007-03-08 13:06:13 -0700555 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
556 if (!save_state)
557 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300558 if (!save_state) {
559 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
560 return -ENOMEM;
561 }
562 cap = (u16 *)&save_state->data[0];
563
564 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
565 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
566 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
567 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
568 pci_add_saved_cap(dev, save_state);
569 return 0;
570}
571
572static void pci_restore_pcie_state(struct pci_dev *dev)
573{
574 int i = 0, pos;
575 struct pci_cap_saved_state *save_state;
576 u16 *cap;
577
578 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
579 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
580 if (!save_state || pos <= 0)
581 return;
582 cap = (u16 *)&save_state->data[0];
583
584 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
585 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
586 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
587 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300588}
589
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800590
591static int pci_save_pcix_state(struct pci_dev *dev)
592{
593 int pos, i = 0;
594 struct pci_cap_saved_state *save_state;
595 u16 *cap;
596
597 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
598 if (pos <= 0)
599 return 0;
600
Eric W. Biederman9f355752007-03-08 13:06:13 -0700601 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
602 if (!save_state)
603 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800604 if (!save_state) {
605 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
606 return -ENOMEM;
607 }
608 cap = (u16 *)&save_state->data[0];
609
610 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
611 pci_add_saved_cap(dev, save_state);
612 return 0;
613}
614
615static void pci_restore_pcix_state(struct pci_dev *dev)
616{
617 int i = 0, pos;
618 struct pci_cap_saved_state *save_state;
619 u16 *cap;
620
621 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
622 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
623 if (!save_state || pos <= 0)
624 return;
625 cap = (u16 *)&save_state->data[0];
626
627 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800628}
629
630
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631/**
632 * pci_save_state - save the PCI configuration space of a device before suspending
633 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 */
635int
636pci_save_state(struct pci_dev *dev)
637{
638 int i;
639 /* XXX: 100% dword access ok here? */
640 for (i = 0; i < 16; i++)
641 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300642 if ((i = pci_save_pcie_state(dev)) != 0)
643 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800644 if ((i = pci_save_pcix_state(dev)) != 0)
645 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 return 0;
647}
648
649/**
650 * pci_restore_state - Restore the saved state of a PCI device
651 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 */
653int
654pci_restore_state(struct pci_dev *dev)
655{
656 int i;
Dave Jones04d9c1a2006-04-18 21:06:51 -0700657 int val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300659 /* PCI Express register must be restored first */
660 pci_restore_pcie_state(dev);
661
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700662 /*
663 * The Base Address register should be programmed before the command
664 * register(s)
665 */
666 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700667 pci_read_config_dword(dev, i * 4, &val);
668 if (val != dev->saved_config_space[i]) {
669 printk(KERN_DEBUG "PM: Writing back config space on "
670 "device %s at offset %x (was %x, writing %x)\n",
671 pci_name(dev), i,
672 val, (int)dev->saved_config_space[i]);
673 pci_write_config_dword(dev,i * 4,
674 dev->saved_config_space[i]);
675 }
676 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800677 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800678 pci_restore_msi_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100679
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 return 0;
681}
682
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900683static int do_pci_enable_device(struct pci_dev *dev, int bars)
684{
685 int err;
686
687 err = pci_set_power_state(dev, PCI_D0);
688 if (err < 0 && err != -EIO)
689 return err;
690 err = pcibios_enable_device(dev, bars);
691 if (err < 0)
692 return err;
693 pci_fixup_device(pci_fixup_enable, dev);
694
695 return 0;
696}
697
698/**
Tejun Heo0b62e132007-07-27 14:43:35 +0900699 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900700 * @dev: PCI device to be resumed
701 *
702 * Note this function is a backend of pci_default_resume and is not supposed
703 * to be called by normal code, write proper resume handler and use it instead.
704 */
Tejun Heo0b62e132007-07-27 14:43:35 +0900705int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900706{
707 if (atomic_read(&dev->enable_cnt))
708 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
709 return 0;
710}
711
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712/**
713 * pci_enable_device_bars - Initialize some of a device for use
714 * @dev: PCI device to be initialized
715 * @bars: bitmask of BAR's that must be configured
716 *
717 * Initialize device before it's used by a driver. Ask low-level code
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900718 * to enable selected I/O and memory resources. Wake up the device if it
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 * was suspended. Beware, this function can fail.
720 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721int
722pci_enable_device_bars(struct pci_dev *dev, int bars)
723{
724 int err;
725
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900726 if (atomic_add_return(1, &dev->enable_cnt) > 1)
727 return 0; /* already enabled */
728
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900729 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700730 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900731 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900732 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733}
734
735/**
736 * pci_enable_device - Initialize device before it's used by a driver.
737 * @dev: PCI device to be initialized
738 *
739 * Initialize device before it's used by a driver. Ask low-level code
740 * to enable I/O and memory. Wake up the device if it was suspended.
741 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800742 *
743 * Note we don't actually enable the device many times if we call
744 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800746int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747{
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900748 return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749}
750
Tejun Heo9ac78492007-01-20 16:00:26 +0900751/*
752 * Managed PCI resources. This manages device on/off, intx/msi/msix
753 * on/off and BAR regions. pci_dev itself records msi/msix status, so
754 * there's no need to track it separately. pci_devres is initialized
755 * when a device is enabled using managed PCI device enable interface.
756 */
757struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -0800758 unsigned int enabled:1;
759 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900760 unsigned int orig_intx:1;
761 unsigned int restore_intx:1;
762 u32 region_mask;
763};
764
765static void pcim_release(struct device *gendev, void *res)
766{
767 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
768 struct pci_devres *this = res;
769 int i;
770
771 if (dev->msi_enabled)
772 pci_disable_msi(dev);
773 if (dev->msix_enabled)
774 pci_disable_msix(dev);
775
776 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
777 if (this->region_mask & (1 << i))
778 pci_release_region(dev, i);
779
780 if (this->restore_intx)
781 pci_intx(dev, this->orig_intx);
782
Tejun Heo7f375f32007-02-25 04:36:01 -0800783 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +0900784 pci_disable_device(dev);
785}
786
787static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
788{
789 struct pci_devres *dr, *new_dr;
790
791 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
792 if (dr)
793 return dr;
794
795 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
796 if (!new_dr)
797 return NULL;
798 return devres_get(&pdev->dev, new_dr, NULL, NULL);
799}
800
801static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
802{
803 if (pci_is_managed(pdev))
804 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
805 return NULL;
806}
807
808/**
809 * pcim_enable_device - Managed pci_enable_device()
810 * @pdev: PCI device to be initialized
811 *
812 * Managed pci_enable_device().
813 */
814int pcim_enable_device(struct pci_dev *pdev)
815{
816 struct pci_devres *dr;
817 int rc;
818
819 dr = get_pci_dr(pdev);
820 if (unlikely(!dr))
821 return -ENOMEM;
Tejun Heo7f375f32007-02-25 04:36:01 -0800822 WARN_ON(!!dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +0900823
824 rc = pci_enable_device(pdev);
825 if (!rc) {
826 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -0800827 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900828 }
829 return rc;
830}
831
832/**
833 * pcim_pin_device - Pin managed PCI device
834 * @pdev: PCI device to pin
835 *
836 * Pin managed PCI device @pdev. Pinned device won't be disabled on
837 * driver detach. @pdev must have been enabled with
838 * pcim_enable_device().
839 */
840void pcim_pin_device(struct pci_dev *pdev)
841{
842 struct pci_devres *dr;
843
844 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -0800845 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +0900846 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800847 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900848}
849
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850/**
851 * pcibios_disable_device - disable arch specific PCI resources for device dev
852 * @dev: the PCI device to disable
853 *
854 * Disables architecture specific PCI resources for the device. This
855 * is the default implementation. Architecture implementations can
856 * override this.
857 */
858void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
859
860/**
861 * pci_disable_device - Disable PCI device after use
862 * @dev: PCI device to be disabled
863 *
864 * Signal to the system that the PCI device is not in use by the system
865 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800866 *
867 * Note we don't actually disable the device until all callers of
868 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 */
870void
871pci_disable_device(struct pci_dev *dev)
872{
Tejun Heo9ac78492007-01-20 16:00:26 +0900873 struct pci_devres *dr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 u16 pci_command;
Shaohua Li99dc8042006-05-26 10:58:27 +0800875
Tejun Heo9ac78492007-01-20 16:00:26 +0900876 dr = find_pci_dr(dev);
877 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800878 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +0900879
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800880 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
881 return;
882
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
884 if (pci_command & PCI_COMMAND_MASTER) {
885 pci_command &= ~PCI_COMMAND_MASTER;
886 pci_write_config_word(dev, PCI_COMMAND, pci_command);
887 }
Kenji Kaneshigeceb43742005-04-08 14:53:31 +0900888 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889
890 pcibios_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891}
892
893/**
Brian Kingf7bdd122007-04-06 16:39:36 -0500894 * pcibios_set_pcie_reset_state - set reset state for device dev
895 * @dev: the PCI-E device reset
896 * @state: Reset state to enter into
897 *
898 *
899 * Sets the PCI-E reset state for the device. This is the default
900 * implementation. Architecture implementations can override this.
901 */
902int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
903 enum pcie_reset_state state)
904{
905 return -EINVAL;
906}
907
908/**
909 * pci_set_pcie_reset_state - set reset state for device dev
910 * @dev: the PCI-E device reset
911 * @state: Reset state to enter into
912 *
913 *
914 * Sets the PCI reset state for the device.
915 */
916int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
917{
918 return pcibios_set_pcie_reset_state(dev, state);
919}
920
921/**
David Brownell075c1772007-04-26 00:12:06 -0700922 * pci_enable_wake - enable PCI device as wakeup event source
923 * @dev: PCI device affected
924 * @state: PCI state from which device will issue wakeup events
925 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926 *
David Brownell075c1772007-04-26 00:12:06 -0700927 * This enables the device as a wakeup event source, or disables it.
928 * When such events involves platform-specific hooks, those hooks are
929 * called automatically by this routine.
930 *
931 * Devices with legacy power management (no standard PCI PM capabilities)
932 * always require such platform hooks. Depending on the platform, devices
933 * supporting the standard PCI PME# signal may require such platform hooks;
934 * they always update bits in config space to allow PME# generation.
935 *
936 * -EIO is returned if the device can't ever be a wakeup event source.
937 * -EINVAL is returned if the device can't generate wakeup events from
938 * the specified PCI state. Returns zero if the operation is successful.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 */
940int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
941{
942 int pm;
David Brownell075c1772007-04-26 00:12:06 -0700943 int status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 u16 value;
945
David Brownell075c1772007-04-26 00:12:06 -0700946 /* Note that drivers should verify device_may_wakeup(&dev->dev)
947 * before calling this function. Platform code should report
948 * errors when drivers try to enable wakeup on devices that
949 * can't issue wakeups, or on which wakeups were disabled by
950 * userspace updating the /sys/devices.../power/wakeup file.
951 */
952
953 status = call_platform_enable_wakeup(&dev->dev, enable);
954
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 /* find PCI PM capability in list */
956 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
957
David Brownell075c1772007-04-26 00:12:06 -0700958 /* If device doesn't support PM Capabilities, but caller wants to
959 * disable wake events, it's a NOP. Otherwise fail unless the
960 * platform hooks handled this legacy device already.
961 */
962 if (!pm)
963 return enable ? status : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964
965 /* Check device's ability to generate PME# */
966 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
967
968 value &= PCI_PM_CAP_PME_MASK;
969 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
970
971 /* Check if it can generate PME# from requested state. */
David Brownell075c1772007-04-26 00:12:06 -0700972 if (!value || !(value & (1 << state))) {
973 /* if it can't, revert what the platform hook changed,
974 * always reporting the base "EINVAL, can't PME#" error
975 */
976 if (enable)
977 call_platform_enable_wakeup(&dev->dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978 return enable ? -EINVAL : 0;
David Brownell075c1772007-04-26 00:12:06 -0700979 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980
981 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
982
983 /* Clear PME_Status by writing 1 to it and enable PME# */
984 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
985
986 if (!enable)
987 value &= ~PCI_PM_CTRL_PME_ENABLE;
988
989 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
David Brownell075c1772007-04-26 00:12:06 -0700990
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991 return 0;
992}
993
994int
995pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
996{
997 u8 pin;
998
Kristen Accardi514d2072005-11-02 16:24:39 -0800999 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 if (!pin)
1001 return -1;
1002 pin--;
1003 while (dev->bus->self) {
1004 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1005 dev = dev->bus->self;
1006 }
1007 *bridge = dev;
1008 return pin;
1009}
1010
1011/**
1012 * pci_release_region - Release a PCI bar
1013 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1014 * @bar: BAR to release
1015 *
1016 * Releases the PCI I/O and memory resources previously reserved by a
1017 * successful call to pci_request_region. Call this function only
1018 * after all use of the PCI regions has ceased.
1019 */
1020void pci_release_region(struct pci_dev *pdev, int bar)
1021{
Tejun Heo9ac78492007-01-20 16:00:26 +09001022 struct pci_devres *dr;
1023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 if (pci_resource_len(pdev, bar) == 0)
1025 return;
1026 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1027 release_region(pci_resource_start(pdev, bar),
1028 pci_resource_len(pdev, bar));
1029 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1030 release_mem_region(pci_resource_start(pdev, bar),
1031 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09001032
1033 dr = find_pci_dr(pdev);
1034 if (dr)
1035 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036}
1037
1038/**
1039 * pci_request_region - Reserved PCI I/O and memory resource
1040 * @pdev: PCI device whose resources are to be reserved
1041 * @bar: BAR to be reserved
1042 * @res_name: Name to be associated with resource.
1043 *
1044 * Mark the PCI region associated with PCI device @pdev BR @bar as
1045 * being reserved by owner @res_name. Do not access any
1046 * address inside the PCI regions unless this call returns
1047 * successfully.
1048 *
1049 * Returns 0 on success, or %EBUSY on error. A warning
1050 * message is also printed on failure.
1051 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001052int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053{
Tejun Heo9ac78492007-01-20 16:00:26 +09001054 struct pci_devres *dr;
1055
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 if (pci_resource_len(pdev, bar) == 0)
1057 return 0;
1058
1059 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1060 if (!request_region(pci_resource_start(pdev, bar),
1061 pci_resource_len(pdev, bar), res_name))
1062 goto err_out;
1063 }
1064 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1065 if (!request_mem_region(pci_resource_start(pdev, bar),
1066 pci_resource_len(pdev, bar), res_name))
1067 goto err_out;
1068 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001069
1070 dr = find_pci_dr(pdev);
1071 if (dr)
1072 dr->region_mask |= 1 << bar;
1073
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 return 0;
1075
1076err_out:
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -07001077 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1078 "for device %s\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1080 bar + 1, /* PCI BAR # */
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -07001081 (unsigned long long)pci_resource_len(pdev, bar),
1082 (unsigned long long)pci_resource_start(pdev, bar),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 pci_name(pdev));
1084 return -EBUSY;
1085}
1086
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001087/**
1088 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1089 * @pdev: PCI device whose resources were previously reserved
1090 * @bars: Bitmask of BARs to be released
1091 *
1092 * Release selected PCI I/O and memory resources previously reserved.
1093 * Call this function only after all use of the PCI regions has ceased.
1094 */
1095void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1096{
1097 int i;
1098
1099 for (i = 0; i < 6; i++)
1100 if (bars & (1 << i))
1101 pci_release_region(pdev, i);
1102}
1103
1104/**
1105 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1106 * @pdev: PCI device whose resources are to be reserved
1107 * @bars: Bitmask of BARs to be requested
1108 * @res_name: Name to be associated with resource
1109 */
1110int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1111 const char *res_name)
1112{
1113 int i;
1114
1115 for (i = 0; i < 6; i++)
1116 if (bars & (1 << i))
1117 if(pci_request_region(pdev, i, res_name))
1118 goto err_out;
1119 return 0;
1120
1121err_out:
1122 while(--i >= 0)
1123 if (bars & (1 << i))
1124 pci_release_region(pdev, i);
1125
1126 return -EBUSY;
1127}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
1129/**
1130 * pci_release_regions - Release reserved PCI I/O and memory resources
1131 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1132 *
1133 * Releases all PCI I/O and memory resources previously reserved by a
1134 * successful call to pci_request_regions. Call this function only
1135 * after all use of the PCI regions has ceased.
1136 */
1137
1138void pci_release_regions(struct pci_dev *pdev)
1139{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001140 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141}
1142
1143/**
1144 * pci_request_regions - Reserved PCI I/O and memory resources
1145 * @pdev: PCI device whose resources are to be reserved
1146 * @res_name: Name to be associated with resource.
1147 *
1148 * Mark all PCI regions associated with PCI device @pdev as
1149 * being reserved by owner @res_name. Do not access any
1150 * address inside the PCI regions unless this call returns
1151 * successfully.
1152 *
1153 * Returns 0 on success, or %EBUSY on error. A warning
1154 * message is also printed on failure.
1155 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001156int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001158 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159}
1160
1161/**
1162 * pci_set_master - enables bus-mastering for device dev
1163 * @dev: the PCI device to enable
1164 *
1165 * Enables bus-mastering on the device and calls pcibios_set_master()
1166 * to do the needed arch specific settings.
1167 */
1168void
1169pci_set_master(struct pci_dev *dev)
1170{
1171 u16 cmd;
1172
1173 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1174 if (! (cmd & PCI_COMMAND_MASTER)) {
1175 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1176 cmd |= PCI_COMMAND_MASTER;
1177 pci_write_config_word(dev, PCI_COMMAND, cmd);
1178 }
1179 dev->is_busmaster = 1;
1180 pcibios_set_master(dev);
1181}
1182
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001183#ifdef PCI_DISABLE_MWI
1184int pci_set_mwi(struct pci_dev *dev)
1185{
1186 return 0;
1187}
1188
Randy Dunlap694625c2007-07-09 11:55:54 -07001189int pci_try_set_mwi(struct pci_dev *dev)
1190{
1191 return 0;
1192}
1193
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001194void pci_clear_mwi(struct pci_dev *dev)
1195{
1196}
1197
1198#else
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001199
1200#ifndef PCI_CACHE_LINE_BYTES
1201#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1202#endif
1203
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204/* This can be overridden by arch code. */
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001205/* Don't forget this is measured in 32-bit words, not bytes */
1206u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207
1208/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001209 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1210 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001212 * Helper function for pci_set_mwi.
1213 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1215 *
1216 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1217 */
1218static int
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001219pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220{
1221 u8 cacheline_size;
1222
1223 if (!pci_cache_line_size)
1224 return -EINVAL; /* The system doesn't support MWI. */
1225
1226 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1227 equal to or multiple of the right value. */
1228 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1229 if (cacheline_size >= pci_cache_line_size &&
1230 (cacheline_size % pci_cache_line_size) == 0)
1231 return 0;
1232
1233 /* Write the correct value. */
1234 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1235 /* Read it back. */
1236 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1237 if (cacheline_size == pci_cache_line_size)
1238 return 0;
1239
1240 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1241 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1242
1243 return -EINVAL;
1244}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245
1246/**
1247 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1248 * @dev: the PCI device for which MWI is enabled
1249 *
Randy Dunlap694625c2007-07-09 11:55:54 -07001250 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251 *
1252 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1253 */
1254int
1255pci_set_mwi(struct pci_dev *dev)
1256{
1257 int rc;
1258 u16 cmd;
1259
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001260 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261 if (rc)
1262 return rc;
1263
1264 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1265 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Randy Dunlap694625c2007-07-09 11:55:54 -07001266 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1267 pci_name(dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 cmd |= PCI_COMMAND_INVALIDATE;
1269 pci_write_config_word(dev, PCI_COMMAND, cmd);
1270 }
1271
1272 return 0;
1273}
1274
1275/**
Randy Dunlap694625c2007-07-09 11:55:54 -07001276 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1277 * @dev: the PCI device for which MWI is enabled
1278 *
1279 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1280 * Callers are not required to check the return value.
1281 *
1282 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1283 */
1284int pci_try_set_mwi(struct pci_dev *dev)
1285{
1286 int rc = pci_set_mwi(dev);
1287 return rc;
1288}
1289
1290/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1292 * @dev: the PCI device to disable
1293 *
1294 * Disables PCI Memory-Write-Invalidate transaction on the device
1295 */
1296void
1297pci_clear_mwi(struct pci_dev *dev)
1298{
1299 u16 cmd;
1300
1301 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1302 if (cmd & PCI_COMMAND_INVALIDATE) {
1303 cmd &= ~PCI_COMMAND_INVALIDATE;
1304 pci_write_config_word(dev, PCI_COMMAND, cmd);
1305 }
1306}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001307#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308
Brett M Russa04ce0f2005-08-15 15:23:41 -04001309/**
1310 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001311 * @pdev: the PCI device to operate on
1312 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04001313 *
1314 * Enables/disables PCI INTx for device dev
1315 */
1316void
1317pci_intx(struct pci_dev *pdev, int enable)
1318{
1319 u16 pci_command, new;
1320
1321 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1322
1323 if (enable) {
1324 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1325 } else {
1326 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1327 }
1328
1329 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09001330 struct pci_devres *dr;
1331
Brett M Russ2fd9d742005-09-09 10:02:22 -07001332 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09001333
1334 dr = find_pci_dr(pdev);
1335 if (dr && !dr->restore_intx) {
1336 dr->restore_intx = 1;
1337 dr->orig_intx = !enable;
1338 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04001339 }
1340}
1341
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001342/**
1343 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07001344 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001345 *
1346 * If you want to use msi see pci_enable_msi and friends.
1347 * This is a lower level primitive that allows us to disable
1348 * msi operation at the device level.
1349 */
1350void pci_msi_off(struct pci_dev *dev)
1351{
1352 int pos;
1353 u16 control;
1354
1355 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1356 if (pos) {
1357 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1358 control &= ~PCI_MSI_FLAGS_ENABLE;
1359 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1360 }
1361 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1362 if (pos) {
1363 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1364 control &= ~PCI_MSIX_FLAGS_ENABLE;
1365 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1366 }
1367}
1368
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1370/*
1371 * These can be overridden by arch-specific implementations
1372 */
1373int
1374pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1375{
1376 if (!pci_dma_supported(dev, mask))
1377 return -EIO;
1378
1379 dev->dma_mask = mask;
1380
1381 return 0;
1382}
1383
1384int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1386{
1387 if (!pci_dma_supported(dev, mask))
1388 return -EIO;
1389
1390 dev->dev.coherent_dma_mask = mask;
1391
1392 return 0;
1393}
1394#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001395
1396/**
Peter Orubad556ad42007-05-15 13:59:13 +02001397 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1398 * @dev: PCI device to query
1399 *
1400 * Returns mmrbc: maximum designed memory read count in bytes
1401 * or appropriate error value.
1402 */
1403int pcix_get_max_mmrbc(struct pci_dev *dev)
1404{
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001405 int err, cap;
Peter Orubad556ad42007-05-15 13:59:13 +02001406 u32 stat;
1407
1408 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1409 if (!cap)
1410 return -EINVAL;
1411
1412 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1413 if (err)
1414 return -EINVAL;
1415
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001416 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
Peter Orubad556ad42007-05-15 13:59:13 +02001417}
1418EXPORT_SYMBOL(pcix_get_max_mmrbc);
1419
1420/**
1421 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1422 * @dev: PCI device to query
1423 *
1424 * Returns mmrbc: maximum memory read count in bytes
1425 * or appropriate error value.
1426 */
1427int pcix_get_mmrbc(struct pci_dev *dev)
1428{
1429 int ret, cap;
1430 u32 cmd;
1431
1432 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1433 if (!cap)
1434 return -EINVAL;
1435
1436 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1437 if (!ret)
1438 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1439
1440 return ret;
1441}
1442EXPORT_SYMBOL(pcix_get_mmrbc);
1443
1444/**
1445 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1446 * @dev: PCI device to query
1447 * @mmrbc: maximum memory read count in bytes
1448 * valid values are 512, 1024, 2048, 4096
1449 *
1450 * If possible sets maximum memory read byte count, some bridges have erratas
1451 * that prevent this.
1452 */
1453int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1454{
1455 int cap, err = -EINVAL;
1456 u32 stat, cmd, v, o;
1457
vignesh babu229f5af2007-08-13 18:23:14 +05301458 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Peter Orubad556ad42007-05-15 13:59:13 +02001459 goto out;
1460
1461 v = ffs(mmrbc) - 10;
1462
1463 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1464 if (!cap)
1465 goto out;
1466
1467 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1468 if (err)
1469 goto out;
1470
1471 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1472 return -E2BIG;
1473
1474 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1475 if (err)
1476 goto out;
1477
1478 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1479 if (o != v) {
1480 if (v > o && dev->bus &&
1481 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1482 return -EIO;
1483
1484 cmd &= ~PCI_X_CMD_MAX_READ;
1485 cmd |= v << 2;
1486 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1487 }
1488out:
1489 return err;
1490}
1491EXPORT_SYMBOL(pcix_set_mmrbc);
1492
1493/**
1494 * pcie_get_readrq - get PCI Express read request size
1495 * @dev: PCI device to query
1496 *
1497 * Returns maximum memory read request in bytes
1498 * or appropriate error value.
1499 */
1500int pcie_get_readrq(struct pci_dev *dev)
1501{
1502 int ret, cap;
1503 u16 ctl;
1504
1505 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1506 if (!cap)
1507 return -EINVAL;
1508
1509 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1510 if (!ret)
1511 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1512
1513 return ret;
1514}
1515EXPORT_SYMBOL(pcie_get_readrq);
1516
1517/**
1518 * pcie_set_readrq - set PCI Express maximum memory read request
1519 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07001520 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02001521 * valid values are 128, 256, 512, 1024, 2048, 4096
1522 *
1523 * If possible sets maximum read byte count
1524 */
1525int pcie_set_readrq(struct pci_dev *dev, int rq)
1526{
1527 int cap, err = -EINVAL;
1528 u16 ctl, v;
1529
vignesh babu229f5af2007-08-13 18:23:14 +05301530 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Peter Orubad556ad42007-05-15 13:59:13 +02001531 goto out;
1532
1533 v = (ffs(rq) - 8) << 12;
1534
1535 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1536 if (!cap)
1537 goto out;
1538
1539 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1540 if (err)
1541 goto out;
1542
1543 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1544 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1545 ctl |= v;
1546 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1547 }
1548
1549out:
1550 return err;
1551}
1552EXPORT_SYMBOL(pcie_set_readrq);
1553
1554/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001555 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08001556 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001557 * @flags: resource type mask to be selected
1558 *
1559 * This helper routine makes bar mask from the type of resource.
1560 */
1561int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1562{
1563 int i, bars = 0;
1564 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1565 if (pci_resource_flags(dev, i) & flags)
1566 bars |= (1 << i);
1567 return bars;
1568}
1569
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570static int __devinit pci_init(void)
1571{
1572 struct pci_dev *dev = NULL;
1573
1574 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1575 pci_fixup_device(pci_fixup_final, dev);
1576 }
1577 return 0;
1578}
1579
1580static int __devinit pci_setup(char *str)
1581{
1582 while (str) {
1583 char *k = strchr(str, ',');
1584 if (k)
1585 *k++ = 0;
1586 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001587 if (!strcmp(str, "nomsi")) {
1588 pci_no_msi();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08001589 } else if (!strncmp(str, "cbiosize=", 9)) {
1590 pci_cardbus_io_size = memparse(str + 9, &str);
1591 } else if (!strncmp(str, "cbmemsize=", 10)) {
1592 pci_cardbus_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001593 } else {
1594 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1595 str);
1596 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 }
1598 str = k;
1599 }
Andi Kleen0637a702006-09-26 10:52:41 +02001600 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601}
Andi Kleen0637a702006-09-26 10:52:41 +02001602early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603
1604device_initcall(pci_init);
1605
John W. Linville064b53db2005-07-27 10:19:44 -04001606EXPORT_SYMBOL_GPL(pci_restore_bars);
Tejun Heo0b62e132007-07-27 14:43:35 +09001607EXPORT_SYMBOL(pci_reenable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608EXPORT_SYMBOL(pci_enable_device_bars);
1609EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001610EXPORT_SYMBOL(pcim_enable_device);
1611EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613EXPORT_SYMBOL(pci_find_capability);
1614EXPORT_SYMBOL(pci_bus_find_capability);
1615EXPORT_SYMBOL(pci_release_regions);
1616EXPORT_SYMBOL(pci_request_regions);
1617EXPORT_SYMBOL(pci_release_region);
1618EXPORT_SYMBOL(pci_request_region);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001619EXPORT_SYMBOL(pci_release_selected_regions);
1620EXPORT_SYMBOL(pci_request_selected_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621EXPORT_SYMBOL(pci_set_master);
1622EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07001623EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04001625EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1628EXPORT_SYMBOL(pci_assign_resource);
1629EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001630EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631
1632EXPORT_SYMBOL(pci_set_power_state);
1633EXPORT_SYMBOL(pci_save_state);
1634EXPORT_SYMBOL(pci_restore_state);
1635EXPORT_SYMBOL(pci_enable_wake);
Brian Kingf7bdd122007-04-06 16:39:36 -05001636EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637