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gerrit-public.fairphone.software / kernel / msm-4.19 / de1036b1cea147c5049c65f5bd26fb451f1624cd / . / drivers / net / ixgbe / ixgbe_fcoe.h
blob: abf4b2b3f2520f35117403061895cf9e968fc003 [file] [log] [blame]
Yi Zoue92cbea2009-05-13 13:10:01 +0000[diff] [blame]1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Shannon Nelson8c47eaa2010-01-13 01:49:34 +0000[diff] [blame]4 Copyright(c) 1999 - 2010 Intel Corporation.
Yi Zoue92cbea2009-05-13 13:10:01 +0000[diff] [blame]5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_FCOE_H
29#define _IXGBE_FCOE_H
30
Yi Zou3d8fd382009-06-08 14:38:44 +0000[diff] [blame]31#include <scsi/fc/fc_fs.h>
Yi Zoue92cbea2009-05-13 13:10:01 +0000[diff] [blame]32#include <scsi/fc/fc_fcoe.h>
33
34/* shift bits within STAT fo FCSTAT */
35#define IXGBE_RXDADV_FCSTAT_SHIFT 4
36
37/* ddp user buffer */
38#define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */
39#define IXGBE_FCPTR_ALIGN 16
40#define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
41#define IXGBE_FCBUFF_4KB 0x0
42#define IXGBE_FCBUFF_8KB 0x1
43#define IXGBE_FCBUFF_16KB 0x2
44#define IXGBE_FCBUFF_64KB 0x3
45#define IXGBE_FCBUFF_MAX 65536 /* 64KB max */
46#define IXGBE_FCBUFF_MIN 4096 /* 4KB min */
47#define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */
48
Yi Zou6ee16522009-08-31 12:34:28 +0000[diff] [blame]49/* Default traffic class to use for FCoE */
50#define IXGBE_FCOE_DEFTC 3
51
Yi Zoue92cbea2009-05-13 13:10:01 +0000[diff] [blame]52/* fcerr */
53#define IXGBE_FCERR_BADCRC 0x00100000
54
55struct ixgbe_fcoe_ddp {
56 int len;
57 u32 err;
58 unsigned int sgc;
59 struct scatterlist *sgl;
60 dma_addr_t udp;
Yi Zoud0ed8932009-05-13 13:11:29 +0000[diff] [blame]61 u64 *udl;
Yi Zoue92cbea2009-05-13 13:10:01 +0000[diff] [blame]62};
63
64struct ixgbe_fcoe {
Yi Zou61a0f422009-12-03 11:32:22 +0000[diff] [blame]65#ifdef CONFIG_IXGBE_DCB
Yi Zou6ee16522009-08-31 12:34:28 +0000[diff] [blame]66 u8 tc;
Yi Zou61a0f422009-12-03 11:32:22 +0000[diff] [blame]67 u8 up;
68#endif
Yi Zoue92cbea2009-05-13 13:10:01 +0000[diff] [blame]69 spinlock_t lock;
70 struct pci_pool *pool;
71 struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
72};
73
74#endif /* _IXGBE_FCOE_H */