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ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +02001/*
2 * Atmel SDMMC controller driver.
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
Ludovic Desroches4e289a72016-04-07 11:13:09 +020018#include <linux/delay.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020019#include <linux/err.h>
20#include <linux/io.h>
Ludovic Desroches44064332016-04-28 14:59:26 +020021#include <linux/kernel.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020022#include <linux/mmc/host.h>
ludovic.desroches@atmel.com64e5cd72016-03-17 14:54:34 +010023#include <linux/mmc/slot-gpio.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020024#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +010027#include <linux/pm.h>
28#include <linux/pm_runtime.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020029
30#include "sdhci-pltfm.h"
31
32#define SDMMC_CACR 0x230
33#define SDMMC_CACR_CAPWREN BIT(0)
34#define SDMMC_CACR_KEY (0x46 << 8)
35
Ludovic Desroches44064332016-04-28 14:59:26 +020036#define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
37
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020038struct sdhci_at91_priv {
39 struct clk *hclock;
40 struct clk *gck;
41 struct clk *mainck;
42};
43
Ludovic Desroches4e289a72016-04-07 11:13:09 +020044static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
45{
46 u16 clk;
47 unsigned long timeout;
48
49 host->mmc->actual_clock = 0;
50
51 /*
52 * There is no requirement to disable the internal clock before
53 * changing the SD clock configuration. Moreover, disabling the
54 * internal clock, changing the configuration and re-enabling the
55 * internal clock causes some bugs. It can prevent to get the internal
56 * clock stable flag ready and an unexpected switch to the base clock
57 * when using presets.
58 */
59 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
60 clk &= SDHCI_CLOCK_INT_EN;
61 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
62
63 if (clock == 0)
64 return;
65
66 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
67
68 clk |= SDHCI_CLOCK_INT_EN;
69 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
70
71 /* Wait max 20 ms */
72 timeout = 20;
73 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
74 & SDHCI_CLOCK_INT_STABLE)) {
75 if (timeout == 0) {
76 pr_err("%s: Internal clock never stabilised.\n",
77 mmc_hostname(host->mmc));
78 return;
79 }
80 timeout--;
81 mdelay(1);
82 }
83
84 clk |= SDHCI_CLOCK_CARD_EN;
85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86}
87
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020088static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
Ludovic Desroches4e289a72016-04-07 11:13:09 +020089 .set_clock = sdhci_at91_set_clock,
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020090 .set_bus_width = sdhci_set_bus_width,
91 .reset = sdhci_reset,
92 .set_uhs_signaling = sdhci_set_uhs_signaling,
93};
94
95static const struct sdhci_pltfm_data soc_data_sama5d2 = {
96 .ops = &sdhci_at91_sama5d2_ops,
97};
98
99static const struct of_device_id sdhci_at91_dt_match[] = {
100 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
101 {}
102};
103
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100104#ifdef CONFIG_PM
105static int sdhci_at91_runtime_suspend(struct device *dev)
106{
107 struct sdhci_host *host = dev_get_drvdata(dev);
108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800109 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100110 int ret;
111
112 ret = sdhci_runtime_suspend_host(host);
113
114 clk_disable_unprepare(priv->gck);
115 clk_disable_unprepare(priv->hclock);
116 clk_disable_unprepare(priv->mainck);
117
118 return ret;
119}
120
121static int sdhci_at91_runtime_resume(struct device *dev)
122{
123 struct sdhci_host *host = dev_get_drvdata(dev);
124 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800125 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100126 int ret;
127
128 ret = clk_prepare_enable(priv->mainck);
129 if (ret) {
130 dev_err(dev, "can't enable mainck\n");
131 return ret;
132 }
133
134 ret = clk_prepare_enable(priv->hclock);
135 if (ret) {
136 dev_err(dev, "can't enable hclock\n");
137 return ret;
138 }
139
140 ret = clk_prepare_enable(priv->gck);
141 if (ret) {
142 dev_err(dev, "can't enable gck\n");
143 return ret;
144 }
145
146 return sdhci_runtime_resume_host(host);
147}
148#endif /* CONFIG_PM */
149
150static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
151 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
152 pm_runtime_force_resume)
153 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
154 sdhci_at91_runtime_resume,
155 NULL)
156};
157
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200158static int sdhci_at91_probe(struct platform_device *pdev)
159{
160 const struct of_device_id *match;
161 const struct sdhci_pltfm_data *soc_data;
162 struct sdhci_host *host;
163 struct sdhci_pltfm_host *pltfm_host;
164 struct sdhci_at91_priv *priv;
165 unsigned int caps0, caps1;
166 unsigned int clk_base, clk_mul;
167 unsigned int gck_rate, real_gck_rate;
168 int ret;
Ludovic Desroches44064332016-04-28 14:59:26 +0200169 unsigned int preset_div;
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200170
171 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
172 if (!match)
173 return -EINVAL;
174 soc_data = match->data;
175
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800176 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
177 if (IS_ERR(host))
178 return PTR_ERR(host);
179
180 pltfm_host = sdhci_priv(host);
181 priv = sdhci_pltfm_priv(pltfm_host);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200182
183 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
184 if (IS_ERR(priv->mainck)) {
185 dev_err(&pdev->dev, "failed to get baseclk\n");
186 return PTR_ERR(priv->mainck);
187 }
188
189 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
190 if (IS_ERR(priv->hclock)) {
191 dev_err(&pdev->dev, "failed to get hclock\n");
192 return PTR_ERR(priv->hclock);
193 }
194
195 priv->gck = devm_clk_get(&pdev->dev, "multclk");
196 if (IS_ERR(priv->gck)) {
197 dev_err(&pdev->dev, "failed to get multclk\n");
198 return PTR_ERR(priv->gck);
199 }
200
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200201 /*
202 * The mult clock is provided by as a generated clock by the PMC
203 * controller. In order to set the rate of gck, we have to get the
204 * base clock rate and the clock mult from capabilities.
205 */
206 clk_prepare_enable(priv->hclock);
207 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
208 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
209 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
210 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
211 gck_rate = clk_base * 1000000 * (clk_mul + 1);
212 ret = clk_set_rate(priv->gck, gck_rate);
213 if (ret < 0) {
214 dev_err(&pdev->dev, "failed to set gck");
215 goto hclock_disable_unprepare;
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200216 }
217 /*
218 * We need to check if we have the requested rate for gck because in
219 * some cases this rate could be not supported. If it happens, the rate
220 * is the closest one gck can provide. We have to update the value
221 * of clk mul.
222 */
223 real_gck_rate = clk_get_rate(priv->gck);
224 if (real_gck_rate != gck_rate) {
225 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
226 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
227 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
228 /* Set capabilities in r/w mode. */
229 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
230 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
231 /* Set capabilities in ro mode. */
232 writel(0, host->ioaddr + SDMMC_CACR);
233 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
234 clk_mul, real_gck_rate);
235 }
236
Ludovic Desroches44064332016-04-28 14:59:26 +0200237 /*
238 * We have to set preset values because it depends on the clk_mul
239 * value. Moreover, SDR104 is supported in a degraded mode since the
240 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
241 * reason, we need to use presets to support SDR104.
242 */
243 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
244 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
245 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
246 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
247 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
248 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
249 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
250 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
251 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
252 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
253 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
254 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
255 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
256 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
257 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
258
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200259 clk_prepare_enable(priv->mainck);
260 clk_prepare_enable(priv->gck);
261
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200262 ret = mmc_of_parse(host->mmc);
263 if (ret)
264 goto clocks_disable_unprepare;
265
266 sdhci_get_of_property(pdev);
267
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100268 pm_runtime_get_noresume(&pdev->dev);
269 pm_runtime_set_active(&pdev->dev);
270 pm_runtime_enable(&pdev->dev);
271 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
272 pm_runtime_use_autosuspend(&pdev->dev);
273
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200274 ret = sdhci_add_host(host);
275 if (ret)
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100276 goto pm_runtime_disable;
277
ludovic.desroches@atmel.com64e5cd72016-03-17 14:54:34 +0100278 /*
279 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
280 * the assumption that all the clocks of the controller are disabled.
281 * It means we can't get irq from it when it is runtime suspended.
282 * For that reason, it is not planned to wake-up on a card detect irq
283 * from the controller.
284 * If we want to use runtime PM and to be able to wake-up on card
285 * insertion, we have to use a GPIO for the card detection or we can
286 * use polling. Be aware that using polling will resume/suspend the
287 * controller between each attempt.
288 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
289 * to enable polling via device tree with broken-cd property.
290 */
291 if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
Arnd Bergmann287980e2016-05-27 23:23:25 +0200292 mmc_gpio_get_cd(host->mmc) < 0) {
ludovic.desroches@atmel.com64e5cd72016-03-17 14:54:34 +0100293 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
294 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
295 }
296
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100297 pm_runtime_put_autosuspend(&pdev->dev);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200298
299 return 0;
300
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100301pm_runtime_disable:
302 pm_runtime_disable(&pdev->dev);
303 pm_runtime_set_suspended(&pdev->dev);
Jisheng Zhang2df9d582016-02-02 19:55:06 +0800304 pm_runtime_put_noidle(&pdev->dev);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200305clocks_disable_unprepare:
306 clk_disable_unprepare(priv->gck);
307 clk_disable_unprepare(priv->mainck);
308hclock_disable_unprepare:
309 clk_disable_unprepare(priv->hclock);
310 sdhci_pltfm_free(pdev);
311 return ret;
312}
313
314static int sdhci_at91_remove(struct platform_device *pdev)
315{
316 struct sdhci_host *host = platform_get_drvdata(pdev);
317 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800318 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
319 struct clk *gck = priv->gck;
320 struct clk *hclock = priv->hclock;
321 struct clk *mainck = priv->mainck;
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200322
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100323 pm_runtime_get_sync(&pdev->dev);
324 pm_runtime_disable(&pdev->dev);
325 pm_runtime_put_noidle(&pdev->dev);
326
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200327 sdhci_pltfm_unregister(pdev);
328
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800329 clk_disable_unprepare(gck);
330 clk_disable_unprepare(hclock);
331 clk_disable_unprepare(mainck);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200332
333 return 0;
334}
335
336static struct platform_driver sdhci_at91_driver = {
337 .driver = {
338 .name = "sdhci-at91",
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200339 .of_match_table = sdhci_at91_dt_match,
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100340 .pm = &sdhci_at91_dev_pm_ops,
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200341 },
342 .probe = sdhci_at91_probe,
343 .remove = sdhci_at91_remove,
344};
345
346module_platform_driver(sdhci_at91_driver);
347
348MODULE_DESCRIPTION("SDHCI driver for at91");
349MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
350MODULE_LICENSE("GPL v2");