Jayamohan Kallickal | 6733b39 | 2009-09-05 07:36:35 +0530 | [diff] [blame] | 1 | /** |
| 2 | * Copyright (C) 2005 - 2009 ServerEngines |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License version 2 |
| 7 | * as published by the Free Software Foundation. The full GNU General |
| 8 | * Public License is included in this distribution in the file called COPYING. |
| 9 | * |
| 10 | * Contact Information: |
| 11 | * linux-drivers@serverengines.com |
| 12 | * |
| 13 | * ServerEngines |
| 14 | * 209 N. Fair Oaks Ave |
| 15 | * Sunnyvale, CA 94085 |
| 16 | */ |
| 17 | |
| 18 | #ifndef BEISCSI_CMDS_H |
| 19 | #define BEISCSI_CMDS_H |
| 20 | |
| 21 | /** |
| 22 | * The driver sends configuration and managements command requests to the |
| 23 | * firmware in the BE. These requests are communicated to the processor |
| 24 | * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one |
| 25 | * WRB inside a MAILBOX. |
| 26 | * The commands are serviced by the ARM processor in the BladeEngine's MPU. |
| 27 | */ |
| 28 | struct be_sge { |
| 29 | u32 pa_lo; |
| 30 | u32 pa_hi; |
| 31 | u32 len; |
| 32 | }; |
| 33 | |
| 34 | #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ |
| 35 | #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ |
| 36 | struct be_mcc_wrb { |
| 37 | u32 embedded; /* dword 0 */ |
| 38 | u32 payload_length; /* dword 1 */ |
| 39 | u32 tag0; /* dword 2 */ |
| 40 | u32 tag1; /* dword 3 */ |
| 41 | u32 rsvd; /* dword 4 */ |
| 42 | union { |
| 43 | u8 embedded_payload[236]; /* used by embedded cmds */ |
| 44 | struct be_sge sgl[19]; /* used by non-embedded cmds */ |
| 45 | } payload; |
| 46 | }; |
| 47 | |
| 48 | #define CQE_FLAGS_VALID_MASK (1 << 31) |
| 49 | #define CQE_FLAGS_ASYNC_MASK (1 << 30) |
| 50 | |
| 51 | /* Completion Status */ |
| 52 | #define MCC_STATUS_SUCCESS 0x0 |
| 53 | |
| 54 | #define CQE_STATUS_COMPL_MASK 0xFFFF |
| 55 | #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ |
| 56 | #define CQE_STATUS_EXTD_MASK 0xFFFF |
| 57 | #define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */ |
| 58 | |
| 59 | struct be_mcc_compl { |
| 60 | u32 status; /* dword 0 */ |
| 61 | u32 tag0; /* dword 1 */ |
| 62 | u32 tag1; /* dword 2 */ |
| 63 | u32 flags; /* dword 3 */ |
| 64 | }; |
| 65 | |
| 66 | /********* Mailbox door bell *************/ |
| 67 | /** |
| 68 | * Used for driver communication with the FW. |
| 69 | * The software must write this register twice to post any command. First, |
| 70 | * it writes the register with hi=1 and the upper bits of the physical address |
| 71 | * for the MAILBOX structure. Software must poll the ready bit until this |
| 72 | * is acknowledged. Then, sotware writes the register with hi=0 with the lower |
| 73 | * bits in the address. It must poll the ready bit until the command is |
| 74 | * complete. Upon completion, the MAILBOX will contain a valid completion |
| 75 | * queue entry. |
| 76 | */ |
| 77 | #define MPU_MAILBOX_DB_OFFSET 0x160 |
| 78 | #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ |
| 79 | #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ |
| 80 | |
| 81 | /********** MPU semphore ******************/ |
| 82 | #define MPU_EP_SEMAPHORE_OFFSET 0xac |
| 83 | #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF |
| 84 | #define EP_SEMAPHORE_POST_ERR_MASK 0x1 |
| 85 | #define EP_SEMAPHORE_POST_ERR_SHIFT 31 |
| 86 | |
| 87 | /********** MCC door bell ************/ |
| 88 | #define DB_MCCQ_OFFSET 0x140 |
| 89 | #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ |
| 90 | /* Number of entries posted */ |
| 91 | #define DB_MCCQ_NUM_POSTED_SHIFT 16 /* bits 16 - 29 */ |
| 92 | |
| 93 | /* MPU semphore POST stage values */ |
| 94 | #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ |
| 95 | |
| 96 | /** |
| 97 | * When the async bit of mcc_compl is set, the last 4 bytes of |
| 98 | * mcc_compl is interpreted as follows: |
| 99 | */ |
| 100 | #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ |
| 101 | #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF |
| 102 | #define ASYNC_EVENT_CODE_LINK_STATE 0x1 |
| 103 | struct be_async_event_trailer { |
| 104 | u32 code; |
| 105 | }; |
| 106 | |
| 107 | enum { |
| 108 | ASYNC_EVENT_LINK_DOWN = 0x0, |
| 109 | ASYNC_EVENT_LINK_UP = 0x1 |
| 110 | }; |
| 111 | |
| 112 | /** |
| 113 | * When the event code of an async trailer is link-state, the mcc_compl |
| 114 | * must be interpreted as follows |
| 115 | */ |
| 116 | struct be_async_event_link_state { |
| 117 | u8 physical_port; |
| 118 | u8 port_link_status; |
| 119 | u8 port_duplex; |
| 120 | u8 port_speed; |
| 121 | u8 port_fault; |
| 122 | u8 rsvd0[7]; |
| 123 | struct be_async_event_trailer trailer; |
| 124 | } __packed; |
| 125 | |
| 126 | struct be_mcc_mailbox { |
| 127 | struct be_mcc_wrb wrb; |
| 128 | struct be_mcc_compl compl; |
| 129 | }; |
| 130 | |
| 131 | /* Type of subsystems supported by FW */ |
| 132 | #define CMD_SUBSYSTEM_COMMON 0x1 |
| 133 | #define CMD_SUBSYSTEM_ISCSI 0x2 |
| 134 | #define CMD_SUBSYSTEM_ETH 0x3 |
| 135 | #define CMD_SUBSYSTEM_ISCSI_INI 0x6 |
| 136 | #define CMD_COMMON_TCP_UPLOAD 0x1 |
| 137 | |
| 138 | /** |
| 139 | * List of common opcodes subsystem CMD_SUBSYSTEM_COMMON |
| 140 | * These opcodes are unique for each subsystem defined above |
| 141 | */ |
| 142 | #define OPCODE_COMMON_CQ_CREATE 12 |
| 143 | #define OPCODE_COMMON_EQ_CREATE 13 |
| 144 | #define OPCODE_COMMON_MCC_CREATE 21 |
| 145 | #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 |
| 146 | #define OPCODE_COMMON_GET_FW_VERSION 35 |
| 147 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 |
| 148 | #define OPCODE_COMMON_FIRMWARE_CONFIG 42 |
| 149 | #define OPCODE_COMMON_MCC_DESTROY 53 |
| 150 | #define OPCODE_COMMON_CQ_DESTROY 54 |
| 151 | #define OPCODE_COMMON_EQ_DESTROY 55 |
| 152 | #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 |
| 153 | #define OPCODE_COMMON_FUNCTION_RESET 61 |
| 154 | |
| 155 | /** |
| 156 | * LIST of opcodes that are common between Initiator and Target |
| 157 | * used by CMD_SUBSYSTEM_ISCSI |
| 158 | * These opcodes are unique for each subsystem defined above |
| 159 | */ |
| 160 | #define OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES 2 |
| 161 | #define OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES 3 |
| 162 | #define OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG 7 |
| 163 | #define OPCODE_COMMON_ISCSI_SET_FRAGNUM_BITS_FOR_SGL_CRA 61 |
| 164 | #define OPCODE_COMMON_ISCSI_DEFQ_CREATE 64 |
| 165 | #define OPCODE_COMMON_ISCSI_DEFQ_DESTROY 65 |
| 166 | #define OPCODE_COMMON_ISCSI_WRBQ_CREATE 66 |
| 167 | #define OPCODE_COMMON_ISCSI_WRBQ_DESTROY 67 |
| 168 | |
| 169 | struct be_cmd_req_hdr { |
| 170 | u8 opcode; /* dword 0 */ |
| 171 | u8 subsystem; /* dword 0 */ |
| 172 | u8 port_number; /* dword 0 */ |
| 173 | u8 domain; /* dword 0 */ |
| 174 | u32 timeout; /* dword 1 */ |
| 175 | u32 request_length; /* dword 2 */ |
| 176 | u32 rsvd; /* dword 3 */ |
| 177 | }; |
| 178 | |
| 179 | struct be_cmd_resp_hdr { |
| 180 | u32 info; /* dword 0 */ |
| 181 | u32 status; /* dword 1 */ |
| 182 | u32 response_length; /* dword 2 */ |
| 183 | u32 actual_resp_len; /* dword 3 */ |
| 184 | }; |
| 185 | |
| 186 | struct phys_addr { |
| 187 | u32 lo; |
| 188 | u32 hi; |
| 189 | }; |
| 190 | |
| 191 | /************************** |
| 192 | * BE Command definitions * |
| 193 | **************************/ |
| 194 | |
| 195 | /** |
| 196 | * Pseudo amap definition in which each bit of the actual structure is defined |
| 197 | * as a byte - used to calculate offset/shift/mask of each field |
| 198 | */ |
| 199 | struct amap_eq_context { |
| 200 | u8 cidx[13]; /* dword 0 */ |
| 201 | u8 rsvd0[3]; /* dword 0 */ |
| 202 | u8 epidx[13]; /* dword 0 */ |
| 203 | u8 valid; /* dword 0 */ |
| 204 | u8 rsvd1; /* dword 0 */ |
| 205 | u8 size; /* dword 0 */ |
| 206 | u8 pidx[13]; /* dword 1 */ |
| 207 | u8 rsvd2[3]; /* dword 1 */ |
| 208 | u8 pd[10]; /* dword 1 */ |
| 209 | u8 count[3]; /* dword 1 */ |
| 210 | u8 solevent; /* dword 1 */ |
| 211 | u8 stalled; /* dword 1 */ |
| 212 | u8 armed; /* dword 1 */ |
| 213 | u8 rsvd3[4]; /* dword 2 */ |
| 214 | u8 func[8]; /* dword 2 */ |
| 215 | u8 rsvd4; /* dword 2 */ |
| 216 | u8 delaymult[10]; /* dword 2 */ |
| 217 | u8 rsvd5[2]; /* dword 2 */ |
| 218 | u8 phase[2]; /* dword 2 */ |
| 219 | u8 nodelay; /* dword 2 */ |
| 220 | u8 rsvd6[4]; /* dword 2 */ |
| 221 | u8 rsvd7[32]; /* dword 3 */ |
| 222 | } __packed; |
| 223 | |
| 224 | struct be_cmd_req_eq_create { |
| 225 | struct be_cmd_req_hdr hdr; /* dw[4] */ |
| 226 | u16 num_pages; /* sword */ |
| 227 | u16 rsvd0; /* sword */ |
| 228 | u8 context[sizeof(struct amap_eq_context) / 8]; /* dw[4] */ |
| 229 | struct phys_addr pages[8]; |
| 230 | } __packed; |
| 231 | |
| 232 | struct be_cmd_resp_eq_create { |
| 233 | struct be_cmd_resp_hdr resp_hdr; |
| 234 | u16 eq_id; /* sword */ |
| 235 | u16 rsvd0; /* sword */ |
| 236 | } __packed; |
| 237 | |
| 238 | struct mac_addr { |
| 239 | u16 size_of_struct; |
| 240 | u8 addr[ETH_ALEN]; |
| 241 | } __packed; |
| 242 | |
| 243 | struct be_cmd_req_mac_query { |
| 244 | struct be_cmd_req_hdr hdr; |
| 245 | u8 type; |
| 246 | u8 permanent; |
| 247 | u16 if_id; |
| 248 | } __packed; |
| 249 | |
| 250 | struct be_cmd_resp_mac_query { |
| 251 | struct be_cmd_resp_hdr hdr; |
| 252 | struct mac_addr mac; |
| 253 | }; |
| 254 | |
| 255 | /******************** Create CQ ***************************/ |
| 256 | /** |
| 257 | * Pseudo amap definition in which each bit of the actual structure is defined |
| 258 | * as a byte - used to calculate offset/shift/mask of each field |
| 259 | */ |
| 260 | struct amap_cq_context { |
| 261 | u8 cidx[11]; /* dword 0 */ |
| 262 | u8 rsvd0; /* dword 0 */ |
| 263 | u8 coalescwm[2]; /* dword 0 */ |
| 264 | u8 nodelay; /* dword 0 */ |
| 265 | u8 epidx[11]; /* dword 0 */ |
| 266 | u8 rsvd1; /* dword 0 */ |
| 267 | u8 count[2]; /* dword 0 */ |
| 268 | u8 valid; /* dword 0 */ |
| 269 | u8 solevent; /* dword 0 */ |
| 270 | u8 eventable; /* dword 0 */ |
| 271 | u8 pidx[11]; /* dword 1 */ |
| 272 | u8 rsvd2; /* dword 1 */ |
| 273 | u8 pd[10]; /* dword 1 */ |
| 274 | u8 eqid[8]; /* dword 1 */ |
| 275 | u8 stalled; /* dword 1 */ |
| 276 | u8 armed; /* dword 1 */ |
| 277 | u8 rsvd3[4]; /* dword 2 */ |
| 278 | u8 func[8]; /* dword 2 */ |
| 279 | u8 rsvd4[20]; /* dword 2 */ |
| 280 | u8 rsvd5[32]; /* dword 3 */ |
| 281 | } __packed; |
| 282 | |
| 283 | struct be_cmd_req_cq_create { |
| 284 | struct be_cmd_req_hdr hdr; |
| 285 | u16 num_pages; |
| 286 | u16 rsvd0; |
| 287 | u8 context[sizeof(struct amap_cq_context) / 8]; |
| 288 | struct phys_addr pages[4]; |
| 289 | } __packed; |
| 290 | |
| 291 | struct be_cmd_resp_cq_create { |
| 292 | struct be_cmd_resp_hdr hdr; |
| 293 | u16 cq_id; |
| 294 | u16 rsvd0; |
| 295 | } __packed; |
| 296 | |
| 297 | /******************** Create MCCQ ***************************/ |
| 298 | /** |
| 299 | * Pseudo amap definition in which each bit of the actual structure is defined |
| 300 | * as a byte - used to calculate offset/shift/mask of each field |
| 301 | */ |
| 302 | struct amap_mcc_context { |
| 303 | u8 con_index[14]; |
| 304 | u8 rsvd0[2]; |
| 305 | u8 ring_size[4]; |
| 306 | u8 fetch_wrb; |
| 307 | u8 fetch_r2t; |
| 308 | u8 cq_id[10]; |
| 309 | u8 prod_index[14]; |
| 310 | u8 fid[8]; |
| 311 | u8 pdid[9]; |
| 312 | u8 valid; |
| 313 | u8 rsvd1[32]; |
| 314 | u8 rsvd2[32]; |
| 315 | } __packed; |
| 316 | |
| 317 | struct be_cmd_req_mcc_create { |
| 318 | struct be_cmd_req_hdr hdr; |
| 319 | u16 num_pages; |
| 320 | u16 rsvd0; |
| 321 | u8 context[sizeof(struct amap_mcc_context) / 8]; |
| 322 | struct phys_addr pages[8]; |
| 323 | } __packed; |
| 324 | |
| 325 | struct be_cmd_resp_mcc_create { |
| 326 | struct be_cmd_resp_hdr hdr; |
| 327 | u16 id; |
| 328 | u16 rsvd0; |
| 329 | } __packed; |
| 330 | |
| 331 | /******************** Q Destroy ***************************/ |
| 332 | /* Type of Queue to be destroyed */ |
| 333 | enum { |
| 334 | QTYPE_EQ = 1, |
| 335 | QTYPE_CQ, |
| 336 | QTYPE_MCCQ, |
| 337 | QTYPE_WRBQ, |
| 338 | QTYPE_DPDUQ, |
| 339 | QTYPE_SGL |
| 340 | }; |
| 341 | |
| 342 | struct be_cmd_req_q_destroy { |
| 343 | struct be_cmd_req_hdr hdr; |
| 344 | u16 id; |
| 345 | u16 bypass_flush; /* valid only for rx q destroy */ |
| 346 | } __packed; |
| 347 | |
| 348 | struct macaddr { |
| 349 | u8 byte[ETH_ALEN]; |
| 350 | }; |
| 351 | |
| 352 | struct be_cmd_req_mcast_mac_config { |
| 353 | struct be_cmd_req_hdr hdr; |
| 354 | u16 num_mac; |
| 355 | u8 promiscuous; |
| 356 | u8 interface_id; |
| 357 | struct macaddr mac[32]; |
| 358 | } __packed; |
| 359 | |
| 360 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) |
| 361 | { |
| 362 | return wrb->payload.embedded_payload; |
| 363 | } |
| 364 | |
| 365 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) |
| 366 | { |
| 367 | return &wrb->payload.sgl[0]; |
| 368 | } |
| 369 | |
| 370 | /******************** Modify EQ Delay *******************/ |
| 371 | struct be_cmd_req_modify_eq_delay { |
| 372 | struct be_cmd_req_hdr hdr; |
| 373 | u32 num_eq; |
| 374 | struct { |
| 375 | u32 eq_id; |
| 376 | u32 phase; |
| 377 | u32 delay_multiplier; |
| 378 | } delay[8]; |
| 379 | } __packed; |
| 380 | |
| 381 | /******************** Get MAC ADDR *******************/ |
| 382 | |
| 383 | #define ETH_ALEN 6 |
| 384 | |
| 385 | |
| 386 | struct be_cmd_req_get_mac_addr { |
| 387 | struct be_cmd_req_hdr hdr; |
| 388 | u32 nic_port_count; |
| 389 | u32 speed; |
| 390 | u32 max_speed; |
| 391 | u32 link_state; |
| 392 | u32 max_frame_size; |
| 393 | u16 size_of_structure; |
| 394 | u8 mac_address[ETH_ALEN]; |
| 395 | u32 rsvd[23]; |
| 396 | }; |
| 397 | |
| 398 | struct be_cmd_resp_get_mac_addr { |
| 399 | struct be_cmd_resp_hdr hdr; |
| 400 | u32 nic_port_count; |
| 401 | u32 speed; |
| 402 | u32 max_speed; |
| 403 | u32 link_state; |
| 404 | u32 max_frame_size; |
| 405 | u16 size_of_structure; |
| 406 | u8 mac_address[6]; |
| 407 | u32 rsvd[23]; |
| 408 | }; |
| 409 | |
| 410 | int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, |
| 411 | struct be_queue_info *eq, int eq_delay); |
| 412 | |
| 413 | int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, |
| 414 | struct be_queue_info *cq, struct be_queue_info *eq, |
| 415 | bool sol_evts, bool no_delay, |
| 416 | int num_cqe_dma_coalesce); |
| 417 | |
| 418 | int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, |
| 419 | int type); |
| 420 | int be_poll_mcc(struct be_ctrl_info *ctrl); |
| 421 | unsigned char mgmt_check_supported_fw(struct be_ctrl_info *ctrl); |
| 422 | int be_cmd_get_mac_addr(struct be_ctrl_info *ctrl, u8 *mac_addr); |
| 423 | |
| 424 | /*ISCSI Functuions */ |
| 425 | int be_cmd_fw_initialize(struct be_ctrl_info *ctrl); |
| 426 | |
| 427 | struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem); |
| 428 | |
| 429 | int be_mbox_notify(struct be_ctrl_info *ctrl); |
| 430 | |
| 431 | int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, |
| 432 | struct be_queue_info *cq, |
| 433 | struct be_queue_info *dq, int length, |
| 434 | int entry_size); |
| 435 | |
| 436 | int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl, |
| 437 | struct be_dma_mem *q_mem, u32 page_offset, |
| 438 | u32 num_pages); |
| 439 | |
| 440 | int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem, |
| 441 | struct be_queue_info *wrbq); |
| 442 | |
| 443 | struct be_default_pdu_context { |
| 444 | u32 dw[4]; |
| 445 | } __packed; |
| 446 | |
| 447 | struct amap_be_default_pdu_context { |
| 448 | u8 dbuf_cindex[13]; /* dword 0 */ |
| 449 | u8 rsvd0[3]; /* dword 0 */ |
| 450 | u8 ring_size[4]; /* dword 0 */ |
| 451 | u8 ring_state[4]; /* dword 0 */ |
| 452 | u8 rsvd1[8]; /* dword 0 */ |
| 453 | u8 dbuf_pindex[13]; /* dword 1 */ |
| 454 | u8 rsvd2; /* dword 1 */ |
| 455 | u8 pci_func_id[8]; /* dword 1 */ |
| 456 | u8 rx_pdid[9]; /* dword 1 */ |
| 457 | u8 rx_pdid_valid; /* dword 1 */ |
| 458 | u8 default_buffer_size[16]; /* dword 2 */ |
| 459 | u8 cq_id_recv[10]; /* dword 2 */ |
| 460 | u8 rx_pdid_not_valid; /* dword 2 */ |
| 461 | u8 rsvd3[5]; /* dword 2 */ |
| 462 | u8 rsvd4[32]; /* dword 3 */ |
| 463 | } __packed; |
| 464 | |
| 465 | struct be_defq_create_req { |
| 466 | struct be_cmd_req_hdr hdr; |
| 467 | u16 num_pages; |
| 468 | u8 ulp_num; |
| 469 | u8 rsvd0; |
| 470 | struct be_default_pdu_context context; |
| 471 | struct phys_addr pages[8]; |
| 472 | } __packed; |
| 473 | |
| 474 | struct be_defq_create_resp { |
| 475 | struct be_cmd_req_hdr hdr; |
| 476 | u16 id; |
| 477 | u16 rsvd0; |
| 478 | } __packed; |
| 479 | |
| 480 | struct be_post_sgl_pages_req { |
| 481 | struct be_cmd_req_hdr hdr; |
| 482 | u16 num_pages; |
| 483 | u16 page_offset; |
| 484 | u32 rsvd0; |
| 485 | struct phys_addr pages[26]; |
| 486 | u32 rsvd1; |
| 487 | } __packed; |
| 488 | |
| 489 | struct be_wrbq_create_req { |
| 490 | struct be_cmd_req_hdr hdr; |
| 491 | u16 num_pages; |
| 492 | u8 ulp_num; |
| 493 | u8 rsvd0; |
| 494 | struct phys_addr pages[8]; |
| 495 | } __packed; |
| 496 | |
| 497 | struct be_wrbq_create_resp { |
| 498 | struct be_cmd_resp_hdr resp_hdr; |
| 499 | u16 cid; |
| 500 | u16 rsvd0; |
| 501 | } __packed; |
| 502 | |
| 503 | #define SOL_CID_MASK 0x0000FFC0 |
| 504 | #define SOL_CODE_MASK 0x0000003F |
| 505 | #define SOL_WRB_INDEX_MASK 0x00FF0000 |
| 506 | #define SOL_CMD_WND_MASK 0xFF000000 |
| 507 | #define SOL_RES_CNT_MASK 0x7FFFFFFF |
| 508 | #define SOL_EXP_CMD_SN_MASK 0xFFFFFFFF |
| 509 | #define SOL_HW_STS_MASK 0x000000FF |
| 510 | #define SOL_STS_MASK 0x0000FF00 |
| 511 | #define SOL_RESP_MASK 0x00FF0000 |
| 512 | #define SOL_FLAGS_MASK 0x7F000000 |
| 513 | #define SOL_S_MASK 0x80000000 |
| 514 | |
| 515 | struct sol_cqe { |
| 516 | u32 dw[4]; |
| 517 | }; |
| 518 | |
| 519 | struct amap_sol_cqe { |
| 520 | u8 hw_sts[8]; /* dword 0 */ |
| 521 | u8 i_sts[8]; /* dword 0 */ |
| 522 | u8 i_resp[8]; /* dword 0 */ |
| 523 | u8 i_flags[7]; /* dword 0 */ |
| 524 | u8 s; /* dword 0 */ |
| 525 | u8 i_exp_cmd_sn[32]; /* dword 1 */ |
| 526 | u8 code[6]; /* dword 2 */ |
| 527 | u8 cid[10]; /* dword 2 */ |
| 528 | u8 wrb_index[8]; /* dword 2 */ |
| 529 | u8 i_cmd_wnd[8]; /* dword 2 */ |
| 530 | u8 i_res_cnt[31]; /* dword 3 */ |
| 531 | u8 valid; /* dword 3 */ |
| 532 | } __packed; |
| 533 | |
| 534 | |
| 535 | /** |
| 536 | * Post WRB Queue Doorbell Register used by the host Storage |
| 537 | * stack to notify the |
| 538 | * controller of a posted Work Request Block |
| 539 | */ |
| 540 | #define DB_WRB_POST_CID_MASK 0x3FF /* bits 0 - 9 */ |
| 541 | #define DB_DEF_PDU_WRB_INDEX_MASK 0xFF /* bits 0 - 9 */ |
| 542 | |
| 543 | #define DB_DEF_PDU_WRB_INDEX_SHIFT 16 |
| 544 | #define DB_DEF_PDU_NUM_POSTED_SHIFT 24 |
| 545 | |
| 546 | struct fragnum_bits_for_sgl_cra_in { |
| 547 | struct be_cmd_req_hdr hdr; |
| 548 | u32 num_bits; |
| 549 | } __packed; |
| 550 | |
| 551 | struct iscsi_cleanup_req { |
| 552 | struct be_cmd_req_hdr hdr; |
| 553 | u16 chute; |
| 554 | u8 hdr_ring_id; |
| 555 | u8 data_ring_id; |
| 556 | |
| 557 | } __packed; |
| 558 | |
| 559 | struct eq_delay { |
| 560 | u32 eq_id; |
| 561 | u32 phase; |
| 562 | u32 delay_multiplier; |
| 563 | } __packed; |
| 564 | |
| 565 | struct be_eq_delay_params_in { |
| 566 | struct be_cmd_req_hdr hdr; |
| 567 | u32 num_eq; |
| 568 | struct eq_delay delay[8]; |
| 569 | } __packed; |
| 570 | |
| 571 | struct ip_address_format { |
| 572 | u16 size_of_structure; |
| 573 | u8 reserved; |
| 574 | u8 ip_type; |
| 575 | u8 ip_address[16]; |
| 576 | u32 rsvd0; |
| 577 | } __packed; |
| 578 | |
| 579 | struct tcp_connect_and_offload_in { |
| 580 | struct be_cmd_req_hdr hdr; |
| 581 | struct ip_address_format ip_address; |
| 582 | u16 tcp_port; |
| 583 | u16 cid; |
| 584 | u16 cq_id; |
| 585 | u16 defq_id; |
| 586 | struct phys_addr dataout_template_pa; |
| 587 | u16 hdr_ring_id; |
| 588 | u16 data_ring_id; |
| 589 | u8 do_offload; |
| 590 | u8 rsvd0[3]; |
| 591 | } __packed; |
| 592 | |
| 593 | struct tcp_connect_and_offload_out { |
| 594 | struct be_cmd_resp_hdr hdr; |
| 595 | u32 connection_handle; |
| 596 | u16 cid; |
| 597 | u16 rsvd0; |
| 598 | |
| 599 | } __packed; |
| 600 | |
| 601 | struct be_mcc_wrb_context { |
| 602 | struct MCC_WRB *wrb; |
| 603 | int *users_final_status; |
| 604 | } __packed; |
| 605 | |
| 606 | #define DB_DEF_PDU_RING_ID_MASK 0x3FF /* bits 0 - 9 */ |
| 607 | #define DB_DEF_PDU_CQPROC_MASK 0x3FFF /* bits 0 - 9 */ |
| 608 | #define DB_DEF_PDU_REARM_SHIFT 14 |
| 609 | #define DB_DEF_PDU_EVENT_SHIFT 15 |
| 610 | #define DB_DEF_PDU_CQPROC_SHIFT 16 |
| 611 | |
| 612 | struct dmsg_cqe { |
| 613 | u32 dw[4]; |
| 614 | } __packed; |
| 615 | |
| 616 | struct tcp_upload_params_in { |
| 617 | struct be_cmd_req_hdr hdr; |
| 618 | u16 id; |
| 619 | u16 upload_type; |
| 620 | u32 reset_seq; |
| 621 | } __packed; |
| 622 | |
| 623 | struct tcp_upload_params_out { |
| 624 | u32 dw[32]; |
| 625 | } __packed; |
| 626 | |
| 627 | union tcp_upload_params { |
| 628 | struct tcp_upload_params_in request; |
| 629 | struct tcp_upload_params_out response; |
| 630 | } __packed; |
| 631 | |
| 632 | struct be_ulp_fw_cfg { |
| 633 | u32 ulp_mode; |
| 634 | u32 etx_base; |
| 635 | u32 etx_count; |
| 636 | u32 sq_base; |
| 637 | u32 sq_count; |
| 638 | u32 rq_base; |
| 639 | u32 rq_count; |
| 640 | u32 dq_base; |
| 641 | u32 dq_count; |
| 642 | u32 lro_base; |
| 643 | u32 lro_count; |
| 644 | u32 icd_base; |
| 645 | u32 icd_count; |
| 646 | }; |
| 647 | |
| 648 | struct be_fw_cfg { |
| 649 | struct be_cmd_req_hdr hdr; |
| 650 | u32 be_config_number; |
| 651 | u32 asic_revision; |
| 652 | u32 phys_port; |
| 653 | u32 function_mode; |
| 654 | struct be_ulp_fw_cfg ulp[2]; |
| 655 | u32 function_caps; |
| 656 | } __packed; |
| 657 | |
| 658 | #define CMD_ISCSI_COMMAND_INVALIDATE 1 |
| 659 | #define ISCSI_OPCODE_SCSI_DATA_OUT 5 |
| 660 | #define OPCODE_COMMON_ISCSI_TCP_CONNECT_AND_OFFLOAD 70 |
| 661 | #define OPCODE_ISCSI_INI_DRIVER_OFFLOAD_SESSION 41 |
| 662 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 |
| 663 | #define OPCODE_COMMON_ISCSI_CLEANUP 59 |
| 664 | #define OPCODE_COMMON_TCP_UPLOAD 56 |
| 665 | #define OPCODE_COMMON_ISCSI_ERROR_RECOVERY_INVALIDATE_COMMANDS 1 |
| 666 | /* --- CMD_ISCSI_INVALIDATE_CONNECTION_TYPE --- */ |
| 667 | #define CMD_ISCSI_CONNECTION_INVALIDATE 1 |
| 668 | #define CMD_ISCSI_CONNECTION_ISSUE_TCP_RST 2 |
| 669 | #define OPCODE_ISCSI_INI_DRIVER_INVALIDATE_CONNECTION 42 |
| 670 | |
| 671 | #define INI_WR_CMD 1 /* Initiator write command */ |
| 672 | #define INI_TMF_CMD 2 /* Initiator TMF command */ |
| 673 | #define INI_NOPOUT_CMD 3 /* Initiator; Send a NOP-OUT */ |
| 674 | #define INI_RD_CMD 5 /* Initiator requesting to send |
| 675 | * a read command |
| 676 | */ |
| 677 | #define TGT_CTX_UPDT_CMD 7 /* Target context update */ |
| 678 | #define TGT_STS_CMD 8 /* Target R2T and other BHS |
| 679 | * where only the status number |
| 680 | * need to be updated |
| 681 | */ |
| 682 | #define TGT_DATAIN_CMD 9 /* Target Data-Ins in response |
| 683 | * to read command |
| 684 | */ |
| 685 | #define TGT_SOS_PDU 10 /* Target:standalone status |
| 686 | * response |
| 687 | */ |
| 688 | #define TGT_DM_CMD 11 /* Indicates that the bhs |
| 689 | * preparedby |
| 690 | * driver should not be touched |
| 691 | */ |
| 692 | /* --- CMD_CHUTE_TYPE --- */ |
| 693 | #define CMD_CONNECTION_CHUTE_0 1 |
| 694 | #define CMD_CONNECTION_CHUTE_1 2 |
| 695 | #define CMD_CONNECTION_CHUTE_2 3 |
| 696 | |
| 697 | #define EQ_MAJOR_CODE_COMPLETION 0 |
| 698 | |
| 699 | #define CMD_ISCSI_SESSION_DEL_CFG_FROM_FLASH 0 |
| 700 | #define CMD_ISCSI_SESSION_SAVE_CFG_ON_FLASH 1 |
| 701 | |
| 702 | /* --- CONNECTION_UPLOAD_PARAMS --- */ |
| 703 | /* These parameters are used to define the type of upload desired. */ |
| 704 | #define CONNECTION_UPLOAD_GRACEFUL 1 /* Graceful upload */ |
| 705 | #define CONNECTION_UPLOAD_ABORT_RESET 2 /* Abortive upload with |
| 706 | * reset |
| 707 | */ |
| 708 | #define CONNECTION_UPLOAD_ABORT 3 /* Abortive upload without |
| 709 | * reset |
| 710 | */ |
| 711 | #define CONNECTION_UPLOAD_ABORT_WITH_SEQ 4 /* Abortive upload with reset, |
| 712 | * sequence number by driver */ |
| 713 | |
| 714 | /* Returns byte size of given field with a structure. */ |
| 715 | |
| 716 | /* Returns the number of items in the field array. */ |
| 717 | #define BE_NUMBER_OF_FIELD(_type_, _field_) \ |
| 718 | (FIELD_SIZEOF(_type_, _field_)/sizeof((((_type_ *)0)->_field_[0])))\ |
| 719 | |
| 720 | /** |
| 721 | * Different types of iSCSI completions to host driver for both initiator |
| 722 | * and taget mode |
| 723 | * of operation. |
| 724 | */ |
| 725 | #define SOL_CMD_COMPLETE 1 /* Solicited command completed |
| 726 | * normally |
| 727 | */ |
| 728 | #define SOL_CMD_KILLED_DATA_DIGEST_ERR 2 /* Solicited command got |
| 729 | * invalidated internally due |
| 730 | * to Data Digest error |
| 731 | */ |
| 732 | #define CXN_KILLED_PDU_SIZE_EXCEEDS_DSL 3 /* Connection got invalidated |
| 733 | * internally |
| 734 | * due to a recieved PDU |
| 735 | * size > DSL |
| 736 | */ |
| 737 | #define CXN_KILLED_BURST_LEN_MISMATCH 4 /* Connection got invalidated |
| 738 | * internally due ti received |
| 739 | * PDU sequence size > |
| 740 | * FBL/MBL. |
| 741 | */ |
| 742 | #define CXN_KILLED_AHS_RCVD 5 /* Connection got invalidated |
| 743 | * internally due to a recieved |
| 744 | * PDU Hdr that has |
| 745 | * AHS */ |
| 746 | #define CXN_KILLED_HDR_DIGEST_ERR 6 /* Connection got invalidated |
| 747 | * internally due to Hdr Digest |
| 748 | * error |
| 749 | */ |
| 750 | #define CXN_KILLED_UNKNOWN_HDR 7 /* Connection got invalidated |
| 751 | * internally |
| 752 | * due to a bad opcode in the |
| 753 | * pdu hdr |
| 754 | */ |
| 755 | #define CXN_KILLED_STALE_ITT_TTT_RCVD 8 /* Connection got invalidated |
| 756 | * internally due to a recieved |
| 757 | * ITT/TTT that does not belong |
| 758 | * to this Connection |
| 759 | */ |
| 760 | #define CXN_KILLED_INVALID_ITT_TTT_RCVD 9 /* Connection got invalidated |
| 761 | * internally due to recieved |
| 762 | * ITT/TTT value > Max |
| 763 | * Supported ITTs/TTTs |
| 764 | */ |
| 765 | #define CXN_KILLED_RST_RCVD 10 /* Connection got invalidated |
| 766 | * internally due to an |
| 767 | * incoming TCP RST |
| 768 | */ |
| 769 | #define CXN_KILLED_TIMED_OUT 11 /* Connection got invalidated |
| 770 | * internally due to timeout on |
| 771 | * tcp segment 12 retransmit |
| 772 | * attempts failed |
| 773 | */ |
| 774 | #define CXN_KILLED_RST_SENT 12 /* Connection got invalidated |
| 775 | * internally due to TCP RST |
| 776 | * sent by the Tx side |
| 777 | */ |
| 778 | #define CXN_KILLED_FIN_RCVD 13 /* Connection got invalidated |
| 779 | * internally due to an |
| 780 | * incoming TCP FIN. |
| 781 | */ |
| 782 | #define CXN_KILLED_BAD_UNSOL_PDU_RCVD 14 /* Connection got invalidated |
| 783 | * internally due to bad |
| 784 | * unsolicited PDU Unsolicited |
| 785 | * PDUs are PDUs with |
| 786 | * ITT=0xffffffff |
| 787 | */ |
| 788 | #define CXN_KILLED_BAD_WRB_INDEX_ERROR 15 /* Connection got invalidated |
| 789 | * internally due to bad WRB |
| 790 | * index. |
| 791 | */ |
| 792 | #define CXN_KILLED_OVER_RUN_RESIDUAL 16 /* Command got invalidated |
| 793 | * internally due to recived |
| 794 | * command has residual |
| 795 | * over run bytes. |
| 796 | */ |
| 797 | #define CXN_KILLED_UNDER_RUN_RESIDUAL 17 /* Command got invalidated |
| 798 | * internally due to recived |
| 799 | * command has residual under |
| 800 | * run bytes. |
| 801 | */ |
| 802 | #define CMD_KILLED_INVALID_STATSN_RCVD 18 /* Command got invalidated |
| 803 | * internally due to a recieved |
| 804 | * PDU has an invalid StatusSN |
| 805 | */ |
| 806 | #define CMD_KILLED_INVALID_R2T_RCVD 19 /* Command got invalidated |
| 807 | * internally due to a recieved |
| 808 | * an R2T with some invalid |
| 809 | * fields in it |
| 810 | */ |
| 811 | #define CMD_CXN_KILLED_LUN_INVALID 20 /* Command got invalidated |
| 812 | * internally due to received |
| 813 | * PDU has an invalid LUN. |
| 814 | */ |
| 815 | #define CMD_CXN_KILLED_ICD_INVALID 21 /* Command got invalidated |
| 816 | * internally due to the |
| 817 | * corresponding ICD not in a |
| 818 | * valid state |
| 819 | */ |
| 820 | #define CMD_CXN_KILLED_ITT_INVALID 22 /* Command got invalidated due |
| 821 | * to received PDU has an |
| 822 | * invalid ITT. |
| 823 | */ |
| 824 | #define CMD_CXN_KILLED_SEQ_OUTOFORDER 23 /* Command got invalidated due |
| 825 | * to received sequence buffer |
| 826 | * offset is out of order. |
| 827 | */ |
| 828 | #define CMD_CXN_KILLED_INVALID_DATASN_RCVD 24 /* Command got invalidated |
| 829 | * internally due to a |
| 830 | * recieved PDU has an invalid |
| 831 | * DataSN |
| 832 | */ |
| 833 | #define CXN_INVALIDATE_NOTIFY 25 /* Connection invalidation |
| 834 | * completion notify. |
| 835 | */ |
| 836 | #define CXN_INVALIDATE_INDEX_NOTIFY 26 /* Connection invalidation |
| 837 | * completion |
| 838 | * with data PDU index. |
| 839 | */ |
| 840 | #define CMD_INVALIDATED_NOTIFY 27 /* Command invalidation |
| 841 | * completionnotifify. |
| 842 | */ |
| 843 | #define UNSOL_HDR_NOTIFY 28 /* Unsolicited header notify.*/ |
| 844 | #define UNSOL_DATA_NOTIFY 29 /* Unsolicited data notify.*/ |
| 845 | #define UNSOL_DATA_DIGEST_ERROR_NOTIFY 30 /* Unsolicited data digest |
| 846 | * error notify. |
| 847 | */ |
| 848 | #define DRIVERMSG_NOTIFY 31 /* TCP acknowledge based |
| 849 | * notification. |
| 850 | */ |
| 851 | #define CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN 32 /* Connection got invalidated |
| 852 | * internally due to command |
| 853 | * and data are not on same |
| 854 | * connection. |
| 855 | */ |
| 856 | #define SOL_CMD_KILLED_DIF_ERR 33 /* Solicited command got |
| 857 | * invalidated internally due |
| 858 | * to DIF error |
| 859 | */ |
| 860 | #define CXN_KILLED_SYN_RCVD 34 /* Connection got invalidated |
| 861 | * internally due to incoming |
| 862 | * TCP SYN |
| 863 | */ |
| 864 | #define CXN_KILLED_IMM_DATA_RCVD 35 /* Connection got invalidated |
| 865 | * internally due to an |
| 866 | * incoming Unsolicited PDU |
| 867 | * that has immediate data on |
| 868 | * the cxn |
| 869 | */ |
| 870 | |
| 871 | void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, |
| 872 | bool embedded, u8 sge_cnt); |
| 873 | |
| 874 | void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, |
| 875 | u8 subsystem, u8 opcode, int cmd_len); |
| 876 | |
| 877 | #endif /* !BEISCSI_CMDS_H */ |