blob: 975dad21ac3890d4b81bb23a0d1bf2962a831e09 [file] [log] [blame]
Haojian Zhuang10d77ec2012-03-01 13:26:15 +08001/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080021 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
26 ranges;
27
Haojian Zhuangff290fc2012-04-19 18:44:50 +080028 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 reg = <0xd4200000 0x00200000>;
33 ranges;
34
35 intc: interrupt-controller@d4282000 {
36 compatible = "mrvl,mmp-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xd4282000 0x1000>;
40 mrvl,intc-nr-irqs = <64>;
41 };
42
43 };
44
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080045 apb@d4000000 { /* APB */
46 compatible = "mrvl,apb-bus", "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0xd4000000 0x00200000>;
50 ranges;
51
Haojian Zhuangff290fc2012-04-19 18:44:50 +080052 timer0: timer@d4014000 {
53 compatible = "mrvl,mmp-timer";
54 reg = <0xd4014000 0x100>;
55 interrupts = <13>;
56 };
57
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080058 uart1: uart@d4017000 {
Haojian Zhuangff290fc2012-04-19 18:44:50 +080059 compatible = "mrvl,mmp-uart";
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080060 reg = <0xd4017000 0x1000>;
61 interrupts = <27>;
62 status = "disabled";
63 };
64
65 uart2: uart@d4018000 {
Haojian Zhuangff290fc2012-04-19 18:44:50 +080066 compatible = "mrvl,mmp-uart";
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080067 reg = <0xd4018000 0x1000>;
68 interrupts = <28>;
69 status = "disabled";
70 };
71
72 uart3: uart@d4026000 {
Haojian Zhuangff290fc2012-04-19 18:44:50 +080073 compatible = "mrvl,mmp-uart";
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080074 reg = <0xd4026000 0x1000>;
75 interrupts = <29>;
76 status = "disabled";
77 };
78
Haojian Zhuangff290fc2012-04-19 18:44:50 +080079 gpio@d4019000 {
Haojian Zhuangf8731172013-04-09 22:27:50 +080080 compatible = "marvell,mmp-gpio";
Haojian Zhuangff290fc2012-04-19 18:44:50 +080081 #address-cells = <1>;
82 #size-cells = <1>;
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080083 reg = <0xd4019000 0x1000>;
Haojian Zhuangff290fc2012-04-19 18:44:50 +080084 gpio-controller;
85 #gpio-cells = <2>;
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080086 interrupts = <49>;
87 interrupt-names = "gpio_mux";
Haojian Zhuang10d77ec2012-03-01 13:26:15 +080088 interrupt-controller;
89 #interrupt-cells = <1>;
Haojian Zhuangff290fc2012-04-19 18:44:50 +080090 ranges;
91
92 gcb0: gpio@d4019000 {
93 reg = <0xd4019000 0x4>;
94 };
95
96 gcb1: gpio@d4019004 {
97 reg = <0xd4019004 0x4>;
98 };
99
100 gcb2: gpio@d4019008 {
101 reg = <0xd4019008 0x4>;
102 };
103
104 gcb3: gpio@d4019100 {
105 reg = <0xd4019100 0x4>;
106 };
Haojian Zhuang10d77ec2012-03-01 13:26:15 +0800107 };
108
109 twsi1: i2c@d4011000 {
Haojian Zhuangff290fc2012-04-19 18:44:50 +0800110 compatible = "mrvl,mmp-twsi";
Haojian Zhuang10d77ec2012-03-01 13:26:15 +0800111 reg = <0xd4011000 0x1000>;
112 interrupts = <7>;
113 mrvl,i2c-fast-mode;
114 status = "disabled";
115 };
116
117 twsi2: i2c@d4025000 {
Haojian Zhuangff290fc2012-04-19 18:44:50 +0800118 compatible = "mrvl,mmp-twsi";
Haojian Zhuang10d77ec2012-03-01 13:26:15 +0800119 reg = <0xd4025000 0x1000>;
120 interrupts = <58>;
121 status = "disabled";
122 };
123
124 rtc: rtc@d4010000 {
125 compatible = "mrvl,mmp-rtc";
126 reg = <0xd4010000 0x1000>;
127 interrupts = <5 6>;
128 interrupt-names = "rtc 1Hz", "rtc alarm";
129 status = "disabled";
130 };
131 };
132 };
133};