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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-v6.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01005 * Modified by Catalin Marinas for noMMU support
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This is the "shell" of the ARMv6 processor support.
12 */
Tim Abbott991da172009-04-27 14:02:22 -040013#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/linkage.h>
15#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020016#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010017#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000018#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <asm/pgtable.h>
20
21#include "proc-macros.S"
22
23#define D_CACHE_LINE_SIZE 32
24
Russell King3747b362006-03-27 16:59:07 +010025#define TTB_C (1 << 0)
26#define TTB_S (1 << 1)
27#define TTB_IMP (1 << 2)
28#define TTB_RGN_NC (0 << 3)
29#define TTB_RGN_WBWA (1 << 3)
30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3)
32
Russell Kingf00ec482010-09-04 10:47:48 +010033#define TTB_FLAGS_UP TTB_RGN_WBWA
34#define PMD_FLAGS_UP PMD_SECT_WB
35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
Russell Kingf2131d32007-02-08 20:46:20 +000037
Linus Torvalds1da177e2005-04-16 15:20:36 -070038ENTRY(cpu_v6_proc_init)
39 mov pc, lr
40
41ENTRY(cpu_v6_proc_fin)
Tony Lindgren67c5587a2005-10-19 23:00:56 +010042 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 bic r0, r0, #0x1000 @ ...i............
44 bic r0, r0, #0x0006 @ .............ca.
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Russell King9ca03a22010-07-26 12:22:12 +010046 mov pc, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48/*
49 * cpu_v6_reset(loc)
50 *
51 * Perform a soft reset of the system. Put the CPU into the
52 * same state as it would be if it had been reset, and branch
53 * to what would be the reset vector.
54 *
55 * - loc - location to jump to for soft reset
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 */
57 .align 5
Will Deacon1a4baaf2011-11-15 13:25:04 +000058 .pushsection .idmap.text, "ax"
Linus Torvalds1da177e2005-04-16 15:20:36 -070059ENTRY(cpu_v6_reset)
Will Deaconf4daf062011-06-06 12:27:34 +010060 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
61 bic r1, r1, #0x1 @ ...............m
62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
63 mov r1, #0
64 mcr p15, 0, r1, c7, c5, 4 @ ISB
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 mov pc, r0
Will Deacon1a4baaf2011-11-15 13:25:04 +000066ENDPROC(cpu_v6_reset)
67 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69/*
70 * cpu_v6_do_idle()
71 *
72 * Idle the processor (eg, wait for interrupt).
73 *
74 * IRQs are already disabled.
75 */
76ENTRY(cpu_v6_do_idle)
Catalin Marinas8553cb62008-11-10 14:14:11 +000077 mov r1, #0
78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
80 mov pc, lr
81
82ENTRY(cpu_v6_dcache_clean_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, #D_CACHE_LINE_SIZE
85 subs r1, r1, #D_CACHE_LINE_SIZE
86 bhi 1b
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 mov pc, lr
88
89/*
Nicolas Pitre2b6e2042012-11-07 21:22:08 +010090 * cpu_v6_switch_mm(pgd_phys, tsk)
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 *
92 * Set the translation table base pointer to be pgd_phys
93 *
94 * - pgd_phys - physical address of new TTB
95 *
96 * It is assumed that:
97 * - we are not using split page tables
98 */
99ENTRY(cpu_v6_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100100#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 mov r2, #0
Ben Dooks251019f2013-02-11 12:25:05 +0100102 mmid r1, r1 @ get mm->context.id
Russell Kingf00ec482010-09-04 10:47:48 +0100103 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
104 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
Russell Kingd93742f52005-08-15 16:53:38 +0100105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
Will Deacon575320d2012-07-06 15:43:03 +0100108#ifdef CONFIG_PID_IN_CONTEXTIDR
109 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
110 bic r2, r2, #0xff @ extract the PID
111 and r1, r1, #0xff
112 orr r1, r1, r2 @ insert into new context ID
113#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100115#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 mov pc, lr
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118/*
Russell Kingad1ae2f2006-12-13 14:34:43 +0000119 * cpu_v6_set_pte_ext(ptep, pte, ext)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 *
121 * Set a level 2 translation table entry.
122 *
123 * - ptep - pointer to level 2 translation table entry
124 * (hardware version is stored at -1024 bytes)
125 * - pte - PTE value to store
Russell Kingad1ae2f2006-12-13 14:34:43 +0000126 * - ext - value for extended PTE bits
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 */
Russell King639b0ae2008-09-06 21:07:45 +0100128 armv6_mt_table cpu_v6
129
Russell Kingad1ae2f2006-12-13 14:34:43 +0000130ENTRY(cpu_v6_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100131#ifdef CONFIG_MMU
Russell King639b0ae2008-09-06 21:07:45 +0100132 armv6_set_pte_ext cpu_v6
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100133#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 mov pc, lr
135
Russell Kingf6b0fa02011-02-06 15:48:39 +0000136/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
137.globl cpu_v6_suspend_size
Russell King1aede682011-08-28 10:30:34 +0100138.equ cpu_v6_suspend_size, 4 * 6
Russell Kingb6c7aab2013-04-08 11:44:57 +0100139#ifdef CONFIG_ARM_CPU_SUSPEND
Russell Kingf6b0fa02011-02-06 15:48:39 +0000140ENTRY(cpu_v6_do_suspend)
Russell King1aede682011-08-28 10:30:34 +0100141 stmfd sp!, {r4 - r9, lr}
Russell Kingf6b0fa02011-02-06 15:48:39 +0000142 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
Will Deaconaa1aadc2012-02-23 13:51:38 +0000143#ifdef CONFIG_MMU
Russell King1aede682011-08-28 10:30:34 +0100144 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
145 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
Will Deaconaa1aadc2012-02-23 13:51:38 +0000146#endif
Russell King1aede682011-08-28 10:30:34 +0100147 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
148 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
149 mrc p15, 0, r9, c1, c0, 0 @ control register
150 stmia r0, {r4 - r9}
151 ldmfd sp!, {r4- r9, pc}
Russell Kingf6b0fa02011-02-06 15:48:39 +0000152ENDPROC(cpu_v6_do_suspend)
153
154ENTRY(cpu_v6_do_resume)
155 mov ip, #0
156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
159 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
Russell King1aede682011-08-28 10:30:34 +0100160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
161 ldmia r0, {r4 - r9}
Russell Kingf6b0fa02011-02-06 15:48:39 +0000162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
Will Deaconaa1aadc2012-02-23 13:51:38 +0000163#ifdef CONFIG_MMU
Russell King1aede682011-08-28 10:30:34 +0100164 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
Russell Kingde8e71c2011-08-27 22:39:09 +0100165 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
166 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
167 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
Russell King1aede682011-08-28 10:30:34 +0100168 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
Will Deaconaa1aadc2012-02-23 13:51:38 +0000169 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
170#endif
Russell King1aede682011-08-28 10:30:34 +0100171 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
172 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
Russell Kingf6b0fa02011-02-06 15:48:39 +0000173 mcr p15, 0, ip, c7, c5, 4 @ ISB
Russell King1aede682011-08-28 10:30:34 +0100174 mov r0, r9 @ control register
Russell Kingf6b0fa02011-02-06 15:48:39 +0000175 b cpu_resume_mmu
176ENDPROC(cpu_v6_do_resume)
Russell Kingf6b0fa02011-02-06 15:48:39 +0000177#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178
Dave Martin7b7dc6e2011-06-23 17:25:46 +0100179 string cpu_v6_name, "ARMv6-compatible processor"
Saeed Bisharaedabd382009-08-06 15:12:43 +0300180
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 .align
182
Russell King5085f3f2010-10-01 15:37:05 +0100183 __CPUINIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184
185/*
186 * __v6_setup
187 *
188 * Initialise TLB, Caches, and MMU state ready to switch the MMU
189 * on. Return in r0 the new CP15 C1 control register setting.
190 *
191 * We automatically detect if we have a Harvard cache, and use the
192 * Harvard cache control instructions insead of the unified cache
193 * control instructions.
194 *
195 * This should be able to cover all ARMv6 cores.
196 *
197 * It is assumed that:
198 * - cache type register is implemented
199 */
200__v6_setup:
Russell King862184f2005-11-07 21:05:42 +0000201#ifdef CONFIG_SMP
Russell Kingf00ec482010-09-04 10:47:48 +0100202 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
203 ALT_UP(nop)
Russell King862184f2005-11-07 21:05:42 +0000204 orr r0, r0, #0x20
Russell Kingf00ec482010-09-04 10:47:48 +0100205 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
206 ALT_UP(nop)
Russell King862184f2005-11-07 21:05:42 +0000207#endif
Russell King862184f2005-11-07 21:05:42 +0000208
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 mov r0, #0
210 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
211 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
212 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
213 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100214#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
216 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
Russell Kingf00ec482010-09-04 10:47:48 +0100217 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
218 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
Catalin Marinasd4279582011-05-26 11:22:44 +0100219 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
220 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
221 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100222#endif /* CONFIG_MMU */
Russell King22b190862006-06-29 15:09:57 +0100223 adr r5, v6_crval
224 ldmia r5, {r5, r6}
Catalin Marinas26584852009-05-30 14:00:18 +0100225#ifdef CONFIG_CPU_ENDIAN_BE8
226 orr r6, r6, #1 << 25 @ big-endian page tables
227#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 mrc p15, 0, r0, c1, c0, 0 @ read control register
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 bic r0, r0, r5 @ clear bits them
Russell King22b190862006-06-29 15:09:57 +0100230 orr r0, r0, r6 @ set them
Catalin Marinas145e10e2011-08-15 11:04:41 +0100231#ifdef CONFIG_ARM_ERRATA_364296
232 /*
233 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
234 * corruption with hit-under-miss enabled). The conditional code below
235 * (setting the undocumented bit 31 in the auxiliary control register
236 * and the FI bit in the control register) disables hit-under-miss
237 * without putting the processor into full low interrupt latency mode.
238 */
239 ldr r6, =0x4107b362 @ id for ARM1136 r0p2
240 mrc p15, 0, r5, c0, c0, 0 @ get processor id
241 teq r5, r6 @ check for the faulty core
242 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
243 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
244 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
245 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
246#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 mov pc, lr @ return to head.S:__ret
248
249 /*
250 * V X F I D LR
251 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
252 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
253 * 0 110 0011 1.00 .111 1101 < we want
254 */
Russell King22b190862006-06-29 15:09:57 +0100255 .type v6_crval, #object
256v6_crval:
257 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
Russell King5085f3f2010-10-01 15:37:05 +0100259 __INITDATA
260
Dave Martin7b7dc6e2011-06-23 17:25:46 +0100261 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
262 define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263
Russell King5085f3f2010-10-01 15:37:05 +0100264 .section ".rodata"
265
Dave Martin7b7dc6e2011-06-23 17:25:46 +0100266 string cpu_arch_name, "armv6"
267 string cpu_elf_name, "v6"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 .align
269
Ben Dooks02b7dd12005-09-20 16:35:03 +0100270 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271
272 /*
273 * Match any ARMv6 processor core.
274 */
275 .type __v6_proc_info, #object
276__v6_proc_info:
277 .long 0x0007b000
278 .long 0x0007f000
Russell Kingf00ec482010-09-04 10:47:48 +0100279 ALT_SMP(.long \
280 PMD_TYPE_SECT | \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 PMD_SECT_AP_WRITE | \
Russell King4b46d642009-11-01 17:44:24 +0000282 PMD_SECT_AP_READ | \
Russell Kingf00ec482010-09-04 10:47:48 +0100283 PMD_FLAGS_SMP)
284 ALT_UP(.long \
285 PMD_TYPE_SECT | \
286 PMD_SECT_AP_WRITE | \
287 PMD_SECT_AP_READ | \
288 PMD_FLAGS_UP)
Russell King8799ee92006-06-29 18:24:21 +0100289 .long PMD_TYPE_SECT | \
290 PMD_SECT_XN | \
291 PMD_SECT_AP_WRITE | \
292 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 b __v6_setup
294 .long cpu_arch_name
295 .long cpu_elf_name
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100296 /* See also feat_v6_fixup() for HWCAP_TLS */
297 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 .long cpu_v6_name
299 .long v6_processor_functions
300 .long v6wbi_tlb_fns
301 .long v6_user_fns
302 .long v6_cache_fns
303 .size __v6_proc_info, . - __v6_proc_info