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eric miao2c8086a2007-09-11 19:13:17 -07001/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
eric miaoe9bba8e2007-10-30 08:01:38 +01008 * 2007-09-02: eric miao <eric.miao@marvell.com>
eric miao2c8086a2007-09-11 19:13:17 -07009 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
eric miao2c8086a2007-09-11 19:13:17 -070015#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h>
20#include <linux/irq.h>
Russell King7b5dea12008-01-07 22:18:30 +000021#include <linux/io.h>
Daniel Mack82ce44d2012-07-25 17:52:52 +020022#include <linux/of.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020023#include <linux/syscore_ops.h>
Sebastian Andrzej Siewiorb4593962011-02-23 12:38:16 +010024#include <linux/i2c/pxa-i2c.h>
eric miao2c8086a2007-09-11 19:13:17 -070025
Marek Vasut851982c2010-10-11 02:20:19 +020026#include <asm/mach/map.h>
Russell King2c74a0c2011-06-22 17:41:48 +010027#include <asm/suspend.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010028#include <mach/hardware.h>
29#include <mach/pxa3xx-regs.h>
Russell Kingafd2fc02008-08-07 11:05:25 +010030#include <mach/reset.h>
Arnd Bergmann293b2da2012-08-24 15:16:48 +020031#include <linux/platform_data/usb-ohci-pxa27x.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010032#include <mach/pm.h>
33#include <mach/dma.h>
Marek Vasutad68bb92010-11-03 16:29:35 +010034#include <mach/smemc.h>
Rob Herring4e611092012-01-03 16:53:48 -060035#include <mach/irqs.h>
eric miao2c8086a2007-09-11 19:13:17 -070036
37#include "generic.h"
38#include "devices.h"
39#include "clock.h"
40
Mike Rapoportbf293ae2009-11-11 11:36:59 +020041#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
42#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
43
Daniel Mack089d0362012-07-22 19:50:22 +020044extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
45
Russell King8c3abc72008-11-08 20:25:21 +000046static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
47static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
48static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
49static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
50static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
51static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
Igor Grinberge68750a2009-11-04 14:14:39 +020052static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
Russell King8c3abc72008-11-08 20:25:21 +000053static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
54static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
55static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
56static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
57static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
58static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
59static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
60static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
61static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
Haojian Zhuang389eda12011-10-17 21:26:55 +080062static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
Russell King8c3abc72008-11-08 20:25:21 +000063
Eric Miao2e8581e2010-11-22 09:41:39 +080064static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
Eric Miaoc0850522010-11-29 22:56:00 +080065static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
Eric Miao2e8581e2010-11-22 09:41:39 +080066static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
67static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
Eric Miao40298132010-11-22 10:49:55 +080068static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
Eric Miao2e8581e2010-11-22 09:41:39 +080069
Russell King8c3abc72008-11-08 20:25:21 +000070static struct clk_lookup pxa3xx_clkregs[] = {
71 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
Mike Rapoport9ba63c42008-08-17 06:23:05 +010072 /* Power I2C clock is always on */
Daniel Mack5c68b092009-06-22 21:01:58 +020073 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
Russell King8c3abc72008-11-08 20:25:21 +000074 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
75 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
76 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
77 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
78 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
79 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
80 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
81 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
82 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
83 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
Igor Grinberg69f22be2010-07-27 15:06:58 +030084 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
Russell King8c3abc72008-11-08 20:25:21 +000085 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
86 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
87 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
88 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
89 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
90 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
91 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
92 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
93 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
Eric Miaoc0850522010-11-29 22:56:00 +080094 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
Haojian Zhuang2cab0292013-04-07 16:44:33 +080095 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
96 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
Haojian Zhuang3e12ec72012-02-21 12:54:57 +080097 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
eric miao2c8086a2007-09-11 19:13:17 -070098};
99
Russell King7b5dea12008-01-07 22:18:30 +0000100#ifdef CONFIG_PM
Russell King7b5dea12008-01-07 22:18:30 +0000101
102#define ISRAM_START 0x5c000000
103#define ISRAM_SIZE SZ_256K
104
105static void __iomem *sram;
106static unsigned long wakeup_src;
107
Russell King7b5dea12008-01-07 22:18:30 +0000108/*
109 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
110 * memory controller has to be reinitialised, so we place some code
111 * in the SRAM to perform this function.
112 *
113 * We disable FIQs across the standby - otherwise, we might receive a
114 * FIQ while the SDRAM is unavailable.
115 */
116static void pxa3xx_cpu_standby(unsigned int pwrmode)
117{
118 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
119 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
120
121 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
122 pm_enter_standby_end - pm_enter_standby_start);
123
124 AD2D0SR = ~0;
125 AD2D1SR = ~0;
126 AD2D0ER = wakeup_src;
127 AD2D1ER = 0;
128 ASCR = ASCR;
129 ARSR = ARSR;
130
131 local_fiq_disable();
132 fn(pwrmode);
133 local_fiq_enable();
134
135 AD2D0ER = 0;
136 AD2D1ER = 0;
Russell King7b5dea12008-01-07 22:18:30 +0000137}
138
eric miaoc4d1fb62008-01-28 23:00:02 +0000139/*
140 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
141 * PXA3xx development kits assumes that the resuming process continues
142 * with the address stored within the first 4 bytes of SDRAM. The PSPR
143 * register is used privately by BootROM and OBM, and _must_ be set to
144 * 0x5c014000 for the moment.
145 */
146static void pxa3xx_cpu_pm_suspend(void)
147{
148 volatile unsigned long *p = (volatile void *)0xc0000000;
149 unsigned long saved_data = *p;
Russell Kinga9503d22011-06-21 16:29:30 +0100150#ifndef CONFIG_IWMMXT
151 u64 acc0;
eric miaoc4d1fb62008-01-28 23:00:02 +0000152
Russell Kinga9503d22011-06-21 16:29:30 +0100153 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
154#endif
155
Russell King29cb3cd2011-07-02 09:54:01 +0100156 extern int pxa3xx_finish_suspend(unsigned long);
eric miaoc4d1fb62008-01-28 23:00:02 +0000157
158 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
159 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
160 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
161
162 /* clear and setup wakeup source */
163 AD3SR = ~0;
164 AD3ER = wakeup_src;
165 ASCR = ASCR;
166 ARSR = ARSR;
167
168 PCFR |= (1u << 13); /* L1_DIS */
169 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
170
171 PSPR = 0x5c014000;
172
173 /* overwrite with the resume address */
Russell King4f5ad992011-02-06 17:41:26 +0000174 *p = virt_to_phys(cpu_resume);
eric miaoc4d1fb62008-01-28 23:00:02 +0000175
Russell King2c74a0c2011-06-22 17:41:48 +0100176 cpu_suspend(0, pxa3xx_finish_suspend);
eric miaoc4d1fb62008-01-28 23:00:02 +0000177
178 *p = saved_data;
179
180 AD3ER = 0;
Russell Kinga9503d22011-06-21 16:29:30 +0100181
182#ifndef CONFIG_IWMMXT
183 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
184#endif
eric miaoc4d1fb62008-01-28 23:00:02 +0000185}
186
Russell King7b5dea12008-01-07 22:18:30 +0000187static void pxa3xx_cpu_pm_enter(suspend_state_t state)
188{
189 /*
190 * Don't sleep if no wakeup sources are defined
191 */
Mark Brownb86a5da2008-04-09 11:32:21 +0100192 if (wakeup_src == 0) {
193 printk(KERN_ERR "Not suspending: no wakeup sources\n");
Russell King7b5dea12008-01-07 22:18:30 +0000194 return;
Mark Brownb86a5da2008-04-09 11:32:21 +0100195 }
Russell King7b5dea12008-01-07 22:18:30 +0000196
197 switch (state) {
198 case PM_SUSPEND_STANDBY:
199 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
200 break;
201
202 case PM_SUSPEND_MEM:
eric miaoc4d1fb62008-01-28 23:00:02 +0000203 pxa3xx_cpu_pm_suspend();
Russell King7b5dea12008-01-07 22:18:30 +0000204 break;
205 }
206}
207
208static int pxa3xx_cpu_pm_valid(suspend_state_t state)
209{
210 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
211}
212
213static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
Russell King7b5dea12008-01-07 22:18:30 +0000214 .valid = pxa3xx_cpu_pm_valid,
215 .enter = pxa3xx_cpu_pm_enter,
216};
217
218static void __init pxa3xx_init_pm(void)
219{
220 sram = ioremap(ISRAM_START, ISRAM_SIZE);
221 if (!sram) {
222 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
223 return;
224 }
225
226 /*
227 * Since we copy wakeup code into the SRAM, we need to ensure
228 * that it is preserved over the low power modes. Note: bit 8
229 * is undocumented in the developer manual, but must be set.
230 */
231 AD1R |= ADXR_L2 | ADXR_R0;
232 AD2R |= ADXR_L2 | ADXR_R0;
233 AD3R |= ADXR_L2 | ADXR_R0;
234
235 /*
236 * Clear the resume enable registers.
237 */
238 AD1D0ER = 0;
239 AD2D0ER = 0;
240 AD2D1ER = 0;
241 AD3ER = 0;
242
243 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
244}
245
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100246static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
Russell King7b5dea12008-01-07 22:18:30 +0000247{
248 unsigned long flags, mask = 0;
249
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100250 switch (d->irq) {
Russell King7b5dea12008-01-07 22:18:30 +0000251 case IRQ_SSP3:
252 mask = ADXER_MFP_WSSP3;
253 break;
254 case IRQ_MSL:
255 mask = ADXER_WMSL0;
256 break;
257 case IRQ_USBH2:
258 case IRQ_USBH1:
259 mask = ADXER_WUSBH;
260 break;
261 case IRQ_KEYPAD:
262 mask = ADXER_WKP;
263 break;
264 case IRQ_AC97:
265 mask = ADXER_MFP_WAC97;
266 break;
267 case IRQ_USIM:
268 mask = ADXER_WUSIM0;
269 break;
270 case IRQ_SSP2:
271 mask = ADXER_MFP_WSSP2;
272 break;
273 case IRQ_I2C:
274 mask = ADXER_MFP_WI2C;
275 break;
276 case IRQ_STUART:
277 mask = ADXER_MFP_WUART3;
278 break;
279 case IRQ_BTUART:
280 mask = ADXER_MFP_WUART2;
281 break;
282 case IRQ_FFUART:
283 mask = ADXER_MFP_WUART1;
284 break;
285 case IRQ_MMC:
286 mask = ADXER_MFP_WMMC1;
287 break;
288 case IRQ_SSP:
289 mask = ADXER_MFP_WSSP1;
290 break;
291 case IRQ_RTCAlrm:
292 mask = ADXER_WRTC;
293 break;
294 case IRQ_SSP4:
295 mask = ADXER_MFP_WSSP4;
296 break;
297 case IRQ_TSI:
298 mask = ADXER_WTSI;
299 break;
300 case IRQ_USIM2:
301 mask = ADXER_WUSIM1;
302 break;
303 case IRQ_MMC2:
304 mask = ADXER_MFP_WMMC2;
305 break;
306 case IRQ_NAND:
307 mask = ADXER_MFP_WFLASH;
308 break;
309 case IRQ_USB2:
310 mask = ADXER_WUSB2;
311 break;
312 case IRQ_WAKEUP0:
313 mask = ADXER_WEXTWAKE0;
314 break;
315 case IRQ_WAKEUP1:
316 mask = ADXER_WEXTWAKE1;
317 break;
318 case IRQ_MMC3:
319 mask = ADXER_MFP_GEN12;
320 break;
Mark Browne1217702008-04-23 10:28:18 +0100321 default:
322 return -EINVAL;
Russell King7b5dea12008-01-07 22:18:30 +0000323 }
324
325 local_irq_save(flags);
326 if (on)
327 wakeup_src |= mask;
328 else
329 wakeup_src &= ~mask;
330 local_irq_restore(flags);
331
332 return 0;
333}
Russell King7b5dea12008-01-07 22:18:30 +0000334#else
335static inline void pxa3xx_init_pm(void) {}
eric miaob9e25ac2008-03-04 14:19:58 +0800336#define pxa3xx_set_wake NULL
Russell King7b5dea12008-01-07 22:18:30 +0000337#endif
338
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100339static void pxa_ack_ext_wakeup(struct irq_data *d)
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200340{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100341 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200342}
343
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100344static void pxa_mask_ext_wakeup(struct irq_data *d)
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200345{
Eric Miao5d284e32011-04-27 22:48:04 +0800346 pxa_mask_irq(d);
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100347 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200348}
349
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100350static void pxa_unmask_ext_wakeup(struct irq_data *d)
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200351{
Eric Miao5d284e32011-04-27 22:48:04 +0800352 pxa_unmask_irq(d);
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100353 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200354}
355
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100356static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
Igor Grinberg12882092010-06-13 11:31:48 +0300357{
358 if (flow_type & IRQ_TYPE_EDGE_RISING)
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100359 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
Igor Grinberg12882092010-06-13 11:31:48 +0300360
361 if (flow_type & IRQ_TYPE_EDGE_FALLING)
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100362 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
Igor Grinberg12882092010-06-13 11:31:48 +0300363
364 return 0;
365}
366
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200367static struct irq_chip pxa_ext_wakeup_chip = {
368 .name = "WAKEUP",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100369 .irq_ack = pxa_ack_ext_wakeup,
370 .irq_mask = pxa_mask_ext_wakeup,
371 .irq_unmask = pxa_unmask_ext_wakeup,
372 .irq_set_type = pxa_set_ext_wakeup_type,
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200373};
374
Haojian Zhuang157d2642011-10-17 20:37:52 +0800375static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
376 unsigned int))
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200377{
378 int irq;
379
380 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100381 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
382 handle_edge_irq);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200383 set_irq_flags(irq, IRQF_VALID);
384 }
385
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100386 pxa_ext_wakeup_chip.irq_set_wake = fn;
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200387}
388
Daniel Mack089d0362012-07-22 19:50:22 +0200389static void __init __pxa3xx_init_irq(void)
eric miao2c8086a2007-09-11 19:13:17 -0700390{
391 /* enable CP6 access */
392 u32 value;
393 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
394 value |= (1 << 6);
395 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
396
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200397 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
eric miao2c8086a2007-09-11 19:13:17 -0700398}
399
Daniel Mack089d0362012-07-22 19:50:22 +0200400void __init pxa3xx_init_irq(void)
401{
402 __pxa3xx_init_irq();
403 pxa_init_irq(56, pxa3xx_set_wake);
404}
405
Haojian Zhuange6c509c2012-08-20 13:46:51 +0800406#ifdef CONFIG_OF
Daniel Mack089d0362012-07-22 19:50:22 +0200407void __init pxa3xx_dt_init_irq(void)
408{
409 __pxa3xx_init_irq();
410 pxa_dt_irq_init(pxa3xx_set_wake);
411}
Haojian Zhuange6c509c2012-08-20 13:46:51 +0800412#endif /* CONFIG_OF */
Daniel Mack089d0362012-07-22 19:50:22 +0200413
Marek Vasut851982c2010-10-11 02:20:19 +0200414static struct map_desc pxa3xx_io_desc[] __initdata = {
415 { /* Mem Ctl */
Arnd Bergmann97b09da2011-10-01 22:03:45 +0200416 .virtual = (unsigned long)SMEMC_VIRT,
Marek Vasutad68bb92010-11-03 16:29:35 +0100417 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
Marek Vasut851982c2010-10-11 02:20:19 +0200418 .length = 0x00200000,
419 .type = MT_DEVICE
420 }
421};
422
423void __init pxa3xx_map_io(void)
424{
425 pxa_map_io();
426 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
427 pxa3xx_get_clk_frequency_khz(1);
428}
429
eric miao2c8086a2007-09-11 19:13:17 -0700430/*
431 * device registration specific to PXA3xx.
432 */
433
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100434void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
435{
Eric Miao14758222008-11-28 15:24:12 +0800436 pxa_register_device(&pxa3xx_device_i2c_power, info);
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100437}
438
eric miao2c8086a2007-09-11 19:13:17 -0700439static struct platform_device *devices[] __initdata = {
Robert Jarzmik94c35a62009-04-21 19:19:36 +0200440 &pxa27x_device_udc,
Eric Miao09a53582010-06-14 00:43:00 +0800441 &pxa_device_pmu,
eric miao2c8086a2007-09-11 19:13:17 -0700442 &pxa_device_i2s,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000443 &pxa_device_asoc_ssp1,
444 &pxa_device_asoc_ssp2,
445 &pxa_device_asoc_ssp3,
446 &pxa_device_asoc_ssp4,
447 &pxa_device_asoc_platform,
Robert Jarzmik72493142008-11-13 23:50:56 +0100448 &sa1100_device_rtc,
eric miao2c8086a2007-09-11 19:13:17 -0700449 &pxa_device_rtc,
eric miaod8e0db12007-12-10 17:54:36 +0800450 &pxa27x_device_ssp1,
451 &pxa27x_device_ssp2,
452 &pxa27x_device_ssp3,
453 &pxa3xx_device_ssp4,
eric miao75540c12008-04-13 21:44:04 +0100454 &pxa27x_device_pwm0,
455 &pxa27x_device_pwm1,
eric miao2c8086a2007-09-11 19:13:17 -0700456};
457
458static int __init pxa3xx_init(void)
459{
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200460 int ret = 0;
eric miao2c8086a2007-09-11 19:13:17 -0700461
462 if (cpu_is_pxa3xx()) {
Eric Miao04fef222008-07-29 14:26:00 +0800463
464 reset_status = ARSR;
465
Dmitry Krivoschekov86260f92008-02-08 15:02:03 +0100466 /*
467 * clear RDH bit every time after reset
468 *
469 * Note: the last 3 bits DxS are write-1-to-clear so carefully
470 * preserve them here in case they will be referenced later
471 */
472 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
473
Russell King0a0300d2010-01-12 12:28:00 +0000474 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
eric miao2c8086a2007-09-11 19:13:17 -0700475
Eric Miaofef1f992009-01-02 16:26:33 +0800476 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
eric miao2c8086a2007-09-11 19:13:17 -0700477 return ret;
478
Russell King7b5dea12008-01-07 22:18:30 +0000479 pxa3xx_init_pm();
480
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200481 register_syscore_ops(&pxa_irq_syscore_ops);
482 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200483 register_syscore_ops(&pxa3xx_clock_syscore_ops);
eric miaoc01655042008-01-28 23:00:02 +0000484
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800485 if (of_have_populated_dt())
486 return 0;
487
488 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
489 if (ret)
490 return ret;
491 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320())
492 ret = platform_device_register(&pxa3xx_device_gpio);
eric miao2c8086a2007-09-11 19:13:17 -0700493 }
eric miaoc01655042008-01-28 23:00:02 +0000494
495 return ret;
eric miao2c8086a2007-09-11 19:13:17 -0700496}
497
Russell King1c104e02008-04-19 10:59:24 +0100498postcore_initcall(pxa3xx_init);