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gerrit-public.fairphone.software / kernel / msm-4.19 / 1f152b48eaaf4918047e84777b01a6d687f066e9 / . / arch / arm / mach-imx / clk-imx31.c
blob: a854b9cae5ea505f3c2586224eb1f12651ffad93 [file] [log] [blame]
Sascha Hauer95878cb2012-03-18 23:48:35 +0100[diff] [blame]1/*
2 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/clk.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22#include <linux/err.h>
23
24#include <mach/hardware.h>
25#include <mach/mx31.h>
26#include <mach/common.h>
27
28#include "clk.h"
29#include "crmregs-imx3.h"
30
31static const char *mcu_main_sel[] = { "spll", "mpll", };
32static const char *per_sel[] = { "per_div", "ipg", };
33static const char *csi_sel[] = { "upll", "spll", };
34static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
35
36enum mx31_clks {
37 ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
38 per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
39 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
40 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
41 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
42 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
43 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
44 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
45 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
46};
47
48static struct clk *clk[clk_max];
49
50int __init mx31_clocks_init(unsigned long fref)
51{
52 void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
53 int i;
54
55 clk[ckih] = imx_clk_fixed("ckih", fref);
56 clk[ckil] = imx_clk_fixed("ckil", 32768);
57 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
58 clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL);
59 clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL);
60 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
61 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
62 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
63 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
64 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
65 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
66 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
67 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
68 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
69 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
70 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
71 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
72 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
73 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
74 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
75 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
76 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
77 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
78 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
79 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
80 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
81 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
82 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
83 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
84 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
85 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
86 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
87 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
88 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
89 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
90 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
91 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
92 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
93 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
94 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
95 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
96 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
97 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
98 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
99 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
100 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
101 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
102 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
103 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
104 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
105 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
106 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
107 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
108 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
109 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
110 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
111 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
112 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
113
114 for (i = 0; i < ARRAY_SIZE(clk); i++)
115 if (IS_ERR(clk[i]))
116 pr_err("imx31 clk %d: register failed with %ld\n",
117 i, PTR_ERR(clk[i]));
118
119 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
120 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
121 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
122 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
123 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
124 clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
125 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
126 clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
127 clk_register_clkdev(clk[epit1_gate], "epit", NULL);
128 clk_register_clkdev(clk[epit2_gate], "epit", NULL);
129 clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
130 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
131 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
132 clk_register_clkdev(clk[kpp_gate], "kpp", NULL);
133 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
134 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
135 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
136 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
137 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
138 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
139 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
140 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
141 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
142 clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
143 clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
144 clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
145 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
146 /* i.mx31 has the i.mx21 type uart */
147 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
148 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
149 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
150 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
151 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
152 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
153 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
154 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
155 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
156 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
157 clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
158 clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
159 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
160 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
161 clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
162 clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
163 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
164 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
165 clk_register_clkdev(clk[firi_gate], "firi", NULL);
166 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
167 clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
168 clk_register_clkdev(clk[rng_gate], "rng", NULL);
169 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
170 clk_register_clkdev(clk[iim_gate], "iim", NULL);
171
172 clk_set_parent(clk[csi], clk[upll]);
173 clk_prepare_enable(clk[emi_gate]);
174 clk_prepare_enable(clk[iim_gate]);
175 mx31_revision();
176 clk_disable_unprepare(clk[iim_gate]);
177
178 mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
179 MX31_INT_GPT);
180
181 return 0;
182}